1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/phy/phy.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/clock/axg-audio-clkc.h>
9#include <dt-bindings/clock/g12a-clkc.h>
10#include <dt-bindings/clock/g12a-aoclkc.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
15
16/ {
17	compatible = "amlogic,g12a";
18
19	interrupt-parent = <&gic>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	cpus {
24		#address-cells = <0x2>;
25		#size-cells = <0x0>;
26
27		cpu0: cpu@0 {
28			device_type = "cpu";
29			compatible = "arm,cortex-a53";
30			reg = <0x0 0x0>;
31			enable-method = "psci";
32			next-level-cache = <&l2>;
33		};
34
35		cpu1: cpu@1 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a53";
38			reg = <0x0 0x1>;
39			enable-method = "psci";
40			next-level-cache = <&l2>;
41		};
42
43		cpu2: cpu@2 {
44			device_type = "cpu";
45			compatible = "arm,cortex-a53";
46			reg = <0x0 0x2>;
47			enable-method = "psci";
48			next-level-cache = <&l2>;
49		};
50
51		cpu3: cpu@3 {
52			device_type = "cpu";
53			compatible = "arm,cortex-a53";
54			reg = <0x0 0x3>;
55			enable-method = "psci";
56			next-level-cache = <&l2>;
57		};
58
59		l2: l2-cache0 {
60			compatible = "cache";
61		};
62	};
63
64	efuse: efuse {
65		compatible = "amlogic,meson-gxbb-efuse";
66		clocks = <&clkc CLKID_EFUSE>;
67		#address-cells = <1>;
68		#size-cells = <1>;
69		read-only;
70	};
71
72	psci {
73		compatible = "arm,psci-1.0";
74		method = "smc";
75	};
76
77	reserved-memory {
78		#address-cells = <2>;
79		#size-cells = <2>;
80		ranges;
81
82		/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
83		secmon_reserved: secmon@5000000 {
84			reg = <0x0 0x05000000 0x0 0x300000>;
85			no-map;
86		};
87
88		linux,cma {
89			compatible = "shared-dma-pool";
90			reusable;
91			size = <0x0 0x10000000>;
92			alignment = <0x0 0x400000>;
93			linux,cma-default;
94		};
95	};
96
97	sm: secure-monitor {
98		compatible = "amlogic,meson-gxbb-sm";
99	};
100
101	soc {
102		compatible = "simple-bus";
103		#address-cells = <2>;
104		#size-cells = <2>;
105		ranges;
106
107		apb: bus@ff600000 {
108			compatible = "simple-bus";
109			reg = <0x0 0xff600000 0x0 0x200000>;
110			#address-cells = <2>;
111			#size-cells = <2>;
112			ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
113
114			hdmi_tx: hdmi-tx@0 {
115				compatible = "amlogic,meson-g12a-dw-hdmi";
116				reg = <0x0 0x0 0x0 0x10000>;
117				interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
118				resets = <&reset RESET_HDMITX_CAPB3>,
119					 <&reset RESET_HDMITX_PHY>,
120					 <&reset RESET_HDMITX>;
121				reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
122				clocks = <&clkc CLKID_HDMI>,
123					 <&clkc CLKID_HTX_PCLK>,
124					 <&clkc CLKID_VPU_INTR>;
125				clock-names = "isfr", "iahb", "venci";
126				#address-cells = <1>;
127				#size-cells = <0>;
128				status = "disabled";
129
130				/* VPU VENC Input */
131				hdmi_tx_venc_port: port@0 {
132					reg = <0>;
133
134					hdmi_tx_in: endpoint {
135						remote-endpoint = <&hdmi_tx_out>;
136					};
137				};
138
139				/* TMDS Output */
140				hdmi_tx_tmds_port: port@1 {
141					reg = <1>;
142				};
143			};
144
145			periphs: bus@34400 {
146				compatible = "simple-bus";
147				reg = <0x0 0x34400 0x0 0x400>;
148				#address-cells = <2>;
149				#size-cells = <2>;
150				ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
151
152				periphs_pinctrl: pinctrl@40 {
153					compatible = "amlogic,meson-g12a-periphs-pinctrl";
154					#address-cells = <2>;
155					#size-cells = <2>;
156					ranges;
157
158					gpio: bank@40 {
159						reg = <0x0 0x40  0x0 0x4c>,
160						      <0x0 0xe8  0x0 0x18>,
161						      <0x0 0x120 0x0 0x18>,
162						      <0x0 0x2c0 0x0 0x40>,
163						      <0x0 0x340 0x0 0x1c>;
164						reg-names = "gpio",
165							    "pull",
166							    "pull-enable",
167							    "mux",
168							    "ds";
169						gpio-controller;
170						#gpio-cells = <2>;
171						gpio-ranges = <&periphs_pinctrl 0 0 86>;
172					};
173
174					cec_ao_a_h_pins: cec_ao_a_h {
175						mux {
176							groups = "cec_ao_a_h";
177							function = "cec_ao_a_h";
178							bias-disable;
179						};
180					};
181
182					cec_ao_b_h_pins: cec_ao_b_h {
183						mux {
184							groups = "cec_ao_b_h";
185							function = "cec_ao_b_h";
186							bias-disable;
187						};
188					};
189
190					emmc_pins: emmc {
191						mux-0 {
192							groups = "emmc_nand_d0",
193								 "emmc_nand_d1",
194								 "emmc_nand_d2",
195								 "emmc_nand_d3",
196								 "emmc_nand_d4",
197								 "emmc_nand_d5",
198								 "emmc_nand_d6",
199								 "emmc_nand_d7",
200								 "emmc_cmd";
201							function = "emmc";
202							bias-pull-up;
203							drive-strength-microamp = <4000>;
204						};
205
206						mux-1 {
207							groups = "emmc_clk";
208							function = "emmc";
209							bias-disable;
210							drive-strength-microamp = <4000>;
211						};
212					};
213
214					emmc_ds_pins: emmc-ds {
215						mux {
216							groups = "emmc_nand_ds";
217							function = "emmc";
218							bias-pull-down;
219							drive-strength-microamp = <4000>;
220						};
221					};
222
223					emmc_clk_gate_pins: emmc_clk_gate {
224						mux {
225							groups = "BOOT_8";
226							function = "gpio_periphs";
227							bias-pull-down;
228							drive-strength-microamp = <4000>;
229						};
230					};
231
232					hdmitx_ddc_pins: hdmitx_ddc {
233						mux {
234							groups = "hdmitx_sda",
235								 "hdmitx_sck";
236							function = "hdmitx";
237							bias-disable;
238						};
239					};
240
241					hdmitx_hpd_pins: hdmitx_hpd {
242						mux {
243							groups = "hdmitx_hpd_in";
244							function = "hdmitx";
245							bias-disable;
246						};
247					};
248
249
250					i2c0_sda_c_pins: i2c0-sda-c {
251						mux {
252							groups = "i2c0_sda_c";
253							function = "i2c0";
254							bias-disable;
255							drive-strength-microamp = <3000>;
256
257						};
258					};
259
260					i2c0_sck_c_pins: i2c0-sck-c {
261						mux {
262							groups = "i2c0_sck_c";
263							function = "i2c0";
264							bias-disable;
265							drive-strength-microamp = <3000>;
266						};
267					};
268
269					i2c0_sda_z0_pins: i2c0-sda-z0 {
270						mux {
271							groups = "i2c0_sda_z0";
272							function = "i2c0";
273							bias-disable;
274							drive-strength-microamp = <3000>;
275						};
276					};
277
278					i2c0_sck_z1_pins: i2c0-sck-z1 {
279						mux {
280							groups = "i2c0_sck_z1";
281							function = "i2c0";
282							bias-disable;
283							drive-strength-microamp = <3000>;
284						};
285					};
286
287					i2c0_sda_z7_pins: i2c0-sda-z7 {
288						mux {
289							groups = "i2c0_sda_z7";
290							function = "i2c0";
291							bias-disable;
292							drive-strength-microamp = <3000>;
293						};
294					};
295
296					i2c0_sda_z8_pins: i2c0-sda-z8 {
297						mux {
298							groups = "i2c0_sda_z8";
299							function = "i2c0";
300							bias-disable;
301							drive-strength-microamp = <3000>;
302						};
303					};
304
305					i2c1_sda_x_pins: i2c1-sda-x {
306						mux {
307							groups = "i2c1_sda_x";
308							function = "i2c1";
309							bias-disable;
310							drive-strength-microamp = <3000>;
311						};
312					};
313
314					i2c1_sck_x_pins: i2c1-sck-x {
315						mux {
316							groups = "i2c1_sck_x";
317							function = "i2c1";
318							bias-disable;
319							drive-strength-microamp = <3000>;
320						};
321					};
322
323					i2c1_sda_h2_pins: i2c1-sda-h2 {
324						mux {
325							groups = "i2c1_sda_h2";
326							function = "i2c1";
327							bias-disable;
328							drive-strength-microamp = <3000>;
329						};
330					};
331
332					i2c1_sck_h3_pins: i2c1-sck-h3 {
333						mux {
334							groups = "i2c1_sck_h3";
335							function = "i2c1";
336							bias-disable;
337							drive-strength-microamp = <3000>;
338						};
339					};
340
341					i2c1_sda_h6_pins: i2c1-sda-h6 {
342						mux {
343							groups = "i2c1_sda_h6";
344							function = "i2c1";
345							bias-disable;
346							drive-strength-microamp = <3000>;
347						};
348					};
349
350					i2c1_sck_h7_pins: i2c1-sck-h7 {
351						mux {
352							groups = "i2c1_sck_h7";
353							function = "i2c1";
354							bias-disable;
355							drive-strength-microamp = <3000>;
356						};
357					};
358
359					i2c2_sda_x_pins: i2c2-sda-x {
360						mux {
361							groups = "i2c2_sda_x";
362							function = "i2c2";
363							bias-disable;
364							drive-strength-microamp = <3000>;
365						};
366					};
367
368					i2c2_sck_x_pins: i2c2-sck-x {
369						mux {
370							groups = "i2c2_sck_x";
371							function = "i2c2";
372							bias-disable;
373							drive-strength-microamp = <3000>;
374						};
375					};
376
377					i2c2_sda_z_pins: i2c2-sda-z {
378						mux {
379							groups = "i2c2_sda_z";
380							function = "i2c2";
381							bias-disable;
382							drive-strength-microamp = <3000>;
383						};
384					};
385
386					i2c2_sck_z_pins: i2c2-sck-z {
387						mux {
388							groups = "i2c2_sck_z";
389							function = "i2c2";
390							bias-disable;
391							drive-strength-microamp = <3000>;
392						};
393					};
394
395					i2c3_sda_h_pins: i2c3-sda-h {
396						mux {
397							groups = "i2c3_sda_h";
398							function = "i2c3";
399							bias-disable;
400							drive-strength-microamp = <3000>;
401						};
402					};
403
404					i2c3_sck_h_pins: i2c3-sck-h {
405						mux {
406							groups = "i2c3_sck_h";
407							function = "i2c3";
408							bias-disable;
409							drive-strength-microamp = <3000>;
410						};
411					};
412
413					i2c3_sda_a_pins: i2c3-sda-a {
414						mux {
415							groups = "i2c3_sda_a";
416							function = "i2c3";
417							bias-disable;
418							drive-strength-microamp = <3000>;
419						};
420					};
421
422					i2c3_sck_a_pins: i2c3-sck-a {
423						mux {
424							groups = "i2c3_sck_a";
425							function = "i2c3";
426							bias-disable;
427							drive-strength-microamp = <3000>;
428						};
429					};
430
431					pwm_a_pins: pwm-a {
432						mux {
433							groups = "pwm_a";
434							function = "pwm_a";
435							bias-disable;
436						};
437					};
438
439					pwm_b_x7_pins: pwm-b-x7 {
440						mux {
441							groups = "pwm_b_x7";
442							function = "pwm_b";
443							bias-disable;
444						};
445					};
446
447					pwm_b_x19_pins: pwm-b-x19 {
448						mux {
449							groups = "pwm_b_x19";
450							function = "pwm_b";
451							bias-disable;
452						};
453					};
454
455					pwm_c_c_pins: pwm-c-c {
456						mux {
457							groups = "pwm_c_c";
458							function = "pwm_c";
459							bias-disable;
460						};
461					};
462
463					pwm_c_x5_pins: pwm-c-x5 {
464						mux {
465							groups = "pwm_c_x5";
466							function = "pwm_c";
467							bias-disable;
468						};
469					};
470
471					pwm_c_x8_pins: pwm-c-x8 {
472						mux {
473							groups = "pwm_c_x8";
474							function = "pwm_c";
475							bias-disable;
476						};
477					};
478
479					pwm_d_x3_pins: pwm-d-x3 {
480						mux {
481							groups = "pwm_d_x3";
482							function = "pwm_d";
483							bias-disable;
484						};
485					};
486
487					pwm_d_x6_pins: pwm-d-x6 {
488						mux {
489							groups = "pwm_d_x6";
490							function = "pwm_d";
491							bias-disable;
492						};
493					};
494
495					pwm_e_pins: pwm-e {
496						mux {
497							groups = "pwm_e";
498							function = "pwm_e";
499							bias-disable;
500						};
501					};
502
503					pwm_f_x_pins: pwm-f-x {
504						mux {
505							groups = "pwm_f_x";
506							function = "pwm_f";
507							bias-disable;
508						};
509					};
510
511					pwm_f_h_pins: pwm-f-h {
512						mux {
513							groups = "pwm_f_h";
514							function = "pwm_f";
515							bias-disable;
516						};
517					};
518
519					sdcard_c_pins: sdcard_c {
520						mux-0 {
521							groups = "sdcard_d0_c",
522								 "sdcard_d1_c",
523								 "sdcard_d2_c",
524								 "sdcard_d3_c",
525								 "sdcard_cmd_c";
526							function = "sdcard";
527							bias-pull-up;
528							drive-strength-microamp = <4000>;
529						};
530
531						mux-1 {
532							groups = "sdcard_clk_c";
533							function = "sdcard";
534							bias-disable;
535							drive-strength-microamp = <4000>;
536						};
537					};
538
539					sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
540						mux {
541							groups = "GPIOC_4";
542							function = "gpio_periphs";
543							bias-pull-down;
544							drive-strength-microamp = <4000>;
545						};
546					};
547
548					sdcard_z_pins: sdcard_z {
549						mux-0 {
550							groups = "sdcard_d0_z",
551								 "sdcard_d1_z",
552								 "sdcard_d2_z",
553								 "sdcard_d3_z",
554								 "sdcard_cmd_z";
555							function = "sdcard";
556							bias-pull-up;
557							drive-strength-microamp = <4000>;
558						};
559
560						mux-1 {
561							groups = "sdcard_clk_z";
562							function = "sdcard";
563							bias-disable;
564							drive-strength-microamp = <4000>;
565						};
566					};
567
568					sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
569						mux {
570							groups = "GPIOZ_6";
571							function = "gpio_periphs";
572							bias-pull-down;
573							drive-strength-microamp = <4000>;
574						};
575					};
576
577					uart_a_pins: uart-a {
578						mux {
579							groups = "uart_a_tx",
580								 "uart_a_rx";
581							function = "uart_a";
582							bias-disable;
583						};
584					};
585
586					uart_a_cts_rts_pins: uart-a-cts-rts {
587						mux {
588							groups = "uart_a_cts",
589								 "uart_a_rts";
590							function = "uart_a";
591							bias-disable;
592						};
593					};
594
595					uart_b_pins: uart-b {
596						mux {
597							groups = "uart_b_tx",
598								 "uart_b_rx";
599							function = "uart_b";
600							bias-disable;
601						};
602					};
603
604					uart_c_pins: uart-c {
605						mux {
606							groups = "uart_c_tx",
607								 "uart_c_rx";
608							function = "uart_c";
609							bias-disable;
610						};
611					};
612
613					uart_c_cts_rts_pins: uart-c-cts-rts {
614						mux {
615							groups = "uart_c_cts",
616								 "uart_c_rts";
617							function = "uart_c";
618							bias-disable;
619						};
620					};
621				};
622			};
623
624			usb2_phy0: phy@36000 {
625				compatible = "amlogic,g12a-usb2-phy";
626				reg = <0x0 0x36000 0x0 0x2000>;
627				clocks = <&xtal>;
628				clock-names = "xtal";
629				resets = <&reset RESET_USB_PHY20>;
630				reset-names = "phy";
631				#phy-cells = <0>;
632			};
633
634			dmc: bus@38000 {
635				compatible = "simple-bus";
636				reg = <0x0 0x38000 0x0 0x400>;
637				#address-cells = <2>;
638				#size-cells = <2>;
639				ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
640
641				canvas: video-lut@48 {
642					compatible = "amlogic,canvas";
643					reg = <0x0 0x48 0x0 0x14>;
644				};
645			};
646
647			usb2_phy1: phy@3a000 {
648				compatible = "amlogic,g12a-usb2-phy";
649				reg = <0x0 0x3a000 0x0 0x2000>;
650				clocks = <&xtal>;
651				clock-names = "xtal";
652				resets = <&reset RESET_USB_PHY21>;
653				reset-names = "phy";
654				#phy-cells = <0>;
655			};
656
657			hiu: bus@3c000 {
658				compatible = "simple-bus";
659				reg = <0x0 0x3c000 0x0 0x1400>;
660				#address-cells = <2>;
661				#size-cells = <2>;
662				ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
663
664				hhi: system-controller@0 {
665					compatible = "amlogic,meson-gx-hhi-sysctrl",
666						     "simple-mfd", "syscon";
667					reg = <0 0 0 0x400>;
668
669					clkc: clock-controller {
670						compatible = "amlogic,g12a-clkc";
671						#clock-cells = <1>;
672						clocks = <&xtal>;
673						clock-names = "xtal";
674					};
675				};
676			};
677
678			audio: bus@42000 {
679				compatible = "simple-bus";
680				reg = <0x0 0x42000 0x0 0x2000>;
681				#address-cells = <2>;
682				#size-cells = <2>;
683				ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>;
684
685				clkc_audio: clock-controller@0 {
686					status = "disabled";
687					compatible = "amlogic,g12a-audio-clkc";
688					reg = <0x0 0x0 0x0 0xb4>;
689					#clock-cells = <1>;
690
691					clocks = <&clkc CLKID_AUDIO>,
692						 <&clkc CLKID_MPLL0>,
693						 <&clkc CLKID_MPLL1>,
694						 <&clkc CLKID_MPLL2>,
695						 <&clkc CLKID_MPLL3>,
696						 <&clkc CLKID_HIFI_PLL>,
697						 <&clkc CLKID_FCLK_DIV3>,
698						 <&clkc CLKID_FCLK_DIV4>,
699						 <&clkc CLKID_GP0_PLL>;
700					clock-names = "pclk",
701						      "mst_in0",
702						      "mst_in1",
703						      "mst_in2",
704						      "mst_in3",
705						      "mst_in4",
706						      "mst_in5",
707						      "mst_in6",
708						      "mst_in7";
709
710					resets = <&reset RESET_AUDIO>;
711				};
712
713				toddr_a: audio-controller@100 {
714					compatible = "amlogic,g12a-toddr",
715						     "amlogic,axg-toddr";
716					reg = <0x0 0x100 0x0 0x1c>;
717					#sound-dai-cells = <0>;
718					sound-name-prefix = "TODDR_A";
719					interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>;
720					clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
721					resets = <&arb AXG_ARB_TODDR_A>;
722					status = "disabled";
723				};
724
725				toddr_b: audio-controller@140 {
726					compatible = "amlogic,g12a-toddr",
727						     "amlogic,axg-toddr";
728					reg = <0x0 0x140 0x0 0x1c>;
729					#sound-dai-cells = <0>;
730					sound-name-prefix = "TODDR_B";
731					interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
732					clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
733					resets = <&arb AXG_ARB_TODDR_B>;
734					status = "disabled";
735				};
736
737				toddr_c: audio-controller@180 {
738					compatible = "amlogic,g12a-toddr",
739						     "amlogic,axg-toddr";
740					reg = <0x0 0x180 0x0 0x1c>;
741					#sound-dai-cells = <0>;
742					sound-name-prefix = "TODDR_C";
743					interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
744					clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
745					resets = <&arb AXG_ARB_TODDR_C>;
746					status = "disabled";
747				};
748
749				frddr_a: audio-controller@1c0 {
750					compatible = "amlogic,g12a-frddr",
751						     "amlogic,axg-frddr";
752					reg = <0x0 0x1c0 0x0 0x1c>;
753					#sound-dai-cells = <0>;
754					sound-name-prefix = "FRDDR_A";
755					interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
756					clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
757					resets = <&arb AXG_ARB_FRDDR_A>;
758					status = "disabled";
759				};
760
761				frddr_b: audio-controller@200 {
762					compatible = "amlogic,g12a-frddr",
763						     "amlogic,axg-frddr";
764					reg = <0x0 0x200 0x0 0x1c>;
765					#sound-dai-cells = <0>;
766					sound-name-prefix = "FRDDR_B";
767					interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
768					clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
769					resets = <&arb AXG_ARB_FRDDR_B>;
770					status = "disabled";
771				};
772
773				frddr_c: audio-controller@240 {
774					compatible = "amlogic,g12a-frddr",
775						     "amlogic,axg-frddr";
776					reg = <0x0 0x240 0x0 0x1c>;
777					#sound-dai-cells = <0>;
778					sound-name-prefix = "FRDDR_C";
779					interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>;
780					clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
781					resets = <&arb AXG_ARB_FRDDR_C>;
782					status = "disabled";
783				};
784
785				arb: reset-controller@280 {
786					status = "disabled";
787					compatible = "amlogic,meson-axg-audio-arb";
788					reg = <0x0 0x280 0x0 0x4>;
789					#reset-cells = <1>;
790					clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
791				};
792			};
793
794			usb3_pcie_phy: phy@46000 {
795				compatible = "amlogic,g12a-usb3-pcie-phy";
796				reg = <0x0 0x46000 0x0 0x2000>;
797				clocks = <&clkc CLKID_PCIE_PLL>;
798				clock-names = "ref_clk";
799				resets = <&reset RESET_PCIE_PHY>;
800				reset-names = "phy";
801				assigned-clocks = <&clkc CLKID_PCIE_PLL>;
802				assigned-clock-rates = <100000000>;
803				#phy-cells = <1>;
804			};
805		};
806
807		aobus: bus@ff800000 {
808			compatible = "simple-bus";
809			reg = <0x0 0xff800000 0x0 0x100000>;
810			#address-cells = <2>;
811			#size-cells = <2>;
812			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
813
814			rti: sys-ctrl@0 {
815				compatible = "amlogic,meson-gx-ao-sysctrl",
816					     "simple-mfd", "syscon";
817				reg = <0x0 0x0 0x0 0x100>;
818				#address-cells = <2>;
819				#size-cells = <2>;
820				ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
821
822				clkc_AO: clock-controller {
823					compatible = "amlogic,meson-g12a-aoclkc";
824					#clock-cells = <1>;
825					#reset-cells = <1>;
826					clocks = <&xtal>, <&clkc CLKID_CLK81>;
827					clock-names = "xtal", "mpeg-clk";
828				};
829
830				pwrc_vpu: power-controller-vpu {
831					compatible = "amlogic,meson-g12a-pwrc-vpu";
832					#power-domain-cells = <0>;
833					amlogic,hhi-sysctrl = <&hhi>;
834					resets = <&reset RESET_VIU>,
835						 <&reset RESET_VENC>,
836						 <&reset RESET_VCBUS>,
837						 <&reset RESET_BT656>,
838						 <&reset RESET_RDMA>,
839						 <&reset RESET_VENCI>,
840						 <&reset RESET_VENCP>,
841						 <&reset RESET_VDAC>,
842						 <&reset RESET_VDI6>,
843						 <&reset RESET_VENCL>,
844						 <&reset RESET_VID_LOCK>;
845					clocks = <&clkc CLKID_VPU>,
846						 <&clkc CLKID_VAPB>;
847					clock-names = "vpu", "vapb";
848					/*
849					 * VPU clocking is provided by two identical clock paths
850					 * VPU_0 and VPU_1 muxed to a single clock by a glitch
851					 * free mux to safely change frequency while running.
852					 * Same for VAPB but with a final gate after the glitch free mux.
853					 */
854					assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
855							  <&clkc CLKID_VPU_0>,
856							  <&clkc CLKID_VPU>, /* Glitch free mux */
857							  <&clkc CLKID_VAPB_0_SEL>,
858							  <&clkc CLKID_VAPB_0>,
859							  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
860					assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
861								 <0>, /* Do Nothing */
862								 <&clkc CLKID_VPU_0>,
863								 <&clkc CLKID_FCLK_DIV4>,
864								 <0>, /* Do Nothing */
865								 <&clkc CLKID_VAPB_0>;
866					assigned-clock-rates = <0>, /* Do Nothing */
867							       <666666666>,
868							       <0>, /* Do Nothing */
869							       <0>, /* Do Nothing */
870							       <250000000>,
871							       <0>; /* Do Nothing */
872				};
873
874				ao_pinctrl: pinctrl@14 {
875					compatible = "amlogic,meson-g12a-aobus-pinctrl";
876					#address-cells = <2>;
877					#size-cells = <2>;
878					ranges;
879
880					gpio_ao: bank@14 {
881						reg = <0x0 0x14 0x0 0x8>,
882						      <0x0 0x1c 0x0 0x8>,
883						      <0x0 0x24 0x0 0x14>;
884						reg-names = "mux",
885							    "ds",
886							    "gpio";
887						gpio-controller;
888						#gpio-cells = <2>;
889						gpio-ranges = <&ao_pinctrl 0 0 15>;
890					};
891
892					i2c_ao_sck_pins: i2c_ao_sck_pins {
893						mux {
894							groups = "i2c_ao_sck";
895							function = "i2c_ao";
896							bias-disable;
897							drive-strength-microamp = <3000>;
898						};
899					};
900
901					i2c_ao_sda_pins: i2c_ao_sda {
902						mux {
903							groups = "i2c_ao_sda";
904							function = "i2c_ao";
905							bias-disable;
906							drive-strength-microamp = <3000>;
907						};
908					};
909
910					i2c_ao_sck_e_pins: i2c_ao_sck_e {
911						mux {
912							groups = "i2c_ao_sck_e";
913							function = "i2c_ao";
914							bias-disable;
915							drive-strength-microamp = <3000>;
916						};
917					};
918
919					i2c_ao_sda_e_pins: i2c_ao_sda_e {
920						mux {
921							groups = "i2c_ao_sda_e";
922							function = "i2c_ao";
923							bias-disable;
924							drive-strength-microamp = <3000>;
925						};
926					};
927
928					uart_ao_a_pins: uart-a-ao {
929						mux {
930							groups = "uart_ao_a_tx",
931								 "uart_ao_a_rx";
932							function = "uart_ao_a";
933							bias-disable;
934						};
935					};
936
937					uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
938						mux {
939							groups = "uart_ao_a_cts",
940								 "uart_ao_a_rts";
941							function = "uart_ao_a";
942							bias-disable;
943						};
944					};
945
946					pwm_ao_a_pins: pwm-ao-a {
947						mux {
948							groups = "pwm_ao_a";
949							function = "pwm_ao_a";
950							bias-disable;
951						};
952					};
953
954					pwm_ao_b_pins: pwm-ao-b {
955						mux {
956							groups = "pwm_ao_b";
957							function = "pwm_ao_b";
958							bias-disable;
959						};
960					};
961
962					pwm_ao_c_4_pins: pwm-ao-c-4 {
963						mux {
964							groups = "pwm_ao_c_4";
965							function = "pwm_ao_c";
966							bias-disable;
967						};
968					};
969
970					pwm_ao_c_6_pins: pwm-ao-c-6 {
971						mux {
972							groups = "pwm_ao_c_6";
973							function = "pwm_ao_c";
974							bias-disable;
975						};
976					};
977
978					pwm_ao_d_5_pins: pwm-ao-d-5 {
979						mux {
980							groups = "pwm_ao_d_5";
981							function = "pwm_ao_d";
982							bias-disable;
983						};
984					};
985
986					pwm_ao_d_10_pins: pwm-ao-d-10 {
987						mux {
988							groups = "pwm_ao_d_10";
989							function = "pwm_ao_d";
990							bias-disable;
991						};
992					};
993
994					pwm_ao_d_e_pins: pwm-ao-d-e {
995						mux {
996							groups = "pwm_ao_d_e";
997							function = "pwm_ao_d";
998						};
999					};
1000
1001					remote_input_ao_pins: remote-input-ao {
1002						mux {
1003							groups = "remote_ao_input";
1004							function = "remote_ao_input";
1005							bias-disable;
1006						};
1007					};
1008				};
1009			};
1010
1011			cec_AO: cec@100 {
1012				compatible = "amlogic,meson-gx-ao-cec";
1013				reg = <0x0 0x00100 0x0 0x14>;
1014				interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
1015				clocks = <&clkc_AO CLKID_AO_CEC>;
1016				clock-names = "core";
1017				status = "disabled";
1018			};
1019
1020			sec_AO: ao-secure@140 {
1021				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1022				reg = <0x0 0x140 0x0 0x140>;
1023				amlogic,has-chip-id;
1024			};
1025
1026			cecb_AO: cec@280 {
1027				compatible = "amlogic,meson-g12a-ao-cec";
1028				reg = <0x0 0x00280 0x0 0x1c>;
1029				interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
1030				clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
1031				clock-names = "oscin";
1032				status = "disabled";
1033			};
1034
1035			pwm_AO_cd: pwm@2000 {
1036				compatible = "amlogic,meson-g12a-ao-pwm-cd";
1037				reg = <0x0 0x2000 0x0 0x20>;
1038				#pwm-cells = <3>;
1039				status = "disabled";
1040			};
1041
1042			uart_AO: serial@3000 {
1043				compatible = "amlogic,meson-gx-uart",
1044					     "amlogic,meson-ao-uart";
1045				reg = <0x0 0x3000 0x0 0x18>;
1046				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1047				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
1048				clock-names = "xtal", "pclk", "baud";
1049				status = "disabled";
1050			};
1051
1052			uart_AO_B: serial@4000 {
1053				compatible = "amlogic,meson-gx-uart",
1054					     "amlogic,meson-ao-uart";
1055				reg = <0x0 0x4000 0x0 0x18>;
1056				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1057				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1058				clock-names = "xtal", "pclk", "baud";
1059				status = "disabled";
1060			};
1061
1062			i2c_AO: i2c@5000 {
1063				compatible = "amlogic,meson-axg-i2c";
1064				status = "disabled";
1065				reg = <0x0 0x05000 0x0 0x20>;
1066				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1067				#address-cells = <1>;
1068				#size-cells = <0>;
1069				clocks = <&clkc CLKID_I2C>;
1070			};
1071
1072			pwm_AO_ab: pwm@7000 {
1073				compatible = "amlogic,meson-g12a-ao-pwm-ab";
1074				reg = <0x0 0x7000 0x0 0x20>;
1075				#pwm-cells = <3>;
1076				status = "disabled";
1077			};
1078
1079			ir: ir@8000 {
1080				compatible = "amlogic,meson-gxbb-ir";
1081				reg = <0x0 0x8000 0x0 0x20>;
1082				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1083				status = "disabled";
1084			};
1085
1086			saradc: adc@9000 {
1087				compatible = "amlogic,meson-g12a-saradc",
1088					     "amlogic,meson-saradc";
1089				reg = <0x0 0x9000 0x0 0x48>;
1090				#io-channel-cells = <1>;
1091				interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
1092				clocks = <&xtal>,
1093					 <&clkc_AO CLKID_AO_SAR_ADC>,
1094					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1095					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1096				clock-names = "clkin", "core", "adc_clk", "adc_sel";
1097				status = "disabled";
1098			};
1099		};
1100
1101		vpu: vpu@ff900000 {
1102			compatible = "amlogic,meson-g12a-vpu";
1103			reg = <0x0 0xff900000 0x0 0x100000>,
1104			      <0x0 0xff63c000 0x0 0x1000>;
1105			reg-names = "vpu", "hhi";
1106			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
1107			#address-cells = <1>;
1108			#size-cells = <0>;
1109			amlogic,canvas = <&canvas>;
1110			power-domains = <&pwrc_vpu>;
1111
1112			/* CVBS VDAC output port */
1113			cvbs_vdac_port: port@0 {
1114				reg = <0>;
1115			};
1116
1117			/* HDMI-TX output port */
1118			hdmi_tx_port: port@1 {
1119				reg = <1>;
1120
1121				hdmi_tx_out: endpoint {
1122					remote-endpoint = <&hdmi_tx_in>;
1123				};
1124			};
1125		};
1126
1127		gic: interrupt-controller@ffc01000 {
1128			compatible = "arm,gic-400";
1129			reg = <0x0 0xffc01000 0 0x1000>,
1130			      <0x0 0xffc02000 0 0x2000>,
1131			      <0x0 0xffc04000 0 0x2000>,
1132			      <0x0 0xffc06000 0 0x2000>;
1133			interrupt-controller;
1134			interrupts = <GIC_PPI 9
1135				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1136			#interrupt-cells = <3>;
1137			#address-cells = <0>;
1138		};
1139
1140		cbus: bus@ffd00000 {
1141			compatible = "simple-bus";
1142			reg = <0x0 0xffd00000 0x0 0x100000>;
1143			#address-cells = <2>;
1144			#size-cells = <2>;
1145			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
1146
1147			reset: reset-controller@1004 {
1148				compatible = "amlogic,meson-g12a-reset",
1149					     "amlogic,meson-axg-reset";
1150				reg = <0x0 0x1004 0x0 0x9c>;
1151				#reset-cells = <1>;
1152			};
1153
1154			pwm_ef: pwm@19000 {
1155				compatible = "amlogic,meson-g12a-ee-pwm";
1156				reg = <0x0 0x19000 0x0 0x20>;
1157				#pwm-cells = <3>;
1158				status = "disabled";
1159			};
1160
1161			pwm_cd: pwm@1a000 {
1162				compatible = "amlogic,meson-g12a-ee-pwm";
1163				reg = <0x0 0x1a000 0x0 0x20>;
1164				#pwm-cells = <3>;
1165				status = "disabled";
1166			};
1167
1168			pwm_ab: pwm@1b000 {
1169				compatible = "amlogic,meson-g12a-ee-pwm";
1170				reg = <0x0 0x1b000 0x0 0x20>;
1171				#pwm-cells = <3>;
1172				status = "disabled";
1173			};
1174
1175			i2c3: i2c@1c000 {
1176				compatible = "amlogic,meson-axg-i2c";
1177				status = "disabled";
1178				reg = <0x0 0x1c000 0x0 0x20>;
1179				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1180				#address-cells = <1>;
1181				#size-cells = <0>;
1182				clocks = <&clkc CLKID_I2C>;
1183			};
1184
1185			i2c2: i2c@1d000 {
1186				compatible = "amlogic,meson-axg-i2c";
1187				status = "disabled";
1188				reg = <0x0 0x1d000 0x0 0x20>;
1189				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1190				#address-cells = <1>;
1191				#size-cells = <0>;
1192				clocks = <&clkc CLKID_I2C>;
1193			};
1194
1195			i2c1: i2c@1e000 {
1196				compatible = "amlogic,meson-axg-i2c";
1197				status = "disabled";
1198				reg = <0x0 0x1e000 0x0 0x20>;
1199				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1200				#address-cells = <1>;
1201				#size-cells = <0>;
1202				clocks = <&clkc CLKID_I2C>;
1203			};
1204
1205			i2c0: i2c@1f000 {
1206				compatible = "amlogic,meson-axg-i2c";
1207				status = "disabled";
1208				reg = <0x0 0x1f000 0x0 0x20>;
1209				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1210				#address-cells = <1>;
1211				#size-cells = <0>;
1212				clocks = <&clkc CLKID_I2C>;
1213			};
1214
1215			clk_msr: clock-measure@18000 {
1216				compatible = "amlogic,meson-g12a-clk-measure";
1217				reg = <0x0 0x18000 0x0 0x10>;
1218			};
1219
1220			uart_C: serial@22000 {
1221				compatible = "amlogic,meson-gx-uart";
1222				reg = <0x0 0x22000 0x0 0x18>;
1223				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
1224				clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
1225				clock-names = "xtal", "pclk", "baud";
1226				status = "disabled";
1227			};
1228
1229			uart_B: serial@23000 {
1230				compatible = "amlogic,meson-gx-uart";
1231				reg = <0x0 0x23000 0x0 0x18>;
1232				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1233				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1234				clock-names = "xtal", "pclk", "baud";
1235				status = "disabled";
1236			};
1237
1238			uart_A: serial@24000 {
1239				compatible = "amlogic,meson-gx-uart";
1240				reg = <0x0 0x24000 0x0 0x18>;
1241				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1242				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1243				clock-names = "xtal", "pclk", "baud";
1244				status = "disabled";
1245			};
1246		};
1247
1248		sd_emmc_b: sd@ffe05000 {
1249			compatible = "amlogic,meson-axg-mmc";
1250			reg = <0x0 0xffe05000 0x0 0x800>;
1251			interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
1252			status = "disabled";
1253			clocks = <&clkc CLKID_SD_EMMC_B>,
1254				 <&clkc CLKID_SD_EMMC_B_CLK0>,
1255				 <&clkc CLKID_FCLK_DIV2>;
1256			clock-names = "core", "clkin0", "clkin1";
1257			resets = <&reset RESET_SD_EMMC_B>;
1258		};
1259
1260		sd_emmc_c: mmc@ffe07000 {
1261			compatible = "amlogic,meson-axg-mmc";
1262			reg = <0x0 0xffe07000 0x0 0x800>;
1263			interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
1264			status = "disabled";
1265			clocks = <&clkc CLKID_SD_EMMC_C>,
1266				 <&clkc CLKID_SD_EMMC_C_CLK0>,
1267				 <&clkc CLKID_FCLK_DIV2>;
1268			clock-names = "core", "clkin0", "clkin1";
1269			resets = <&reset RESET_SD_EMMC_C>;
1270		};
1271
1272		usb: usb@ffe09000 {
1273			status = "disabled";
1274			compatible = "amlogic,meson-g12a-usb-ctrl";
1275			reg = <0x0 0xffe09000 0x0 0xa0>;
1276			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1277			#address-cells = <2>;
1278			#size-cells = <2>;
1279			ranges;
1280
1281			clocks = <&clkc CLKID_USB>;
1282			resets = <&reset RESET_USB>;
1283
1284			dr_mode = "otg";
1285
1286			phys = <&usb2_phy0>, <&usb2_phy1>,
1287			       <&usb3_pcie_phy PHY_TYPE_USB3>;
1288			phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
1289
1290			dwc2: usb@ff400000 {
1291				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
1292				reg = <0x0 0xff400000 0x0 0x40000>;
1293				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1294				clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
1295				clock-names = "ddr";
1296				phys = <&usb2_phy1>;
1297				dr_mode = "peripheral";
1298				g-rx-fifo-size = <192>;
1299				g-np-tx-fifo-size = <128>;
1300				g-tx-fifo-size = <128 128 16 16 16>;
1301			};
1302
1303			dwc3: usb@ff500000 {
1304				compatible = "snps,dwc3";
1305				reg = <0x0 0xff500000 0x0 0x100000>;
1306				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1307				dr_mode = "host";
1308				snps,dis_u2_susphy_quirk;
1309				snps,quirk-frame-length-adjustment;
1310			};
1311		};
1312
1313		mali: gpu@ffe40000 {
1314			compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
1315			reg = <0x0 0xffe40000 0x0 0x40000>;
1316			interrupt-parent = <&gic>;
1317			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1318				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1319				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1320			interrupt-names = "gpu", "mmu", "job";
1321			clocks = <&clkc CLKID_MALI>;
1322			resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
1323
1324			/*
1325			 * Mali clocking is provided by two identical clock paths
1326			 * MALI_0 and MALI_1 muxed to a single clock by a glitch
1327			 * free mux to safely change frequency while running.
1328			 */
1329			assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
1330					  <&clkc CLKID_MALI_0>,
1331					  <&clkc CLKID_MALI>; /* Glitch free mux */
1332			assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
1333						 <0>, /* Do Nothing */
1334						 <&clkc CLKID_MALI_0>;
1335			assigned-clock-rates = <0>, /* Do Nothing */
1336					       <800000000>,
1337					       <0>; /* Do Nothing */
1338		};
1339	};
1340
1341	timer {
1342		compatible = "arm,armv8-timer";
1343		interrupts = <GIC_PPI 13
1344			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1345			     <GIC_PPI 14
1346			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1347			     <GIC_PPI 11
1348			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1349			     <GIC_PPI 10
1350			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1351	};
1352
1353	xtal: xtal-clk {
1354		compatible = "fixed-clock";
1355		clock-frequency = <24000000>;
1356		clock-output-names = "xtal";
1357		#clock-cells = <0>;
1358	};
1359
1360};
1361