1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/clock/g12a-clkc.h>
8#include <dt-bindings/clock/g12a-aoclkc.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13	compatible = "amlogic,g12a";
14
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	cpus {
20		#address-cells = <0x2>;
21		#size-cells = <0x0>;
22
23		cpu0: cpu@0 {
24			device_type = "cpu";
25			compatible = "arm,cortex-a53";
26			reg = <0x0 0x0>;
27			enable-method = "psci";
28			next-level-cache = <&l2>;
29		};
30
31		cpu1: cpu@1 {
32			device_type = "cpu";
33			compatible = "arm,cortex-a53";
34			reg = <0x0 0x1>;
35			enable-method = "psci";
36			next-level-cache = <&l2>;
37		};
38
39		cpu2: cpu@2 {
40			device_type = "cpu";
41			compatible = "arm,cortex-a53";
42			reg = <0x0 0x2>;
43			enable-method = "psci";
44			next-level-cache = <&l2>;
45		};
46
47		cpu3: cpu@3 {
48			device_type = "cpu";
49			compatible = "arm,cortex-a53";
50			reg = <0x0 0x3>;
51			enable-method = "psci";
52			next-level-cache = <&l2>;
53		};
54
55		l2: l2-cache0 {
56			compatible = "cache";
57		};
58	};
59
60	efuse: efuse {
61		compatible = "amlogic,meson-gxbb-efuse";
62		clocks = <&clkc CLKID_EFUSE>;
63		#address-cells = <1>;
64		#size-cells = <1>;
65		read-only;
66	};
67
68	psci {
69		compatible = "arm,psci-1.0";
70		method = "smc";
71	};
72
73	reserved-memory {
74		#address-cells = <2>;
75		#size-cells = <2>;
76		ranges;
77
78		/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
79		secmon_reserved: secmon@5000000 {
80			reg = <0x0 0x05000000 0x0 0x300000>;
81			no-map;
82		};
83
84		linux,cma {
85			compatible = "shared-dma-pool";
86			reusable;
87			size = <0x0 0x10000000>;
88			alignment = <0x0 0x400000>;
89			linux,cma-default;
90		};
91	};
92
93	sm: secure-monitor {
94		compatible = "amlogic,meson-gxbb-sm";
95	};
96
97	soc {
98		compatible = "simple-bus";
99		#address-cells = <2>;
100		#size-cells = <2>;
101		ranges;
102
103		apb: bus@ff600000 {
104			compatible = "simple-bus";
105			reg = <0x0 0xff600000 0x0 0x200000>;
106			#address-cells = <2>;
107			#size-cells = <2>;
108			ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
109
110			periphs: bus@34400 {
111				compatible = "simple-bus";
112				reg = <0x0 0x34400 0x0 0x400>;
113				#address-cells = <2>;
114				#size-cells = <2>;
115				ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
116
117				periphs_pinctrl: pinctrl@40 {
118					compatible = "amlogic,meson-g12a-periphs-pinctrl";
119					#address-cells = <2>;
120					#size-cells = <2>;
121					ranges;
122
123					gpio: bank@40 {
124						reg = <0x0 0x40  0x0 0x4c>,
125						      <0x0 0xe8  0x0 0x18>,
126						      <0x0 0x120 0x0 0x18>,
127						      <0x0 0x2c0 0x0 0x40>,
128						      <0x0 0x340 0x0 0x1c>;
129						reg-names = "gpio",
130							    "pull",
131							    "pull-enable",
132							    "mux",
133							    "ds";
134						gpio-controller;
135						#gpio-cells = <2>;
136						gpio-ranges = <&periphs_pinctrl 0 0 86>;
137					};
138
139					uart_a_pins: uart-a {
140						mux {
141							groups = "uart_a_tx",
142								 "uart_a_rx";
143							function = "uart_a";
144							bias-disable;
145						};
146					};
147
148					uart_a_cts_rts_pins: uart-a-cts-rts {
149						mux {
150							groups = "uart_a_cts",
151								 "uart_a_rts";
152							function = "uart_a";
153							bias-disable;
154						};
155					};
156
157					uart_b_pins: uart-b {
158						mux {
159							groups = "uart_b_tx",
160								 "uart_b_rx";
161							function = "uart_b";
162							bias-disable;
163						};
164					};
165
166					uart_c_pins: uart-c {
167						mux {
168							groups = "uart_c_tx",
169								 "uart_c_rx";
170							function = "uart_c";
171							bias-disable;
172						};
173					};
174
175					uart_c_cts_rts_pins: uart-c-cts-rts {
176						mux {
177							groups = "uart_c_cts",
178								 "uart_c_rts";
179							function = "uart_c";
180							bias-disable;
181						};
182					};
183				};
184			};
185
186			hiu: bus@3c000 {
187				compatible = "simple-bus";
188				reg = <0x0 0x3c000 0x0 0x1400>;
189				#address-cells = <2>;
190				#size-cells = <2>;
191				ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
192
193				hhi: system-controller@0 {
194					compatible = "amlogic,meson-gx-hhi-sysctrl",
195						     "simple-mfd", "syscon";
196					reg = <0 0 0 0x400>;
197
198					clkc: clock-controller {
199						compatible = "amlogic,g12a-clkc";
200						#clock-cells = <1>;
201						clocks = <&xtal>;
202						clock-names = "xtal";
203					};
204				};
205			};
206		};
207
208		aobus: bus@ff800000 {
209			compatible = "simple-bus";
210			reg = <0x0 0xff800000 0x0 0x100000>;
211			#address-cells = <2>;
212			#size-cells = <2>;
213			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
214
215			rti: sys-ctrl@0 {
216				compatible = "amlogic,meson-gx-ao-sysctrl",
217					     "simple-mfd", "syscon";
218				reg = <0x0 0x0 0x0 0x100>;
219				#address-cells = <2>;
220				#size-cells = <2>;
221				ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
222
223				clkc_AO: clock-controller {
224					compatible = "amlogic,meson-g12a-aoclkc";
225					#clock-cells = <1>;
226					#reset-cells = <1>;
227					clocks = <&xtal>, <&clkc CLKID_CLK81>;
228					clock-names = "xtal", "mpeg-clk";
229				};
230
231				ao_pinctrl: pinctrl@14 {
232					compatible = "amlogic,meson-g12a-aobus-pinctrl";
233					#address-cells = <2>;
234					#size-cells = <2>;
235					ranges;
236
237					gpio_ao: bank@14 {
238						reg = <0x0 0x14 0x0 0x8>,
239						      <0x0 0x1c 0x0 0x8>,
240						      <0x0 0x24 0x0 0x14>;
241						reg-names = "mux",
242							    "ds",
243							    "gpio";
244						gpio-controller;
245						#gpio-cells = <2>;
246						gpio-ranges = <&ao_pinctrl 0 0 15>;
247					};
248
249					uart_ao_a_pins: uart-a-ao {
250						mux {
251							groups = "uart_ao_a_tx",
252								 "uart_ao_a_rx";
253							function = "uart_ao_a";
254							bias-disable;
255						};
256					};
257
258					uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
259						mux {
260							groups = "uart_ao_a_cts",
261								 "uart_ao_a_rts";
262							function = "uart_ao_a";
263							bias-disable;
264						};
265					};
266				};
267			};
268
269			sec_AO: ao-secure@140 {
270				compatible = "amlogic,meson-gx-ao-secure", "syscon";
271				reg = <0x0 0x140 0x0 0x140>;
272				amlogic,has-chip-id;
273			};
274
275			uart_AO: serial@3000 {
276				compatible = "amlogic,meson-gx-uart",
277					     "amlogic,meson-ao-uart";
278				reg = <0x0 0x3000 0x0 0x18>;
279				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
280				clocks = <&xtal>, <&xtal>, <&xtal>;
281				clock-names = "xtal", "pclk", "baud";
282				status = "disabled";
283			};
284
285			uart_AO_B: serial@4000 {
286				compatible = "amlogic,meson-gx-uart",
287					     "amlogic,meson-ao-uart";
288				reg = <0x0 0x4000 0x0 0x18>;
289				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
290				clocks = <&xtal>, <&xtal>, <&xtal>;
291				clock-names = "xtal", "pclk", "baud";
292				status = "disabled";
293			};
294
295			saradc: adc@9000 {
296				compatible = "amlogic,meson-g12a-saradc",
297					     "amlogic,meson-saradc";
298				reg = <0x0 0x9000 0x0 0x48>;
299				#io-channel-cells = <1>;
300				interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
301				clocks = <&xtal>,
302					 <&clkc_AO CLKID_AO_SAR_ADC>,
303					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
304					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
305				clock-names = "clkin", "core", "adc_clk", "adc_sel";
306				status = "disabled";
307			};
308		};
309
310		gic: interrupt-controller@ffc01000 {
311			compatible = "arm,gic-400";
312			reg = <0x0 0xffc01000 0 0x1000>,
313			      <0x0 0xffc02000 0 0x2000>,
314			      <0x0 0xffc04000 0 0x2000>,
315			      <0x0 0xffc06000 0 0x2000>;
316			interrupt-controller;
317			interrupts = <GIC_PPI 9
318				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
319			#interrupt-cells = <3>;
320			#address-cells = <0>;
321		};
322
323		cbus: bus@ffd00000 {
324			compatible = "simple-bus";
325			reg = <0x0 0xffd00000 0x0 0x100000>;
326			#address-cells = <2>;
327			#size-cells = <2>;
328			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
329
330			reset: reset-controller@1004 {
331				compatible = "amlogic,meson-g12a-reset",
332					     "amlogic,meson-axg-reset";
333				reg = <0x0 0x1004 0x0 0x9c>;
334				#reset-cells = <1>;
335			};
336
337			clk_msr: clock-measure@18000 {
338				compatible = "amlogic,meson-g12a-clk-measure";
339				reg = <0x0 0x18000 0x0 0x10>;
340			};
341
342			uart_C: serial@22000 {
343				compatible = "amlogic,meson-gx-uart";
344				reg = <0x0 0x22000 0x0 0x18>;
345				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
346				clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
347				clock-names = "xtal", "pclk", "baud";
348				status = "disabled";
349			};
350
351			uart_B: serial@23000 {
352				compatible = "amlogic,meson-gx-uart";
353				reg = <0x0 0x23000 0x0 0x18>;
354				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
355				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
356				clock-names = "xtal", "pclk", "baud";
357				status = "disabled";
358			};
359
360			uart_A: serial@24000 {
361				compatible = "amlogic,meson-gx-uart";
362				reg = <0x0 0x24000 0x0 0x18>;
363				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
364				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
365				clock-names = "xtal", "pclk", "baud";
366				status = "disabled";
367			};
368		};
369	};
370
371	timer {
372		compatible = "arm,armv8-timer";
373		interrupts = <GIC_PPI 13
374			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
375			     <GIC_PPI 14
376			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
377			     <GIC_PPI 11
378			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
379			     <GIC_PPI 10
380			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
381	};
382
383	xtal: xtal-clk {
384		compatible = "fixed-clock";
385		clock-frequency = <24000000>;
386		clock-output-names = "xtal";
387		#clock-cells = <0>;
388	};
389
390};
391