1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11	compatible = "amlogic,g12a";
12
13	interrupt-parent = <&gic>;
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	cpus {
18		#address-cells = <0x2>;
19		#size-cells = <0x0>;
20
21		cpu0: cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a53", "arm,armv8";
24			reg = <0x0 0x0>;
25			enable-method = "psci";
26			next-level-cache = <&l2>;
27		};
28
29		cpu1: cpu@1 {
30			device_type = "cpu";
31			compatible = "arm,cortex-a53", "arm,armv8";
32			reg = <0x0 0x1>;
33			enable-method = "psci";
34			next-level-cache = <&l2>;
35		};
36
37		cpu2: cpu@2 {
38			device_type = "cpu";
39			compatible = "arm,cortex-a53", "arm,armv8";
40			reg = <0x0 0x2>;
41			enable-method = "psci";
42			next-level-cache = <&l2>;
43		};
44
45		cpu3: cpu@3 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a53", "arm,armv8";
48			reg = <0x0 0x3>;
49			enable-method = "psci";
50			next-level-cache = <&l2>;
51		};
52
53		l2: l2-cache0 {
54			compatible = "cache";
55		};
56	};
57
58	psci {
59		compatible = "arm,psci-1.0";
60		method = "smc";
61	};
62
63	reserved-memory {
64		#address-cells = <2>;
65		#size-cells = <2>;
66		ranges;
67
68		/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
69		secmon_reserved: secmon@5000000 {
70			reg = <0x0 0x05000000 0x0 0x300000>;
71			no-map;
72		};
73	};
74
75	soc {
76		compatible = "simple-bus";
77		#address-cells = <2>;
78		#size-cells = <2>;
79		ranges;
80
81		apb: bus@ff600000 {
82			compatible = "simple-bus";
83			reg = <0x0 0xff600000 0x0 0x200000>;
84			#address-cells = <2>;
85			#size-cells = <2>;
86			ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
87
88			periphs: bus@34400 {
89				compatible = "simple-bus";
90				reg = <0x0 0x34400 0x0 0x400>;
91				#address-cells = <2>;
92				#size-cells = <2>;
93				ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
94			};
95
96			hiu: bus@3c000 {
97				compatible = "simple-bus";
98				reg = <0x0 0x3c000 0x0 0x1400>;
99				#address-cells = <2>;
100				#size-cells = <2>;
101				ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
102			};
103		};
104
105		aobus: bus@ff800000 {
106			compatible = "simple-bus";
107			reg = <0x0 0xff800000 0x0 0x100000>;
108			#address-cells = <2>;
109			#size-cells = <2>;
110			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
111
112			uart_AO: serial@3000 {
113				compatible = "amlogic,meson-gx-uart",
114					     "amlogic,meson-ao-uart";
115				reg = <0x0 0x3000 0x0 0x18>;
116				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
117				clocks = <&xtal>, <&xtal>, <&xtal>;
118				clock-names = "xtal", "pclk", "baud";
119				status = "disabled";
120			};
121
122			uart_AO_B: serial@4000 {
123				compatible = "amlogic,meson-gx-uart",
124					     "amlogic,meson-ao-uart";
125				reg = <0x0 0x4000 0x0 0x18>;
126				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
127				clocks = <&xtal>, <&xtal>, <&xtal>;
128				clock-names = "xtal", "pclk", "baud";
129				status = "disabled";
130			};
131		};
132
133		gic: interrupt-controller@ffc01000 {
134			compatible = "arm,gic-400";
135			reg = <0x0 0xffc01000 0 0x1000>,
136			      <0x0 0xffc02000 0 0x2000>,
137			      <0x0 0xffc04000 0 0x2000>,
138			      <0x0 0xffc06000 0 0x2000>;
139			interrupt-controller;
140			interrupts = <GIC_PPI 9
141				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
142			#interrupt-cells = <3>;
143			#address-cells = <0>;
144		};
145
146		cbus: bus@ffd00000 {
147			compatible = "simple-bus";
148			reg = <0x0 0xffd00000 0x0 0x100000>;
149			#address-cells = <2>;
150			#size-cells = <2>;
151			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
152
153			clk_msr: clock-measure@18000 {
154				compatible = "amlogic,meson-g12a-clk-measure";
155				reg = <0x0 0x18000 0x0 0x10>;
156			};
157		};
158	};
159
160	timer {
161		compatible = "arm,armv8-timer";
162		interrupts = <GIC_PPI 13
163			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
164			     <GIC_PPI 14
165			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
166			     <GIC_PPI 11
167			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
168			     <GIC_PPI 10
169			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
170	};
171
172	xtal: xtal-clk {
173		compatible = "fixed-clock";
174		clock-frequency = <24000000>;
175		clock-output-names = "xtal";
176		#clock-cells = <0>;
177	};
178
179};
180