1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/phy/phy.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/clock/g12a-clkc.h>
9#include <dt-bindings/clock/g12a-aoclkc.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
13
14/ {
15	compatible = "amlogic,g12a";
16
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	cpus {
22		#address-cells = <0x2>;
23		#size-cells = <0x0>;
24
25		cpu0: cpu@0 {
26			device_type = "cpu";
27			compatible = "arm,cortex-a53";
28			reg = <0x0 0x0>;
29			enable-method = "psci";
30			next-level-cache = <&l2>;
31		};
32
33		cpu1: cpu@1 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a53";
36			reg = <0x0 0x1>;
37			enable-method = "psci";
38			next-level-cache = <&l2>;
39		};
40
41		cpu2: cpu@2 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53";
44			reg = <0x0 0x2>;
45			enable-method = "psci";
46			next-level-cache = <&l2>;
47		};
48
49		cpu3: cpu@3 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a53";
52			reg = <0x0 0x3>;
53			enable-method = "psci";
54			next-level-cache = <&l2>;
55		};
56
57		l2: l2-cache0 {
58			compatible = "cache";
59		};
60	};
61
62	efuse: efuse {
63		compatible = "amlogic,meson-gxbb-efuse";
64		clocks = <&clkc CLKID_EFUSE>;
65		#address-cells = <1>;
66		#size-cells = <1>;
67		read-only;
68	};
69
70	psci {
71		compatible = "arm,psci-1.0";
72		method = "smc";
73	};
74
75	reserved-memory {
76		#address-cells = <2>;
77		#size-cells = <2>;
78		ranges;
79
80		/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
81		secmon_reserved: secmon@5000000 {
82			reg = <0x0 0x05000000 0x0 0x300000>;
83			no-map;
84		};
85
86		linux,cma {
87			compatible = "shared-dma-pool";
88			reusable;
89			size = <0x0 0x10000000>;
90			alignment = <0x0 0x400000>;
91			linux,cma-default;
92		};
93	};
94
95	sm: secure-monitor {
96		compatible = "amlogic,meson-gxbb-sm";
97	};
98
99	soc {
100		compatible = "simple-bus";
101		#address-cells = <2>;
102		#size-cells = <2>;
103		ranges;
104
105		apb: bus@ff600000 {
106			compatible = "simple-bus";
107			reg = <0x0 0xff600000 0x0 0x200000>;
108			#address-cells = <2>;
109			#size-cells = <2>;
110			ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
111
112			periphs: bus@34400 {
113				compatible = "simple-bus";
114				reg = <0x0 0x34400 0x0 0x400>;
115				#address-cells = <2>;
116				#size-cells = <2>;
117				ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
118
119				periphs_pinctrl: pinctrl@40 {
120					compatible = "amlogic,meson-g12a-periphs-pinctrl";
121					#address-cells = <2>;
122					#size-cells = <2>;
123					ranges;
124
125					gpio: bank@40 {
126						reg = <0x0 0x40  0x0 0x4c>,
127						      <0x0 0xe8  0x0 0x18>,
128						      <0x0 0x120 0x0 0x18>,
129						      <0x0 0x2c0 0x0 0x40>,
130						      <0x0 0x340 0x0 0x1c>;
131						reg-names = "gpio",
132							    "pull",
133							    "pull-enable",
134							    "mux",
135							    "ds";
136						gpio-controller;
137						#gpio-cells = <2>;
138						gpio-ranges = <&periphs_pinctrl 0 0 86>;
139					};
140
141					uart_a_pins: uart-a {
142						mux {
143							groups = "uart_a_tx",
144								 "uart_a_rx";
145							function = "uart_a";
146							bias-disable;
147						};
148					};
149
150					uart_a_cts_rts_pins: uart-a-cts-rts {
151						mux {
152							groups = "uart_a_cts",
153								 "uart_a_rts";
154							function = "uart_a";
155							bias-disable;
156						};
157					};
158
159					uart_b_pins: uart-b {
160						mux {
161							groups = "uart_b_tx",
162								 "uart_b_rx";
163							function = "uart_b";
164							bias-disable;
165						};
166					};
167
168					uart_c_pins: uart-c {
169						mux {
170							groups = "uart_c_tx",
171								 "uart_c_rx";
172							function = "uart_c";
173							bias-disable;
174						};
175					};
176
177					uart_c_cts_rts_pins: uart-c-cts-rts {
178						mux {
179							groups = "uart_c_cts",
180								 "uart_c_rts";
181							function = "uart_c";
182							bias-disable;
183						};
184					};
185				};
186			};
187
188			usb2_phy0: phy@36000 {
189				compatible = "amlogic,g12a-usb2-phy";
190				reg = <0x0 0x36000 0x0 0x2000>;
191				clocks = <&xtal>;
192				clock-names = "xtal";
193				resets = <&reset RESET_USB_PHY20>;
194				reset-names = "phy";
195				#phy-cells = <0>;
196			};
197
198			usb2_phy1: phy@3a000 {
199				compatible = "amlogic,g12a-usb2-phy";
200				reg = <0x0 0x3a000 0x0 0x2000>;
201				clocks = <&xtal>;
202				clock-names = "xtal";
203				resets = <&reset RESET_USB_PHY21>;
204				reset-names = "phy";
205				#phy-cells = <0>;
206			};
207
208			hiu: bus@3c000 {
209				compatible = "simple-bus";
210				reg = <0x0 0x3c000 0x0 0x1400>;
211				#address-cells = <2>;
212				#size-cells = <2>;
213				ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
214
215				hhi: system-controller@0 {
216					compatible = "amlogic,meson-gx-hhi-sysctrl",
217						     "simple-mfd", "syscon";
218					reg = <0 0 0 0x400>;
219
220					clkc: clock-controller {
221						compatible = "amlogic,g12a-clkc";
222						#clock-cells = <1>;
223						clocks = <&xtal>;
224						clock-names = "xtal";
225					};
226				};
227			};
228
229			usb3_pcie_phy: phy@46000 {
230				compatible = "amlogic,g12a-usb3-pcie-phy";
231				reg = <0x0 0x46000 0x0 0x2000>;
232				clocks = <&clkc CLKID_PCIE_PLL>;
233				clock-names = "ref_clk";
234				resets = <&reset RESET_PCIE_PHY>;
235				reset-names = "phy";
236				assigned-clocks = <&clkc CLKID_PCIE_PLL>;
237				assigned-clock-rates = <100000000>;
238				#phy-cells = <1>;
239			};
240		};
241
242		aobus: bus@ff800000 {
243			compatible = "simple-bus";
244			reg = <0x0 0xff800000 0x0 0x100000>;
245			#address-cells = <2>;
246			#size-cells = <2>;
247			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
248
249			rti: sys-ctrl@0 {
250				compatible = "amlogic,meson-gx-ao-sysctrl",
251					     "simple-mfd", "syscon";
252				reg = <0x0 0x0 0x0 0x100>;
253				#address-cells = <2>;
254				#size-cells = <2>;
255				ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
256
257				clkc_AO: clock-controller {
258					compatible = "amlogic,meson-g12a-aoclkc";
259					#clock-cells = <1>;
260					#reset-cells = <1>;
261					clocks = <&xtal>, <&clkc CLKID_CLK81>;
262					clock-names = "xtal", "mpeg-clk";
263				};
264
265				ao_pinctrl: pinctrl@14 {
266					compatible = "amlogic,meson-g12a-aobus-pinctrl";
267					#address-cells = <2>;
268					#size-cells = <2>;
269					ranges;
270
271					gpio_ao: bank@14 {
272						reg = <0x0 0x14 0x0 0x8>,
273						      <0x0 0x1c 0x0 0x8>,
274						      <0x0 0x24 0x0 0x14>;
275						reg-names = "mux",
276							    "ds",
277							    "gpio";
278						gpio-controller;
279						#gpio-cells = <2>;
280						gpio-ranges = <&ao_pinctrl 0 0 15>;
281					};
282
283					uart_ao_a_pins: uart-a-ao {
284						mux {
285							groups = "uart_ao_a_tx",
286								 "uart_ao_a_rx";
287							function = "uart_ao_a";
288							bias-disable;
289						};
290					};
291
292					uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
293						mux {
294							groups = "uart_ao_a_cts",
295								 "uart_ao_a_rts";
296							function = "uart_ao_a";
297							bias-disable;
298						};
299					};
300				};
301			};
302
303			sec_AO: ao-secure@140 {
304				compatible = "amlogic,meson-gx-ao-secure", "syscon";
305				reg = <0x0 0x140 0x0 0x140>;
306				amlogic,has-chip-id;
307			};
308
309			uart_AO: serial@3000 {
310				compatible = "amlogic,meson-gx-uart",
311					     "amlogic,meson-ao-uart";
312				reg = <0x0 0x3000 0x0 0x18>;
313				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
314				clocks = <&xtal>, <&xtal>, <&xtal>;
315				clock-names = "xtal", "pclk", "baud";
316				status = "disabled";
317			};
318
319			uart_AO_B: serial@4000 {
320				compatible = "amlogic,meson-gx-uart",
321					     "amlogic,meson-ao-uart";
322				reg = <0x0 0x4000 0x0 0x18>;
323				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
324				clocks = <&xtal>, <&xtal>, <&xtal>;
325				clock-names = "xtal", "pclk", "baud";
326				status = "disabled";
327			};
328
329			saradc: adc@9000 {
330				compatible = "amlogic,meson-g12a-saradc",
331					     "amlogic,meson-saradc";
332				reg = <0x0 0x9000 0x0 0x48>;
333				#io-channel-cells = <1>;
334				interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
335				clocks = <&xtal>,
336					 <&clkc_AO CLKID_AO_SAR_ADC>,
337					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
338					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
339				clock-names = "clkin", "core", "adc_clk", "adc_sel";
340				status = "disabled";
341			};
342		};
343
344		gic: interrupt-controller@ffc01000 {
345			compatible = "arm,gic-400";
346			reg = <0x0 0xffc01000 0 0x1000>,
347			      <0x0 0xffc02000 0 0x2000>,
348			      <0x0 0xffc04000 0 0x2000>,
349			      <0x0 0xffc06000 0 0x2000>;
350			interrupt-controller;
351			interrupts = <GIC_PPI 9
352				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
353			#interrupt-cells = <3>;
354			#address-cells = <0>;
355		};
356
357		cbus: bus@ffd00000 {
358			compatible = "simple-bus";
359			reg = <0x0 0xffd00000 0x0 0x100000>;
360			#address-cells = <2>;
361			#size-cells = <2>;
362			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
363
364			reset: reset-controller@1004 {
365				compatible = "amlogic,meson-g12a-reset",
366					     "amlogic,meson-axg-reset";
367				reg = <0x0 0x1004 0x0 0x9c>;
368				#reset-cells = <1>;
369			};
370
371			clk_msr: clock-measure@18000 {
372				compatible = "amlogic,meson-g12a-clk-measure";
373				reg = <0x0 0x18000 0x0 0x10>;
374			};
375
376			uart_C: serial@22000 {
377				compatible = "amlogic,meson-gx-uart";
378				reg = <0x0 0x22000 0x0 0x18>;
379				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
380				clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
381				clock-names = "xtal", "pclk", "baud";
382				status = "disabled";
383			};
384
385			uart_B: serial@23000 {
386				compatible = "amlogic,meson-gx-uart";
387				reg = <0x0 0x23000 0x0 0x18>;
388				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
389				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
390				clock-names = "xtal", "pclk", "baud";
391				status = "disabled";
392			};
393
394			uart_A: serial@24000 {
395				compatible = "amlogic,meson-gx-uart";
396				reg = <0x0 0x24000 0x0 0x18>;
397				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
398				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
399				clock-names = "xtal", "pclk", "baud";
400				status = "disabled";
401			};
402		};
403
404		usb: usb@ffe09000 {
405			status = "disabled";
406			compatible = "amlogic,meson-g12a-usb-ctrl";
407			reg = <0x0 0xffe09000 0x0 0xa0>;
408			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
409			#address-cells = <2>;
410			#size-cells = <2>;
411			ranges;
412
413			clocks = <&clkc CLKID_USB>;
414			resets = <&reset RESET_USB>;
415
416			dr_mode = "otg";
417
418			phys = <&usb2_phy0>, <&usb2_phy1>,
419			       <&usb3_pcie_phy PHY_TYPE_USB3>;
420			phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
421
422			dwc2: usb@ff400000 {
423				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
424				reg = <0x0 0xff400000 0x0 0x40000>;
425				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
426				clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
427				clock-names = "ddr";
428				phys = <&usb2_phy1>;
429				dr_mode = "peripheral";
430				g-rx-fifo-size = <192>;
431				g-np-tx-fifo-size = <128>;
432				g-tx-fifo-size = <128 128 16 16 16>;
433			};
434
435			dwc3: usb@ff500000 {
436				compatible = "snps,dwc3";
437				reg = <0x0 0xff500000 0x0 0x100000>;
438				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
439				dr_mode = "host";
440				snps,dis_u2_susphy_quirk;
441				snps,quirk-frame-length-adjustment;
442			};
443		};
444
445		mali: gpu@ffe40000 {
446			compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
447			reg = <0x0 0xffe40000 0x0 0x40000>;
448			interrupt-parent = <&gic>;
449			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
450				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
451				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
452			interrupt-names = "gpu", "mmu", "job";
453			clocks = <&clkc CLKID_MALI>;
454			resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
455
456			/*
457			 * Mali clocking is provided by two identical clock paths
458			 * MALI_0 and MALI_1 muxed to a single clock by a glitch
459			 * free mux to safely change frequency while running.
460			 */
461			assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
462					  <&clkc CLKID_MALI_0>,
463					  <&clkc CLKID_MALI>; /* Glitch free mux */
464			assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
465						 <0>, /* Do Nothing */
466						 <&clkc CLKID_MALI_0>;
467			assigned-clock-rates = <0>, /* Do Nothing */
468					       <800000000>,
469					       <0>; /* Do Nothing */
470		};
471	};
472
473	timer {
474		compatible = "arm,armv8-timer";
475		interrupts = <GIC_PPI 13
476			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
477			     <GIC_PPI 14
478			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
479			     <GIC_PPI 11
480			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
481			     <GIC_PPI 10
482			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
483	};
484
485	xtal: xtal-clk {
486		compatible = "fixed-clock";
487		clock-frequency = <24000000>;
488		clock-output-names = "xtal";
489		#clock-cells = <0>;
490	};
491
492};
493