1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 15 16/ { 17 compatible = "amlogic,g12a"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 cpus { 57 #address-cells = <0x2>; 58 #size-cells = <0x0>; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0 0x0>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x0 0x2>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 next-level-cache = <&l2>; 90 }; 91 92 l2: l2-cache0 { 93 compatible = "cache"; 94 }; 95 }; 96 97 efuse: efuse { 98 compatible = "amlogic,meson-gxbb-efuse"; 99 clocks = <&clkc CLKID_EFUSE>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 read-only; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 110 reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 116 secmon_reserved: secmon@5000000 { 117 reg = <0x0 0x05000000 0x0 0x300000>; 118 no-map; 119 }; 120 121 linux,cma { 122 compatible = "shared-dma-pool"; 123 reusable; 124 size = <0x0 0x10000000>; 125 alignment = <0x0 0x400000>; 126 linux,cma-default; 127 }; 128 }; 129 130 sm: secure-monitor { 131 compatible = "amlogic,meson-gxbb-sm"; 132 }; 133 134 soc { 135 compatible = "simple-bus"; 136 #address-cells = <2>; 137 #size-cells = <2>; 138 ranges; 139 140 apb: bus@ff600000 { 141 compatible = "simple-bus"; 142 reg = <0x0 0xff600000 0x0 0x200000>; 143 #address-cells = <2>; 144 #size-cells = <2>; 145 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 146 147 hdmi_tx: hdmi-tx@0 { 148 compatible = "amlogic,meson-g12a-dw-hdmi"; 149 reg = <0x0 0x0 0x0 0x10000>; 150 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 151 resets = <&reset RESET_HDMITX_CAPB3>, 152 <&reset RESET_HDMITX_PHY>, 153 <&reset RESET_HDMITX>; 154 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 155 clocks = <&clkc CLKID_HDMI>, 156 <&clkc CLKID_HTX_PCLK>, 157 <&clkc CLKID_VPU_INTR>; 158 clock-names = "isfr", "iahb", "venci"; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 status = "disabled"; 162 163 /* VPU VENC Input */ 164 hdmi_tx_venc_port: port@0 { 165 reg = <0>; 166 167 hdmi_tx_in: endpoint { 168 remote-endpoint = <&hdmi_tx_out>; 169 }; 170 }; 171 172 /* TMDS Output */ 173 hdmi_tx_tmds_port: port@1 { 174 reg = <1>; 175 }; 176 }; 177 178 periphs: bus@34400 { 179 compatible = "simple-bus"; 180 reg = <0x0 0x34400 0x0 0x400>; 181 #address-cells = <2>; 182 #size-cells = <2>; 183 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 184 185 periphs_pinctrl: pinctrl@40 { 186 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 187 #address-cells = <2>; 188 #size-cells = <2>; 189 ranges; 190 191 gpio: bank@40 { 192 reg = <0x0 0x40 0x0 0x4c>, 193 <0x0 0xe8 0x0 0x18>, 194 <0x0 0x120 0x0 0x18>, 195 <0x0 0x2c0 0x0 0x40>, 196 <0x0 0x340 0x0 0x1c>; 197 reg-names = "gpio", 198 "pull", 199 "pull-enable", 200 "mux", 201 "ds"; 202 gpio-controller; 203 #gpio-cells = <2>; 204 gpio-ranges = <&periphs_pinctrl 0 0 86>; 205 }; 206 207 cec_ao_a_h_pins: cec_ao_a_h { 208 mux { 209 groups = "cec_ao_a_h"; 210 function = "cec_ao_a_h"; 211 bias-disable; 212 }; 213 }; 214 215 cec_ao_b_h_pins: cec_ao_b_h { 216 mux { 217 groups = "cec_ao_b_h"; 218 function = "cec_ao_b_h"; 219 bias-disable; 220 }; 221 }; 222 223 emmc_pins: emmc { 224 mux-0 { 225 groups = "emmc_nand_d0", 226 "emmc_nand_d1", 227 "emmc_nand_d2", 228 "emmc_nand_d3", 229 "emmc_nand_d4", 230 "emmc_nand_d5", 231 "emmc_nand_d6", 232 "emmc_nand_d7", 233 "emmc_cmd"; 234 function = "emmc"; 235 bias-pull-up; 236 drive-strength-microamp = <4000>; 237 }; 238 239 mux-1 { 240 groups = "emmc_clk"; 241 function = "emmc"; 242 bias-disable; 243 drive-strength-microamp = <4000>; 244 }; 245 }; 246 247 emmc_ds_pins: emmc-ds { 248 mux { 249 groups = "emmc_nand_ds"; 250 function = "emmc"; 251 bias-pull-down; 252 drive-strength-microamp = <4000>; 253 }; 254 }; 255 256 emmc_clk_gate_pins: emmc_clk_gate { 257 mux { 258 groups = "BOOT_8"; 259 function = "gpio_periphs"; 260 bias-pull-down; 261 drive-strength-microamp = <4000>; 262 }; 263 }; 264 265 hdmitx_ddc_pins: hdmitx_ddc { 266 mux { 267 groups = "hdmitx_sda", 268 "hdmitx_sck"; 269 function = "hdmitx"; 270 bias-disable; 271 }; 272 }; 273 274 hdmitx_hpd_pins: hdmitx_hpd { 275 mux { 276 groups = "hdmitx_hpd_in"; 277 function = "hdmitx"; 278 bias-disable; 279 }; 280 }; 281 282 283 i2c0_sda_c_pins: i2c0-sda-c { 284 mux { 285 groups = "i2c0_sda_c"; 286 function = "i2c0"; 287 bias-disable; 288 drive-strength-microamp = <3000>; 289 290 }; 291 }; 292 293 i2c0_sck_c_pins: i2c0-sck-c { 294 mux { 295 groups = "i2c0_sck_c"; 296 function = "i2c0"; 297 bias-disable; 298 drive-strength-microamp = <3000>; 299 }; 300 }; 301 302 i2c0_sda_z0_pins: i2c0-sda-z0 { 303 mux { 304 groups = "i2c0_sda_z0"; 305 function = "i2c0"; 306 bias-disable; 307 drive-strength-microamp = <3000>; 308 }; 309 }; 310 311 i2c0_sck_z1_pins: i2c0-sck-z1 { 312 mux { 313 groups = "i2c0_sck_z1"; 314 function = "i2c0"; 315 bias-disable; 316 drive-strength-microamp = <3000>; 317 }; 318 }; 319 320 i2c0_sda_z7_pins: i2c0-sda-z7 { 321 mux { 322 groups = "i2c0_sda_z7"; 323 function = "i2c0"; 324 bias-disable; 325 drive-strength-microamp = <3000>; 326 }; 327 }; 328 329 i2c0_sda_z8_pins: i2c0-sda-z8 { 330 mux { 331 groups = "i2c0_sda_z8"; 332 function = "i2c0"; 333 bias-disable; 334 drive-strength-microamp = <3000>; 335 }; 336 }; 337 338 i2c1_sda_x_pins: i2c1-sda-x { 339 mux { 340 groups = "i2c1_sda_x"; 341 function = "i2c1"; 342 bias-disable; 343 drive-strength-microamp = <3000>; 344 }; 345 }; 346 347 i2c1_sck_x_pins: i2c1-sck-x { 348 mux { 349 groups = "i2c1_sck_x"; 350 function = "i2c1"; 351 bias-disable; 352 drive-strength-microamp = <3000>; 353 }; 354 }; 355 356 i2c1_sda_h2_pins: i2c1-sda-h2 { 357 mux { 358 groups = "i2c1_sda_h2"; 359 function = "i2c1"; 360 bias-disable; 361 drive-strength-microamp = <3000>; 362 }; 363 }; 364 365 i2c1_sck_h3_pins: i2c1-sck-h3 { 366 mux { 367 groups = "i2c1_sck_h3"; 368 function = "i2c1"; 369 bias-disable; 370 drive-strength-microamp = <3000>; 371 }; 372 }; 373 374 i2c1_sda_h6_pins: i2c1-sda-h6 { 375 mux { 376 groups = "i2c1_sda_h6"; 377 function = "i2c1"; 378 bias-disable; 379 drive-strength-microamp = <3000>; 380 }; 381 }; 382 383 i2c1_sck_h7_pins: i2c1-sck-h7 { 384 mux { 385 groups = "i2c1_sck_h7"; 386 function = "i2c1"; 387 bias-disable; 388 drive-strength-microamp = <3000>; 389 }; 390 }; 391 392 i2c2_sda_x_pins: i2c2-sda-x { 393 mux { 394 groups = "i2c2_sda_x"; 395 function = "i2c2"; 396 bias-disable; 397 drive-strength-microamp = <3000>; 398 }; 399 }; 400 401 i2c2_sck_x_pins: i2c2-sck-x { 402 mux { 403 groups = "i2c2_sck_x"; 404 function = "i2c2"; 405 bias-disable; 406 drive-strength-microamp = <3000>; 407 }; 408 }; 409 410 i2c2_sda_z_pins: i2c2-sda-z { 411 mux { 412 groups = "i2c2_sda_z"; 413 function = "i2c2"; 414 bias-disable; 415 drive-strength-microamp = <3000>; 416 }; 417 }; 418 419 i2c2_sck_z_pins: i2c2-sck-z { 420 mux { 421 groups = "i2c2_sck_z"; 422 function = "i2c2"; 423 bias-disable; 424 drive-strength-microamp = <3000>; 425 }; 426 }; 427 428 i2c3_sda_h_pins: i2c3-sda-h { 429 mux { 430 groups = "i2c3_sda_h"; 431 function = "i2c3"; 432 bias-disable; 433 drive-strength-microamp = <3000>; 434 }; 435 }; 436 437 i2c3_sck_h_pins: i2c3-sck-h { 438 mux { 439 groups = "i2c3_sck_h"; 440 function = "i2c3"; 441 bias-disable; 442 drive-strength-microamp = <3000>; 443 }; 444 }; 445 446 i2c3_sda_a_pins: i2c3-sda-a { 447 mux { 448 groups = "i2c3_sda_a"; 449 function = "i2c3"; 450 bias-disable; 451 drive-strength-microamp = <3000>; 452 }; 453 }; 454 455 i2c3_sck_a_pins: i2c3-sck-a { 456 mux { 457 groups = "i2c3_sck_a"; 458 function = "i2c3"; 459 bias-disable; 460 drive-strength-microamp = <3000>; 461 }; 462 }; 463 464 mclk0_a_pins: mclk0-a { 465 mux { 466 groups = "mclk0_a"; 467 function = "mclk0"; 468 bias-disable; 469 drive-strength-microamp = <3000>; 470 }; 471 }; 472 473 mclk1_a_pins: mclk1-a { 474 mux { 475 groups = "mclk1_a"; 476 function = "mclk1"; 477 bias-disable; 478 drive-strength-microamp = <3000>; 479 }; 480 }; 481 482 mclk1_x_pins: mclk1-x { 483 mux { 484 groups = "mclk1_x"; 485 function = "mclk1"; 486 bias-disable; 487 drive-strength-microamp = <3000>; 488 }; 489 }; 490 491 mclk1_z_pins: mclk1-z { 492 mux { 493 groups = "mclk1_z"; 494 function = "mclk1"; 495 bias-disable; 496 drive-strength-microamp = <3000>; 497 }; 498 }; 499 500 pwm_a_pins: pwm-a { 501 mux { 502 groups = "pwm_a"; 503 function = "pwm_a"; 504 bias-disable; 505 }; 506 }; 507 508 pwm_b_x7_pins: pwm-b-x7 { 509 mux { 510 groups = "pwm_b_x7"; 511 function = "pwm_b"; 512 bias-disable; 513 }; 514 }; 515 516 pwm_b_x19_pins: pwm-b-x19 { 517 mux { 518 groups = "pwm_b_x19"; 519 function = "pwm_b"; 520 bias-disable; 521 }; 522 }; 523 524 pwm_c_c_pins: pwm-c-c { 525 mux { 526 groups = "pwm_c_c"; 527 function = "pwm_c"; 528 bias-disable; 529 }; 530 }; 531 532 pwm_c_x5_pins: pwm-c-x5 { 533 mux { 534 groups = "pwm_c_x5"; 535 function = "pwm_c"; 536 bias-disable; 537 }; 538 }; 539 540 pwm_c_x8_pins: pwm-c-x8 { 541 mux { 542 groups = "pwm_c_x8"; 543 function = "pwm_c"; 544 bias-disable; 545 }; 546 }; 547 548 pwm_d_x3_pins: pwm-d-x3 { 549 mux { 550 groups = "pwm_d_x3"; 551 function = "pwm_d"; 552 bias-disable; 553 }; 554 }; 555 556 pwm_d_x6_pins: pwm-d-x6 { 557 mux { 558 groups = "pwm_d_x6"; 559 function = "pwm_d"; 560 bias-disable; 561 }; 562 }; 563 564 pwm_e_pins: pwm-e { 565 mux { 566 groups = "pwm_e"; 567 function = "pwm_e"; 568 bias-disable; 569 }; 570 }; 571 572 pwm_f_x_pins: pwm-f-x { 573 mux { 574 groups = "pwm_f_x"; 575 function = "pwm_f"; 576 bias-disable; 577 }; 578 }; 579 580 pwm_f_h_pins: pwm-f-h { 581 mux { 582 groups = "pwm_f_h"; 583 function = "pwm_f"; 584 bias-disable; 585 }; 586 }; 587 588 sdcard_c_pins: sdcard_c { 589 mux-0 { 590 groups = "sdcard_d0_c", 591 "sdcard_d1_c", 592 "sdcard_d2_c", 593 "sdcard_d3_c", 594 "sdcard_cmd_c"; 595 function = "sdcard"; 596 bias-pull-up; 597 drive-strength-microamp = <4000>; 598 }; 599 600 mux-1 { 601 groups = "sdcard_clk_c"; 602 function = "sdcard"; 603 bias-disable; 604 drive-strength-microamp = <4000>; 605 }; 606 }; 607 608 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 609 mux { 610 groups = "GPIOC_4"; 611 function = "gpio_periphs"; 612 bias-pull-down; 613 drive-strength-microamp = <4000>; 614 }; 615 }; 616 617 sdcard_z_pins: sdcard_z { 618 mux-0 { 619 groups = "sdcard_d0_z", 620 "sdcard_d1_z", 621 "sdcard_d2_z", 622 "sdcard_d3_z", 623 "sdcard_cmd_z"; 624 function = "sdcard"; 625 bias-pull-up; 626 drive-strength-microamp = <4000>; 627 }; 628 629 mux-1 { 630 groups = "sdcard_clk_z"; 631 function = "sdcard"; 632 bias-disable; 633 drive-strength-microamp = <4000>; 634 }; 635 }; 636 637 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 638 mux { 639 groups = "GPIOZ_6"; 640 function = "gpio_periphs"; 641 bias-pull-down; 642 drive-strength-microamp = <4000>; 643 }; 644 }; 645 646 tdm_a_din0_pins: tdm-a-din0 { 647 mux { 648 groups = "tdm_a_din0"; 649 function = "tdm_a"; 650 bias-disable; 651 }; 652 }; 653 654 655 tdm_a_din1_pins: tdm-a-din1 { 656 mux { 657 groups = "tdm_a_din1"; 658 function = "tdm_a"; 659 bias-disable; 660 }; 661 }; 662 663 tdm_a_dout0_pins: tdm-a-dout0 { 664 mux { 665 groups = "tdm_a_dout0"; 666 function = "tdm_a"; 667 bias-disable; 668 drive-strength-microamp = <3000>; 669 }; 670 }; 671 672 tdm_a_dout1_pins: tdm-a-dout1 { 673 mux { 674 groups = "tdm_a_dout1"; 675 function = "tdm_a"; 676 bias-disable; 677 drive-strength-microamp = <3000>; 678 }; 679 }; 680 681 tdm_a_fs_pins: tdm-a-fs { 682 mux { 683 groups = "tdm_a_fs"; 684 function = "tdm_a"; 685 bias-disable; 686 drive-strength-microamp = <3000>; 687 }; 688 }; 689 690 tdm_a_sclk_pins: tdm-a-sclk { 691 mux { 692 groups = "tdm_a_sclk"; 693 function = "tdm_a"; 694 bias-disable; 695 drive-strength-microamp = <3000>; 696 }; 697 }; 698 699 tdm_a_slv_fs_pins: tdm-a-slv-fs { 700 mux { 701 groups = "tdm_a_slv_fs"; 702 function = "tdm_a"; 703 bias-disable; 704 }; 705 }; 706 707 708 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 709 mux { 710 groups = "tdm_a_slv_sclk"; 711 function = "tdm_a"; 712 bias-disable; 713 }; 714 }; 715 716 tdm_b_din0_pins: tdm-b-din0 { 717 mux { 718 groups = "tdm_b_din0"; 719 function = "tdm_b"; 720 bias-disable; 721 }; 722 }; 723 724 tdm_b_din1_pins: tdm-b-din1 { 725 mux { 726 groups = "tdm_b_din1"; 727 function = "tdm_b"; 728 bias-disable; 729 }; 730 }; 731 732 tdm_b_din2_pins: tdm-b-din2 { 733 mux { 734 groups = "tdm_b_din2"; 735 function = "tdm_b"; 736 bias-disable; 737 }; 738 }; 739 740 tdm_b_din3_a_pins: tdm-b-din3-a { 741 mux { 742 groups = "tdm_b_din3_a"; 743 function = "tdm_b"; 744 bias-disable; 745 }; 746 }; 747 748 tdm_b_din3_h_pins: tdm-b-din3-h { 749 mux { 750 groups = "tdm_b_din3_h"; 751 function = "tdm_b"; 752 bias-disable; 753 }; 754 }; 755 756 tdm_b_dout0_pins: tdm-b-dout0 { 757 mux { 758 groups = "tdm_b_dout0"; 759 function = "tdm_b"; 760 bias-disable; 761 drive-strength-microamp = <3000>; 762 }; 763 }; 764 765 tdm_b_dout1_pins: tdm-b-dout1 { 766 mux { 767 groups = "tdm_b_dout1"; 768 function = "tdm_b"; 769 bias-disable; 770 drive-strength-microamp = <3000>; 771 }; 772 }; 773 774 tdm_b_dout2_pins: tdm-b-dout2 { 775 mux { 776 groups = "tdm_b_dout2"; 777 function = "tdm_b"; 778 bias-disable; 779 drive-strength-microamp = <3000>; 780 }; 781 }; 782 783 tdm_b_dout3_a_pins: tdm-b-dout3-a { 784 mux { 785 groups = "tdm_b_dout3_a"; 786 function = "tdm_b"; 787 bias-disable; 788 drive-strength-microamp = <3000>; 789 }; 790 }; 791 792 tdm_b_dout3_h_pins: tdm-b-dout3-h { 793 mux { 794 groups = "tdm_b_dout3_h"; 795 function = "tdm_b"; 796 bias-disable; 797 drive-strength-microamp = <3000>; 798 }; 799 }; 800 801 tdm_b_fs_pins: tdm-b-fs { 802 mux { 803 groups = "tdm_b_fs"; 804 function = "tdm_b"; 805 bias-disable; 806 drive-strength-microamp = <3000>; 807 }; 808 }; 809 810 tdm_b_sclk_pins: tdm-b-sclk { 811 mux { 812 groups = "tdm_b_sclk"; 813 function = "tdm_b"; 814 bias-disable; 815 drive-strength-microamp = <3000>; 816 }; 817 }; 818 819 tdm_b_slv_fs_pins: tdm-b-slv-fs { 820 mux { 821 groups = "tdm_b_slv_fs"; 822 function = "tdm_b"; 823 bias-disable; 824 }; 825 }; 826 827 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 828 mux { 829 groups = "tdm_b_slv_sclk"; 830 function = "tdm_b"; 831 bias-disable; 832 }; 833 }; 834 835 tdm_c_din0_a_pins: tdm-c-din0-a { 836 mux { 837 groups = "tdm_c_din0_a"; 838 function = "tdm_c"; 839 bias-disable; 840 }; 841 }; 842 843 tdm_c_din0_z_pins: tdm-c-din0-z { 844 mux { 845 groups = "tdm_c_din0_z"; 846 function = "tdm_c"; 847 bias-disable; 848 }; 849 }; 850 851 tdm_c_din1_a_pins: tdm-c-din1-a { 852 mux { 853 groups = "tdm_c_din1_a"; 854 function = "tdm_c"; 855 bias-disable; 856 }; 857 }; 858 859 tdm_c_din1_z_pins: tdm-c-din1-z { 860 mux { 861 groups = "tdm_c_din1_z"; 862 function = "tdm_c"; 863 bias-disable; 864 }; 865 }; 866 867 tdm_c_din2_a_pins: tdm-c-din2-a { 868 mux { 869 groups = "tdm_c_din2_a"; 870 function = "tdm_c"; 871 bias-disable; 872 }; 873 }; 874 875 tdm_c_din2_z_pins: tdm-c-din2-z { 876 mux { 877 groups = "tdm_c_din2_z"; 878 function = "tdm_c"; 879 bias-disable; 880 }; 881 }; 882 883 tdm_c_din3_a_pins: tdm-c-din3-a { 884 mux { 885 groups = "tdm_c_din3_a"; 886 function = "tdm_c"; 887 bias-disable; 888 }; 889 }; 890 891 tdm_c_din3_z_pins: tdm-c-din3-z { 892 mux { 893 groups = "tdm_c_din3_z"; 894 function = "tdm_c"; 895 bias-disable; 896 }; 897 }; 898 899 tdm_c_dout0_a_pins: tdm-c-dout0-a { 900 mux { 901 groups = "tdm_c_dout0_a"; 902 function = "tdm_c"; 903 bias-disable; 904 drive-strength-microamp = <3000>; 905 }; 906 }; 907 908 tdm_c_dout0_z_pins: tdm-c-dout0-z { 909 mux { 910 groups = "tdm_c_dout0_z"; 911 function = "tdm_c"; 912 bias-disable; 913 drive-strength-microamp = <3000>; 914 }; 915 }; 916 917 tdm_c_dout1_a_pins: tdm-c-dout1-a { 918 mux { 919 groups = "tdm_c_dout1_a"; 920 function = "tdm_c"; 921 bias-disable; 922 drive-strength-microamp = <3000>; 923 }; 924 }; 925 926 tdm_c_dout1_z_pins: tdm-c-dout1-z { 927 mux { 928 groups = "tdm_c_dout1_z"; 929 function = "tdm_c"; 930 bias-disable; 931 drive-strength-microamp = <3000>; 932 }; 933 }; 934 935 tdm_c_dout2_a_pins: tdm-c-dout2-a { 936 mux { 937 groups = "tdm_c_dout2_a"; 938 function = "tdm_c"; 939 bias-disable; 940 drive-strength-microamp = <3000>; 941 }; 942 }; 943 944 tdm_c_dout2_z_pins: tdm-c-dout2-z { 945 mux { 946 groups = "tdm_c_dout2_z"; 947 function = "tdm_c"; 948 bias-disable; 949 drive-strength-microamp = <3000>; 950 }; 951 }; 952 953 tdm_c_dout3_a_pins: tdm-c-dout3-a { 954 mux { 955 groups = "tdm_c_dout3_a"; 956 function = "tdm_c"; 957 bias-disable; 958 drive-strength-microamp = <3000>; 959 }; 960 }; 961 962 tdm_c_dout3_z_pins: tdm-c-dout3-z { 963 mux { 964 groups = "tdm_c_dout3_z"; 965 function = "tdm_c"; 966 bias-disable; 967 drive-strength-microamp = <3000>; 968 }; 969 }; 970 971 tdm_c_fs_a_pins: tdm-c-fs-a { 972 mux { 973 groups = "tdm_c_fs_a"; 974 function = "tdm_c"; 975 bias-disable; 976 drive-strength-microamp = <3000>; 977 }; 978 }; 979 980 tdm_c_fs_z_pins: tdm-c-fs-z { 981 mux { 982 groups = "tdm_c_fs_z"; 983 function = "tdm_c"; 984 bias-disable; 985 drive-strength-microamp = <3000>; 986 }; 987 }; 988 989 tdm_c_sclk_a_pins: tdm-c-sclk-a { 990 mux { 991 groups = "tdm_c_sclk_a"; 992 function = "tdm_c"; 993 bias-disable; 994 drive-strength-microamp = <3000>; 995 }; 996 }; 997 998 tdm_c_sclk_z_pins: tdm-c-sclk-z { 999 mux { 1000 groups = "tdm_c_sclk_z"; 1001 function = "tdm_c"; 1002 bias-disable; 1003 drive-strength-microamp = <3000>; 1004 }; 1005 }; 1006 1007 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1008 mux { 1009 groups = "tdm_c_slv_fs_a"; 1010 function = "tdm_c"; 1011 bias-disable; 1012 }; 1013 }; 1014 1015 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1016 mux { 1017 groups = "tdm_c_slv_fs_z"; 1018 function = "tdm_c"; 1019 bias-disable; 1020 }; 1021 }; 1022 1023 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1024 mux { 1025 groups = "tdm_c_slv_sclk_a"; 1026 function = "tdm_c"; 1027 bias-disable; 1028 }; 1029 }; 1030 1031 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1032 mux { 1033 groups = "tdm_c_slv_sclk_z"; 1034 function = "tdm_c"; 1035 bias-disable; 1036 }; 1037 }; 1038 1039 uart_a_pins: uart-a { 1040 mux { 1041 groups = "uart_a_tx", 1042 "uart_a_rx"; 1043 function = "uart_a"; 1044 bias-disable; 1045 }; 1046 }; 1047 1048 uart_a_cts_rts_pins: uart-a-cts-rts { 1049 mux { 1050 groups = "uart_a_cts", 1051 "uart_a_rts"; 1052 function = "uart_a"; 1053 bias-disable; 1054 }; 1055 }; 1056 1057 uart_b_pins: uart-b { 1058 mux { 1059 groups = "uart_b_tx", 1060 "uart_b_rx"; 1061 function = "uart_b"; 1062 bias-disable; 1063 }; 1064 }; 1065 1066 uart_c_pins: uart-c { 1067 mux { 1068 groups = "uart_c_tx", 1069 "uart_c_rx"; 1070 function = "uart_c"; 1071 bias-disable; 1072 }; 1073 }; 1074 1075 uart_c_cts_rts_pins: uart-c-cts-rts { 1076 mux { 1077 groups = "uart_c_cts", 1078 "uart_c_rts"; 1079 function = "uart_c"; 1080 bias-disable; 1081 }; 1082 }; 1083 }; 1084 }; 1085 1086 usb2_phy0: phy@36000 { 1087 compatible = "amlogic,g12a-usb2-phy"; 1088 reg = <0x0 0x36000 0x0 0x2000>; 1089 clocks = <&xtal>; 1090 clock-names = "xtal"; 1091 resets = <&reset RESET_USB_PHY20>; 1092 reset-names = "phy"; 1093 #phy-cells = <0>; 1094 }; 1095 1096 dmc: bus@38000 { 1097 compatible = "simple-bus"; 1098 reg = <0x0 0x38000 0x0 0x400>; 1099 #address-cells = <2>; 1100 #size-cells = <2>; 1101 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1102 1103 canvas: video-lut@48 { 1104 compatible = "amlogic,canvas"; 1105 reg = <0x0 0x48 0x0 0x14>; 1106 }; 1107 }; 1108 1109 usb2_phy1: phy@3a000 { 1110 compatible = "amlogic,g12a-usb2-phy"; 1111 reg = <0x0 0x3a000 0x0 0x2000>; 1112 clocks = <&xtal>; 1113 clock-names = "xtal"; 1114 resets = <&reset RESET_USB_PHY21>; 1115 reset-names = "phy"; 1116 #phy-cells = <0>; 1117 }; 1118 1119 hiu: bus@3c000 { 1120 compatible = "simple-bus"; 1121 reg = <0x0 0x3c000 0x0 0x1400>; 1122 #address-cells = <2>; 1123 #size-cells = <2>; 1124 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1125 1126 hhi: system-controller@0 { 1127 compatible = "amlogic,meson-gx-hhi-sysctrl", 1128 "simple-mfd", "syscon"; 1129 reg = <0 0 0 0x400>; 1130 1131 clkc: clock-controller { 1132 compatible = "amlogic,g12a-clkc"; 1133 #clock-cells = <1>; 1134 clocks = <&xtal>; 1135 clock-names = "xtal"; 1136 }; 1137 }; 1138 }; 1139 1140 audio: bus@42000 { 1141 compatible = "simple-bus"; 1142 reg = <0x0 0x42000 0x0 0x2000>; 1143 #address-cells = <2>; 1144 #size-cells = <2>; 1145 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1146 1147 clkc_audio: clock-controller@0 { 1148 status = "disabled"; 1149 compatible = "amlogic,g12a-audio-clkc"; 1150 reg = <0x0 0x0 0x0 0xb4>; 1151 #clock-cells = <1>; 1152 1153 clocks = <&clkc CLKID_AUDIO>, 1154 <&clkc CLKID_MPLL0>, 1155 <&clkc CLKID_MPLL1>, 1156 <&clkc CLKID_MPLL2>, 1157 <&clkc CLKID_MPLL3>, 1158 <&clkc CLKID_HIFI_PLL>, 1159 <&clkc CLKID_FCLK_DIV3>, 1160 <&clkc CLKID_FCLK_DIV4>, 1161 <&clkc CLKID_GP0_PLL>; 1162 clock-names = "pclk", 1163 "mst_in0", 1164 "mst_in1", 1165 "mst_in2", 1166 "mst_in3", 1167 "mst_in4", 1168 "mst_in5", 1169 "mst_in6", 1170 "mst_in7"; 1171 1172 resets = <&reset RESET_AUDIO>; 1173 }; 1174 1175 toddr_a: audio-controller@100 { 1176 compatible = "amlogic,g12a-toddr", 1177 "amlogic,axg-toddr"; 1178 reg = <0x0 0x100 0x0 0x1c>; 1179 #sound-dai-cells = <0>; 1180 sound-name-prefix = "TODDR_A"; 1181 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1182 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1183 resets = <&arb AXG_ARB_TODDR_A>; 1184 status = "disabled"; 1185 }; 1186 1187 toddr_b: audio-controller@140 { 1188 compatible = "amlogic,g12a-toddr", 1189 "amlogic,axg-toddr"; 1190 reg = <0x0 0x140 0x0 0x1c>; 1191 #sound-dai-cells = <0>; 1192 sound-name-prefix = "TODDR_B"; 1193 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1194 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1195 resets = <&arb AXG_ARB_TODDR_B>; 1196 status = "disabled"; 1197 }; 1198 1199 toddr_c: audio-controller@180 { 1200 compatible = "amlogic,g12a-toddr", 1201 "amlogic,axg-toddr"; 1202 reg = <0x0 0x180 0x0 0x1c>; 1203 #sound-dai-cells = <0>; 1204 sound-name-prefix = "TODDR_C"; 1205 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1206 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1207 resets = <&arb AXG_ARB_TODDR_C>; 1208 status = "disabled"; 1209 }; 1210 1211 frddr_a: audio-controller@1c0 { 1212 compatible = "amlogic,g12a-frddr", 1213 "amlogic,axg-frddr"; 1214 reg = <0x0 0x1c0 0x0 0x1c>; 1215 #sound-dai-cells = <0>; 1216 sound-name-prefix = "FRDDR_A"; 1217 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1218 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1219 resets = <&arb AXG_ARB_FRDDR_A>; 1220 status = "disabled"; 1221 }; 1222 1223 frddr_b: audio-controller@200 { 1224 compatible = "amlogic,g12a-frddr", 1225 "amlogic,axg-frddr"; 1226 reg = <0x0 0x200 0x0 0x1c>; 1227 #sound-dai-cells = <0>; 1228 sound-name-prefix = "FRDDR_B"; 1229 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1230 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1231 resets = <&arb AXG_ARB_FRDDR_B>; 1232 status = "disabled"; 1233 }; 1234 1235 frddr_c: audio-controller@240 { 1236 compatible = "amlogic,g12a-frddr", 1237 "amlogic,axg-frddr"; 1238 reg = <0x0 0x240 0x0 0x1c>; 1239 #sound-dai-cells = <0>; 1240 sound-name-prefix = "FRDDR_C"; 1241 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1242 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1243 resets = <&arb AXG_ARB_FRDDR_C>; 1244 status = "disabled"; 1245 }; 1246 1247 arb: reset-controller@280 { 1248 status = "disabled"; 1249 compatible = "amlogic,meson-axg-audio-arb"; 1250 reg = <0x0 0x280 0x0 0x4>; 1251 #reset-cells = <1>; 1252 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1253 }; 1254 1255 tdmin_a: audio-controller@300 { 1256 compatible = "amlogic,g12a-tdmin", 1257 "amlogic,axg-tdmin"; 1258 reg = <0x0 0x300 0x0 0x40>; 1259 sound-name-prefix = "TDMIN_A"; 1260 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1261 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1262 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1263 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1264 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1265 clock-names = "pclk", "sclk", "sclk_sel", 1266 "lrclk", "lrclk_sel"; 1267 status = "disabled"; 1268 }; 1269 1270 tdmin_b: audio-controller@340 { 1271 compatible = "amlogic,g12a-tdmin", 1272 "amlogic,axg-tdmin"; 1273 reg = <0x0 0x340 0x0 0x40>; 1274 sound-name-prefix = "TDMIN_B"; 1275 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1276 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1277 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1278 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1279 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1280 clock-names = "pclk", "sclk", "sclk_sel", 1281 "lrclk", "lrclk_sel"; 1282 status = "disabled"; 1283 }; 1284 1285 tdmin_c: audio-controller@380 { 1286 compatible = "amlogic,g12a-tdmin", 1287 "amlogic,axg-tdmin"; 1288 reg = <0x0 0x380 0x0 0x40>; 1289 sound-name-prefix = "TDMIN_C"; 1290 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1291 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1292 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1293 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1294 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1295 clock-names = "pclk", "sclk", "sclk_sel", 1296 "lrclk", "lrclk_sel"; 1297 status = "disabled"; 1298 }; 1299 1300 tdmin_lb: audio-controller@3c0 { 1301 compatible = "amlogic,g12a-tdmin", 1302 "amlogic,axg-tdmin"; 1303 reg = <0x0 0x3c0 0x0 0x40>; 1304 sound-name-prefix = "TDMIN_LB"; 1305 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1306 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1307 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1308 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1309 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1310 clock-names = "pclk", "sclk", "sclk_sel", 1311 "lrclk", "lrclk_sel"; 1312 status = "disabled"; 1313 }; 1314 1315 tdmout_a: audio-controller@500 { 1316 compatible = "amlogic,g12a-tdmout"; 1317 reg = <0x0 0x500 0x0 0x40>; 1318 sound-name-prefix = "TDMOUT_A"; 1319 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1320 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1321 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1322 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1323 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1324 clock-names = "pclk", "sclk", "sclk_sel", 1325 "lrclk", "lrclk_sel"; 1326 status = "disabled"; 1327 }; 1328 1329 tdmout_b: audio-controller@540 { 1330 compatible = "amlogic,g12a-tdmout"; 1331 reg = <0x0 0x540 0x0 0x40>; 1332 sound-name-prefix = "TDMOUT_B"; 1333 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1334 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1335 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1336 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1337 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1338 clock-names = "pclk", "sclk", "sclk_sel", 1339 "lrclk", "lrclk_sel"; 1340 status = "disabled"; 1341 }; 1342 1343 tdmout_c: audio-controller@580 { 1344 compatible = "amlogic,g12a-tdmout"; 1345 reg = <0x0 0x580 0x0 0x40>; 1346 sound-name-prefix = "TDMOUT_C"; 1347 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1348 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1349 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1350 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1351 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1352 clock-names = "pclk", "sclk", "sclk_sel", 1353 "lrclk", "lrclk_sel"; 1354 status = "disabled"; 1355 }; 1356 }; 1357 1358 usb3_pcie_phy: phy@46000 { 1359 compatible = "amlogic,g12a-usb3-pcie-phy"; 1360 reg = <0x0 0x46000 0x0 0x2000>; 1361 clocks = <&clkc CLKID_PCIE_PLL>; 1362 clock-names = "ref_clk"; 1363 resets = <&reset RESET_PCIE_PHY>; 1364 reset-names = "phy"; 1365 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1366 assigned-clock-rates = <100000000>; 1367 #phy-cells = <1>; 1368 }; 1369 }; 1370 1371 aobus: bus@ff800000 { 1372 compatible = "simple-bus"; 1373 reg = <0x0 0xff800000 0x0 0x100000>; 1374 #address-cells = <2>; 1375 #size-cells = <2>; 1376 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1377 1378 rti: sys-ctrl@0 { 1379 compatible = "amlogic,meson-gx-ao-sysctrl", 1380 "simple-mfd", "syscon"; 1381 reg = <0x0 0x0 0x0 0x100>; 1382 #address-cells = <2>; 1383 #size-cells = <2>; 1384 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1385 1386 clkc_AO: clock-controller { 1387 compatible = "amlogic,meson-g12a-aoclkc"; 1388 #clock-cells = <1>; 1389 #reset-cells = <1>; 1390 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1391 clock-names = "xtal", "mpeg-clk"; 1392 }; 1393 1394 pwrc_vpu: power-controller-vpu { 1395 compatible = "amlogic,meson-g12a-pwrc-vpu"; 1396 #power-domain-cells = <0>; 1397 amlogic,hhi-sysctrl = <&hhi>; 1398 resets = <&reset RESET_VIU>, 1399 <&reset RESET_VENC>, 1400 <&reset RESET_VCBUS>, 1401 <&reset RESET_BT656>, 1402 <&reset RESET_RDMA>, 1403 <&reset RESET_VENCI>, 1404 <&reset RESET_VENCP>, 1405 <&reset RESET_VDAC>, 1406 <&reset RESET_VDI6>, 1407 <&reset RESET_VENCL>, 1408 <&reset RESET_VID_LOCK>; 1409 clocks = <&clkc CLKID_VPU>, 1410 <&clkc CLKID_VAPB>; 1411 clock-names = "vpu", "vapb"; 1412 /* 1413 * VPU clocking is provided by two identical clock paths 1414 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1415 * free mux to safely change frequency while running. 1416 * Same for VAPB but with a final gate after the glitch free mux. 1417 */ 1418 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1419 <&clkc CLKID_VPU_0>, 1420 <&clkc CLKID_VPU>, /* Glitch free mux */ 1421 <&clkc CLKID_VAPB_0_SEL>, 1422 <&clkc CLKID_VAPB_0>, 1423 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1424 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1425 <0>, /* Do Nothing */ 1426 <&clkc CLKID_VPU_0>, 1427 <&clkc CLKID_FCLK_DIV4>, 1428 <0>, /* Do Nothing */ 1429 <&clkc CLKID_VAPB_0>; 1430 assigned-clock-rates = <0>, /* Do Nothing */ 1431 <666666666>, 1432 <0>, /* Do Nothing */ 1433 <0>, /* Do Nothing */ 1434 <250000000>, 1435 <0>; /* Do Nothing */ 1436 }; 1437 1438 ao_pinctrl: pinctrl@14 { 1439 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1440 #address-cells = <2>; 1441 #size-cells = <2>; 1442 ranges; 1443 1444 gpio_ao: bank@14 { 1445 reg = <0x0 0x14 0x0 0x8>, 1446 <0x0 0x1c 0x0 0x8>, 1447 <0x0 0x24 0x0 0x14>; 1448 reg-names = "mux", 1449 "ds", 1450 "gpio"; 1451 gpio-controller; 1452 #gpio-cells = <2>; 1453 gpio-ranges = <&ao_pinctrl 0 0 15>; 1454 }; 1455 1456 i2c_ao_sck_pins: i2c_ao_sck_pins { 1457 mux { 1458 groups = "i2c_ao_sck"; 1459 function = "i2c_ao"; 1460 bias-disable; 1461 drive-strength-microamp = <3000>; 1462 }; 1463 }; 1464 1465 i2c_ao_sda_pins: i2c_ao_sda { 1466 mux { 1467 groups = "i2c_ao_sda"; 1468 function = "i2c_ao"; 1469 bias-disable; 1470 drive-strength-microamp = <3000>; 1471 }; 1472 }; 1473 1474 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1475 mux { 1476 groups = "i2c_ao_sck_e"; 1477 function = "i2c_ao"; 1478 bias-disable; 1479 drive-strength-microamp = <3000>; 1480 }; 1481 }; 1482 1483 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1484 mux { 1485 groups = "i2c_ao_sda_e"; 1486 function = "i2c_ao"; 1487 bias-disable; 1488 drive-strength-microamp = <3000>; 1489 }; 1490 }; 1491 1492 mclk0_ao_pins: mclk0-ao { 1493 mux { 1494 groups = "mclk0_ao"; 1495 function = "mclk0_ao"; 1496 bias-disable; 1497 drive-strength-microamp = <3000>; 1498 }; 1499 }; 1500 1501 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1502 mux { 1503 groups = "tdm_ao_b_din0"; 1504 function = "tdm_ao_b"; 1505 bias-disable; 1506 }; 1507 }; 1508 1509 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1510 mux { 1511 groups = "tdm_ao_b_din1"; 1512 function = "tdm_ao_b"; 1513 bias-disable; 1514 }; 1515 }; 1516 1517 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1518 mux { 1519 groups = "tdm_ao_b_din2"; 1520 function = "tdm_ao_b"; 1521 bias-disable; 1522 }; 1523 }; 1524 1525 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1526 mux { 1527 groups = "tdm_ao_b_dout0"; 1528 function = "tdm_ao_b"; 1529 bias-disable; 1530 drive-strength-microamp = <3000>; 1531 }; 1532 }; 1533 1534 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1535 mux { 1536 groups = "tdm_ao_b_dout1"; 1537 function = "tdm_ao_b"; 1538 bias-disable; 1539 drive-strength-microamp = <3000>; 1540 }; 1541 }; 1542 1543 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1544 mux { 1545 groups = "tdm_ao_b_dout2"; 1546 function = "tdm_ao_b"; 1547 bias-disable; 1548 drive-strength-microamp = <3000>; 1549 }; 1550 }; 1551 1552 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1553 mux { 1554 groups = "tdm_ao_b_fs"; 1555 function = "tdm_ao_b"; 1556 bias-disable; 1557 drive-strength-microamp = <3000>; 1558 }; 1559 }; 1560 1561 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1562 mux { 1563 groups = "tdm_ao_b_sclk"; 1564 function = "tdm_ao_b"; 1565 bias-disable; 1566 drive-strength-microamp = <3000>; 1567 }; 1568 }; 1569 1570 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1571 mux { 1572 groups = "tdm_ao_b_slv_fs"; 1573 function = "tdm_ao_b"; 1574 bias-disable; 1575 }; 1576 }; 1577 1578 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1579 mux { 1580 groups = "tdm_ao_b_slv_sclk"; 1581 function = "tdm_ao_b"; 1582 bias-disable; 1583 }; 1584 }; 1585 1586 uart_ao_a_pins: uart-a-ao { 1587 mux { 1588 groups = "uart_ao_a_tx", 1589 "uart_ao_a_rx"; 1590 function = "uart_ao_a"; 1591 bias-disable; 1592 }; 1593 }; 1594 1595 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1596 mux { 1597 groups = "uart_ao_a_cts", 1598 "uart_ao_a_rts"; 1599 function = "uart_ao_a"; 1600 bias-disable; 1601 }; 1602 }; 1603 1604 pwm_ao_a_pins: pwm-ao-a { 1605 mux { 1606 groups = "pwm_ao_a"; 1607 function = "pwm_ao_a"; 1608 bias-disable; 1609 }; 1610 }; 1611 1612 pwm_ao_b_pins: pwm-ao-b { 1613 mux { 1614 groups = "pwm_ao_b"; 1615 function = "pwm_ao_b"; 1616 bias-disable; 1617 }; 1618 }; 1619 1620 pwm_ao_c_4_pins: pwm-ao-c-4 { 1621 mux { 1622 groups = "pwm_ao_c_4"; 1623 function = "pwm_ao_c"; 1624 bias-disable; 1625 }; 1626 }; 1627 1628 pwm_ao_c_6_pins: pwm-ao-c-6 { 1629 mux { 1630 groups = "pwm_ao_c_6"; 1631 function = "pwm_ao_c"; 1632 bias-disable; 1633 }; 1634 }; 1635 1636 pwm_ao_d_5_pins: pwm-ao-d-5 { 1637 mux { 1638 groups = "pwm_ao_d_5"; 1639 function = "pwm_ao_d"; 1640 bias-disable; 1641 }; 1642 }; 1643 1644 pwm_ao_d_10_pins: pwm-ao-d-10 { 1645 mux { 1646 groups = "pwm_ao_d_10"; 1647 function = "pwm_ao_d"; 1648 bias-disable; 1649 }; 1650 }; 1651 1652 pwm_ao_d_e_pins: pwm-ao-d-e { 1653 mux { 1654 groups = "pwm_ao_d_e"; 1655 function = "pwm_ao_d"; 1656 }; 1657 }; 1658 1659 remote_input_ao_pins: remote-input-ao { 1660 mux { 1661 groups = "remote_ao_input"; 1662 function = "remote_ao_input"; 1663 bias-disable; 1664 }; 1665 }; 1666 }; 1667 }; 1668 1669 cec_AO: cec@100 { 1670 compatible = "amlogic,meson-gx-ao-cec"; 1671 reg = <0x0 0x00100 0x0 0x14>; 1672 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 1673 clocks = <&clkc_AO CLKID_AO_CEC>; 1674 clock-names = "core"; 1675 status = "disabled"; 1676 }; 1677 1678 sec_AO: ao-secure@140 { 1679 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1680 reg = <0x0 0x140 0x0 0x140>; 1681 amlogic,has-chip-id; 1682 }; 1683 1684 cecb_AO: cec@280 { 1685 compatible = "amlogic,meson-g12a-ao-cec"; 1686 reg = <0x0 0x00280 0x0 0x1c>; 1687 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1688 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 1689 clock-names = "oscin"; 1690 status = "disabled"; 1691 }; 1692 1693 pwm_AO_cd: pwm@2000 { 1694 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 1695 reg = <0x0 0x2000 0x0 0x20>; 1696 #pwm-cells = <3>; 1697 status = "disabled"; 1698 }; 1699 1700 uart_AO: serial@3000 { 1701 compatible = "amlogic,meson-gx-uart", 1702 "amlogic,meson-ao-uart"; 1703 reg = <0x0 0x3000 0x0 0x18>; 1704 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1705 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 1706 clock-names = "xtal", "pclk", "baud"; 1707 status = "disabled"; 1708 }; 1709 1710 uart_AO_B: serial@4000 { 1711 compatible = "amlogic,meson-gx-uart", 1712 "amlogic,meson-ao-uart"; 1713 reg = <0x0 0x4000 0x0 0x18>; 1714 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1715 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1716 clock-names = "xtal", "pclk", "baud"; 1717 status = "disabled"; 1718 }; 1719 1720 i2c_AO: i2c@5000 { 1721 compatible = "amlogic,meson-axg-i2c"; 1722 status = "disabled"; 1723 reg = <0x0 0x05000 0x0 0x20>; 1724 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1725 #address-cells = <1>; 1726 #size-cells = <0>; 1727 clocks = <&clkc CLKID_I2C>; 1728 }; 1729 1730 pwm_AO_ab: pwm@7000 { 1731 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 1732 reg = <0x0 0x7000 0x0 0x20>; 1733 #pwm-cells = <3>; 1734 status = "disabled"; 1735 }; 1736 1737 ir: ir@8000 { 1738 compatible = "amlogic,meson-gxbb-ir"; 1739 reg = <0x0 0x8000 0x0 0x20>; 1740 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1741 status = "disabled"; 1742 }; 1743 1744 saradc: adc@9000 { 1745 compatible = "amlogic,meson-g12a-saradc", 1746 "amlogic,meson-saradc"; 1747 reg = <0x0 0x9000 0x0 0x48>; 1748 #io-channel-cells = <1>; 1749 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 1750 clocks = <&xtal>, 1751 <&clkc_AO CLKID_AO_SAR_ADC>, 1752 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1753 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1754 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1755 status = "disabled"; 1756 }; 1757 }; 1758 1759 vpu: vpu@ff900000 { 1760 compatible = "amlogic,meson-g12a-vpu"; 1761 reg = <0x0 0xff900000 0x0 0x100000>, 1762 <0x0 0xff63c000 0x0 0x1000>; 1763 reg-names = "vpu", "hhi"; 1764 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 1765 #address-cells = <1>; 1766 #size-cells = <0>; 1767 amlogic,canvas = <&canvas>; 1768 power-domains = <&pwrc_vpu>; 1769 1770 /* CVBS VDAC output port */ 1771 cvbs_vdac_port: port@0 { 1772 reg = <0>; 1773 }; 1774 1775 /* HDMI-TX output port */ 1776 hdmi_tx_port: port@1 { 1777 reg = <1>; 1778 1779 hdmi_tx_out: endpoint { 1780 remote-endpoint = <&hdmi_tx_in>; 1781 }; 1782 }; 1783 }; 1784 1785 gic: interrupt-controller@ffc01000 { 1786 compatible = "arm,gic-400"; 1787 reg = <0x0 0xffc01000 0 0x1000>, 1788 <0x0 0xffc02000 0 0x2000>, 1789 <0x0 0xffc04000 0 0x2000>, 1790 <0x0 0xffc06000 0 0x2000>; 1791 interrupt-controller; 1792 interrupts = <GIC_PPI 9 1793 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1794 #interrupt-cells = <3>; 1795 #address-cells = <0>; 1796 }; 1797 1798 cbus: bus@ffd00000 { 1799 compatible = "simple-bus"; 1800 reg = <0x0 0xffd00000 0x0 0x100000>; 1801 #address-cells = <2>; 1802 #size-cells = <2>; 1803 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 1804 1805 reset: reset-controller@1004 { 1806 compatible = "amlogic,meson-g12a-reset", 1807 "amlogic,meson-axg-reset"; 1808 reg = <0x0 0x1004 0x0 0x9c>; 1809 #reset-cells = <1>; 1810 }; 1811 1812 pwm_ef: pwm@19000 { 1813 compatible = "amlogic,meson-g12a-ee-pwm"; 1814 reg = <0x0 0x19000 0x0 0x20>; 1815 #pwm-cells = <3>; 1816 status = "disabled"; 1817 }; 1818 1819 pwm_cd: pwm@1a000 { 1820 compatible = "amlogic,meson-g12a-ee-pwm"; 1821 reg = <0x0 0x1a000 0x0 0x20>; 1822 #pwm-cells = <3>; 1823 status = "disabled"; 1824 }; 1825 1826 pwm_ab: pwm@1b000 { 1827 compatible = "amlogic,meson-g12a-ee-pwm"; 1828 reg = <0x0 0x1b000 0x0 0x20>; 1829 #pwm-cells = <3>; 1830 status = "disabled"; 1831 }; 1832 1833 i2c3: i2c@1c000 { 1834 compatible = "amlogic,meson-axg-i2c"; 1835 status = "disabled"; 1836 reg = <0x0 0x1c000 0x0 0x20>; 1837 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1838 #address-cells = <1>; 1839 #size-cells = <0>; 1840 clocks = <&clkc CLKID_I2C>; 1841 }; 1842 1843 i2c2: i2c@1d000 { 1844 compatible = "amlogic,meson-axg-i2c"; 1845 status = "disabled"; 1846 reg = <0x0 0x1d000 0x0 0x20>; 1847 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1848 #address-cells = <1>; 1849 #size-cells = <0>; 1850 clocks = <&clkc CLKID_I2C>; 1851 }; 1852 1853 i2c1: i2c@1e000 { 1854 compatible = "amlogic,meson-axg-i2c"; 1855 status = "disabled"; 1856 reg = <0x0 0x1e000 0x0 0x20>; 1857 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1858 #address-cells = <1>; 1859 #size-cells = <0>; 1860 clocks = <&clkc CLKID_I2C>; 1861 }; 1862 1863 i2c0: i2c@1f000 { 1864 compatible = "amlogic,meson-axg-i2c"; 1865 status = "disabled"; 1866 reg = <0x0 0x1f000 0x0 0x20>; 1867 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1868 #address-cells = <1>; 1869 #size-cells = <0>; 1870 clocks = <&clkc CLKID_I2C>; 1871 }; 1872 1873 clk_msr: clock-measure@18000 { 1874 compatible = "amlogic,meson-g12a-clk-measure"; 1875 reg = <0x0 0x18000 0x0 0x10>; 1876 }; 1877 1878 uart_C: serial@22000 { 1879 compatible = "amlogic,meson-gx-uart"; 1880 reg = <0x0 0x22000 0x0 0x18>; 1881 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 1882 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 1883 clock-names = "xtal", "pclk", "baud"; 1884 status = "disabled"; 1885 }; 1886 1887 uart_B: serial@23000 { 1888 compatible = "amlogic,meson-gx-uart"; 1889 reg = <0x0 0x23000 0x0 0x18>; 1890 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1891 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1892 clock-names = "xtal", "pclk", "baud"; 1893 status = "disabled"; 1894 }; 1895 1896 uart_A: serial@24000 { 1897 compatible = "amlogic,meson-gx-uart"; 1898 reg = <0x0 0x24000 0x0 0x18>; 1899 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1900 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1901 clock-names = "xtal", "pclk", "baud"; 1902 status = "disabled"; 1903 }; 1904 }; 1905 1906 sd_emmc_b: sd@ffe05000 { 1907 compatible = "amlogic,meson-axg-mmc"; 1908 reg = <0x0 0xffe05000 0x0 0x800>; 1909 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 1910 status = "disabled"; 1911 clocks = <&clkc CLKID_SD_EMMC_B>, 1912 <&clkc CLKID_SD_EMMC_B_CLK0>, 1913 <&clkc CLKID_FCLK_DIV2>; 1914 clock-names = "core", "clkin0", "clkin1"; 1915 resets = <&reset RESET_SD_EMMC_B>; 1916 }; 1917 1918 sd_emmc_c: mmc@ffe07000 { 1919 compatible = "amlogic,meson-axg-mmc"; 1920 reg = <0x0 0xffe07000 0x0 0x800>; 1921 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 1922 status = "disabled"; 1923 clocks = <&clkc CLKID_SD_EMMC_C>, 1924 <&clkc CLKID_SD_EMMC_C_CLK0>, 1925 <&clkc CLKID_FCLK_DIV2>; 1926 clock-names = "core", "clkin0", "clkin1"; 1927 resets = <&reset RESET_SD_EMMC_C>; 1928 }; 1929 1930 usb: usb@ffe09000 { 1931 status = "disabled"; 1932 compatible = "amlogic,meson-g12a-usb-ctrl"; 1933 reg = <0x0 0xffe09000 0x0 0xa0>; 1934 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1935 #address-cells = <2>; 1936 #size-cells = <2>; 1937 ranges; 1938 1939 clocks = <&clkc CLKID_USB>; 1940 resets = <&reset RESET_USB>; 1941 1942 dr_mode = "otg"; 1943 1944 phys = <&usb2_phy0>, <&usb2_phy1>, 1945 <&usb3_pcie_phy PHY_TYPE_USB3>; 1946 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 1947 1948 dwc2: usb@ff400000 { 1949 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 1950 reg = <0x0 0xff400000 0x0 0x40000>; 1951 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1952 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 1953 clock-names = "ddr"; 1954 phys = <&usb2_phy1>; 1955 dr_mode = "peripheral"; 1956 g-rx-fifo-size = <192>; 1957 g-np-tx-fifo-size = <128>; 1958 g-tx-fifo-size = <128 128 16 16 16>; 1959 }; 1960 1961 dwc3: usb@ff500000 { 1962 compatible = "snps,dwc3"; 1963 reg = <0x0 0xff500000 0x0 0x100000>; 1964 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1965 dr_mode = "host"; 1966 snps,dis_u2_susphy_quirk; 1967 snps,quirk-frame-length-adjustment; 1968 }; 1969 }; 1970 1971 mali: gpu@ffe40000 { 1972 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 1973 reg = <0x0 0xffe40000 0x0 0x40000>; 1974 interrupt-parent = <&gic>; 1975 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1978 interrupt-names = "gpu", "mmu", "job"; 1979 clocks = <&clkc CLKID_MALI>; 1980 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 1981 1982 /* 1983 * Mali clocking is provided by two identical clock paths 1984 * MALI_0 and MALI_1 muxed to a single clock by a glitch 1985 * free mux to safely change frequency while running. 1986 */ 1987 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 1988 <&clkc CLKID_MALI_0>, 1989 <&clkc CLKID_MALI>; /* Glitch free mux */ 1990 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 1991 <0>, /* Do Nothing */ 1992 <&clkc CLKID_MALI_0>; 1993 assigned-clock-rates = <0>, /* Do Nothing */ 1994 <800000000>, 1995 <0>; /* Do Nothing */ 1996 }; 1997 }; 1998 1999 timer { 2000 compatible = "arm,armv8-timer"; 2001 interrupts = <GIC_PPI 13 2002 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2003 <GIC_PPI 14 2004 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2005 <GIC_PPI 11 2006 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2007 <GIC_PPI 10 2008 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2009 }; 2010 2011 xtal: xtal-clk { 2012 compatible = "fixed-clock"; 2013 clock-frequency = <24000000>; 2014 clock-output-names = "xtal"; 2015 #clock-cells = <0>; 2016 }; 2017 2018}; 2019