1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13 14/ { 15 compatible = "amlogic,g12a"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <0x2>; 23 #size-cells = <0x0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a53"; 28 reg = <0x0 0x0>; 29 enable-method = "psci"; 30 next-level-cache = <&l2>; 31 }; 32 33 cpu1: cpu@1 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0 0x1>; 37 enable-method = "psci"; 38 next-level-cache = <&l2>; 39 }; 40 41 cpu2: cpu@2 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0 0x2>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 }; 48 49 cpu3: cpu@3 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x0 0x3>; 53 enable-method = "psci"; 54 next-level-cache = <&l2>; 55 }; 56 57 l2: l2-cache0 { 58 compatible = "cache"; 59 }; 60 }; 61 62 efuse: efuse { 63 compatible = "amlogic,meson-gxbb-efuse"; 64 clocks = <&clkc CLKID_EFUSE>; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 read-only; 68 }; 69 70 psci { 71 compatible = "arm,psci-1.0"; 72 method = "smc"; 73 }; 74 75 reserved-memory { 76 #address-cells = <2>; 77 #size-cells = <2>; 78 ranges; 79 80 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 81 secmon_reserved: secmon@5000000 { 82 reg = <0x0 0x05000000 0x0 0x300000>; 83 no-map; 84 }; 85 86 linux,cma { 87 compatible = "shared-dma-pool"; 88 reusable; 89 size = <0x0 0x10000000>; 90 alignment = <0x0 0x400000>; 91 linux,cma-default; 92 }; 93 }; 94 95 sm: secure-monitor { 96 compatible = "amlogic,meson-gxbb-sm"; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 apb: bus@ff600000 { 106 compatible = "simple-bus"; 107 reg = <0x0 0xff600000 0x0 0x200000>; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 111 112 hdmi_tx: hdmi-tx@0 { 113 compatible = "amlogic,meson-g12a-dw-hdmi"; 114 reg = <0x0 0x0 0x0 0x10000>; 115 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 116 resets = <&reset RESET_HDMITX_CAPB3>, 117 <&reset RESET_HDMITX_PHY>, 118 <&reset RESET_HDMITX>; 119 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 120 clocks = <&clkc CLKID_HDMI>, 121 <&clkc CLKID_HTX_PCLK>, 122 <&clkc CLKID_VPU_INTR>; 123 clock-names = "isfr", "iahb", "venci"; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 status = "disabled"; 127 128 /* VPU VENC Input */ 129 hdmi_tx_venc_port: port@0 { 130 reg = <0>; 131 132 hdmi_tx_in: endpoint { 133 remote-endpoint = <&hdmi_tx_out>; 134 }; 135 }; 136 137 /* TMDS Output */ 138 hdmi_tx_tmds_port: port@1 { 139 reg = <1>; 140 }; 141 }; 142 143 periphs: bus@34400 { 144 compatible = "simple-bus"; 145 reg = <0x0 0x34400 0x0 0x400>; 146 #address-cells = <2>; 147 #size-cells = <2>; 148 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 149 150 periphs_pinctrl: pinctrl@40 { 151 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 152 #address-cells = <2>; 153 #size-cells = <2>; 154 ranges; 155 156 gpio: bank@40 { 157 reg = <0x0 0x40 0x0 0x4c>, 158 <0x0 0xe8 0x0 0x18>, 159 <0x0 0x120 0x0 0x18>, 160 <0x0 0x2c0 0x0 0x40>, 161 <0x0 0x340 0x0 0x1c>; 162 reg-names = "gpio", 163 "pull", 164 "pull-enable", 165 "mux", 166 "ds"; 167 gpio-controller; 168 #gpio-cells = <2>; 169 gpio-ranges = <&periphs_pinctrl 0 0 86>; 170 }; 171 172 cec_ao_a_h_pins: cec_ao_a_h { 173 mux { 174 groups = "cec_ao_a_h"; 175 function = "cec_ao_a_h"; 176 bias-disable; 177 }; 178 }; 179 180 cec_ao_b_h_pins: cec_ao_b_h { 181 mux { 182 groups = "cec_ao_b_h"; 183 function = "cec_ao_b_h"; 184 bias-disable; 185 }; 186 }; 187 188 hdmitx_ddc_pins: hdmitx_ddc { 189 mux { 190 groups = "hdmitx_sda", 191 "hdmitx_sck"; 192 function = "hdmitx"; 193 bias-disable; 194 }; 195 }; 196 197 hdmitx_hpd_pins: hdmitx_hpd { 198 mux { 199 groups = "hdmitx_hpd_in"; 200 function = "hdmitx"; 201 bias-disable; 202 }; 203 }; 204 205 uart_a_pins: uart-a { 206 mux { 207 groups = "uart_a_tx", 208 "uart_a_rx"; 209 function = "uart_a"; 210 bias-disable; 211 }; 212 }; 213 214 uart_a_cts_rts_pins: uart-a-cts-rts { 215 mux { 216 groups = "uart_a_cts", 217 "uart_a_rts"; 218 function = "uart_a"; 219 bias-disable; 220 }; 221 }; 222 223 uart_b_pins: uart-b { 224 mux { 225 groups = "uart_b_tx", 226 "uart_b_rx"; 227 function = "uart_b"; 228 bias-disable; 229 }; 230 }; 231 232 uart_c_pins: uart-c { 233 mux { 234 groups = "uart_c_tx", 235 "uart_c_rx"; 236 function = "uart_c"; 237 bias-disable; 238 }; 239 }; 240 241 uart_c_cts_rts_pins: uart-c-cts-rts { 242 mux { 243 groups = "uart_c_cts", 244 "uart_c_rts"; 245 function = "uart_c"; 246 bias-disable; 247 }; 248 }; 249 }; 250 }; 251 252 usb2_phy0: phy@36000 { 253 compatible = "amlogic,g12a-usb2-phy"; 254 reg = <0x0 0x36000 0x0 0x2000>; 255 clocks = <&xtal>; 256 clock-names = "xtal"; 257 resets = <&reset RESET_USB_PHY20>; 258 reset-names = "phy"; 259 #phy-cells = <0>; 260 }; 261 262 dmc: bus@38000 { 263 compatible = "simple-bus"; 264 reg = <0x0 0x38000 0x0 0x400>; 265 #address-cells = <2>; 266 #size-cells = <2>; 267 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 268 269 canvas: video-lut@48 { 270 compatible = "amlogic,canvas"; 271 reg = <0x0 0x48 0x0 0x14>; 272 }; 273 }; 274 275 usb2_phy1: phy@3a000 { 276 compatible = "amlogic,g12a-usb2-phy"; 277 reg = <0x0 0x3a000 0x0 0x2000>; 278 clocks = <&xtal>; 279 clock-names = "xtal"; 280 resets = <&reset RESET_USB_PHY21>; 281 reset-names = "phy"; 282 #phy-cells = <0>; 283 }; 284 285 hiu: bus@3c000 { 286 compatible = "simple-bus"; 287 reg = <0x0 0x3c000 0x0 0x1400>; 288 #address-cells = <2>; 289 #size-cells = <2>; 290 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 291 292 hhi: system-controller@0 { 293 compatible = "amlogic,meson-gx-hhi-sysctrl", 294 "simple-mfd", "syscon"; 295 reg = <0 0 0 0x400>; 296 297 clkc: clock-controller { 298 compatible = "amlogic,g12a-clkc"; 299 #clock-cells = <1>; 300 clocks = <&xtal>; 301 clock-names = "xtal"; 302 }; 303 }; 304 }; 305 306 usb3_pcie_phy: phy@46000 { 307 compatible = "amlogic,g12a-usb3-pcie-phy"; 308 reg = <0x0 0x46000 0x0 0x2000>; 309 clocks = <&clkc CLKID_PCIE_PLL>; 310 clock-names = "ref_clk"; 311 resets = <&reset RESET_PCIE_PHY>; 312 reset-names = "phy"; 313 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 314 assigned-clock-rates = <100000000>; 315 #phy-cells = <1>; 316 }; 317 }; 318 319 aobus: bus@ff800000 { 320 compatible = "simple-bus"; 321 reg = <0x0 0xff800000 0x0 0x100000>; 322 #address-cells = <2>; 323 #size-cells = <2>; 324 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 325 326 rti: sys-ctrl@0 { 327 compatible = "amlogic,meson-gx-ao-sysctrl", 328 "simple-mfd", "syscon"; 329 reg = <0x0 0x0 0x0 0x100>; 330 #address-cells = <2>; 331 #size-cells = <2>; 332 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 333 334 clkc_AO: clock-controller { 335 compatible = "amlogic,meson-g12a-aoclkc"; 336 #clock-cells = <1>; 337 #reset-cells = <1>; 338 clocks = <&xtal>, <&clkc CLKID_CLK81>; 339 clock-names = "xtal", "mpeg-clk"; 340 }; 341 342 pwrc_vpu: power-controller-vpu { 343 compatible = "amlogic,meson-g12a-pwrc-vpu"; 344 #power-domain-cells = <0>; 345 amlogic,hhi-sysctrl = <&hhi>; 346 resets = <&reset RESET_VIU>, 347 <&reset RESET_VENC>, 348 <&reset RESET_VCBUS>, 349 <&reset RESET_BT656>, 350 <&reset RESET_RDMA>, 351 <&reset RESET_VENCI>, 352 <&reset RESET_VENCP>, 353 <&reset RESET_VDAC>, 354 <&reset RESET_VDI6>, 355 <&reset RESET_VENCL>, 356 <&reset RESET_VID_LOCK>; 357 clocks = <&clkc CLKID_VPU>, 358 <&clkc CLKID_VAPB>; 359 clock-names = "vpu", "vapb"; 360 /* 361 * VPU clocking is provided by two identical clock paths 362 * VPU_0 and VPU_1 muxed to a single clock by a glitch 363 * free mux to safely change frequency while running. 364 * Same for VAPB but with a final gate after the glitch free mux. 365 */ 366 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 367 <&clkc CLKID_VPU_0>, 368 <&clkc CLKID_VPU>, /* Glitch free mux */ 369 <&clkc CLKID_VAPB_0_SEL>, 370 <&clkc CLKID_VAPB_0>, 371 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 372 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 373 <0>, /* Do Nothing */ 374 <&clkc CLKID_VPU_0>, 375 <&clkc CLKID_FCLK_DIV4>, 376 <0>, /* Do Nothing */ 377 <&clkc CLKID_VAPB_0>; 378 assigned-clock-rates = <0>, /* Do Nothing */ 379 <666666666>, 380 <0>, /* Do Nothing */ 381 <0>, /* Do Nothing */ 382 <250000000>, 383 <0>; /* Do Nothing */ 384 }; 385 386 ao_pinctrl: pinctrl@14 { 387 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 388 #address-cells = <2>; 389 #size-cells = <2>; 390 ranges; 391 392 gpio_ao: bank@14 { 393 reg = <0x0 0x14 0x0 0x8>, 394 <0x0 0x1c 0x0 0x8>, 395 <0x0 0x24 0x0 0x14>; 396 reg-names = "mux", 397 "ds", 398 "gpio"; 399 gpio-controller; 400 #gpio-cells = <2>; 401 gpio-ranges = <&ao_pinctrl 0 0 15>; 402 }; 403 404 uart_ao_a_pins: uart-a-ao { 405 mux { 406 groups = "uart_ao_a_tx", 407 "uart_ao_a_rx"; 408 function = "uart_ao_a"; 409 bias-disable; 410 }; 411 }; 412 413 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 414 mux { 415 groups = "uart_ao_a_cts", 416 "uart_ao_a_rts"; 417 function = "uart_ao_a"; 418 bias-disable; 419 }; 420 }; 421 }; 422 }; 423 424 cec_AO: cec@100 { 425 compatible = "amlogic,meson-gx-ao-cec"; 426 reg = <0x0 0x00100 0x0 0x14>; 427 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 428 clocks = <&clkc_AO CLKID_AO_CEC>; 429 clock-names = "core"; 430 status = "disabled"; 431 }; 432 433 sec_AO: ao-secure@140 { 434 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 435 reg = <0x0 0x140 0x0 0x140>; 436 amlogic,has-chip-id; 437 }; 438 439 cecb_AO: cec@280 { 440 compatible = "amlogic,meson-g12a-ao-cec"; 441 reg = <0x0 0x00280 0x0 0x1c>; 442 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 443 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 444 clock-names = "oscin"; 445 status = "disabled"; 446 }; 447 448 uart_AO: serial@3000 { 449 compatible = "amlogic,meson-gx-uart", 450 "amlogic,meson-ao-uart"; 451 reg = <0x0 0x3000 0x0 0x18>; 452 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 453 clocks = <&xtal>, <&xtal>, <&xtal>; 454 clock-names = "xtal", "pclk", "baud"; 455 status = "disabled"; 456 }; 457 458 uart_AO_B: serial@4000 { 459 compatible = "amlogic,meson-gx-uart", 460 "amlogic,meson-ao-uart"; 461 reg = <0x0 0x4000 0x0 0x18>; 462 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 463 clocks = <&xtal>, <&xtal>, <&xtal>; 464 clock-names = "xtal", "pclk", "baud"; 465 status = "disabled"; 466 }; 467 468 saradc: adc@9000 { 469 compatible = "amlogic,meson-g12a-saradc", 470 "amlogic,meson-saradc"; 471 reg = <0x0 0x9000 0x0 0x48>; 472 #io-channel-cells = <1>; 473 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 474 clocks = <&xtal>, 475 <&clkc_AO CLKID_AO_SAR_ADC>, 476 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 477 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 478 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 479 status = "disabled"; 480 }; 481 }; 482 483 vpu: vpu@ff900000 { 484 compatible = "amlogic,meson-g12a-vpu"; 485 reg = <0x0 0xff900000 0x0 0x100000>, 486 <0x0 0xff63c000 0x0 0x1000>; 487 reg-names = "vpu", "hhi"; 488 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 amlogic,canvas = <&canvas>; 492 power-domains = <&pwrc_vpu>; 493 494 /* CVBS VDAC output port */ 495 cvbs_vdac_port: port@0 { 496 reg = <0>; 497 }; 498 499 /* HDMI-TX output port */ 500 hdmi_tx_port: port@1 { 501 reg = <1>; 502 503 hdmi_tx_out: endpoint { 504 remote-endpoint = <&hdmi_tx_in>; 505 }; 506 }; 507 }; 508 509 gic: interrupt-controller@ffc01000 { 510 compatible = "arm,gic-400"; 511 reg = <0x0 0xffc01000 0 0x1000>, 512 <0x0 0xffc02000 0 0x2000>, 513 <0x0 0xffc04000 0 0x2000>, 514 <0x0 0xffc06000 0 0x2000>; 515 interrupt-controller; 516 interrupts = <GIC_PPI 9 517 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 518 #interrupt-cells = <3>; 519 #address-cells = <0>; 520 }; 521 522 cbus: bus@ffd00000 { 523 compatible = "simple-bus"; 524 reg = <0x0 0xffd00000 0x0 0x100000>; 525 #address-cells = <2>; 526 #size-cells = <2>; 527 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 528 529 reset: reset-controller@1004 { 530 compatible = "amlogic,meson-g12a-reset", 531 "amlogic,meson-axg-reset"; 532 reg = <0x0 0x1004 0x0 0x9c>; 533 #reset-cells = <1>; 534 }; 535 536 clk_msr: clock-measure@18000 { 537 compatible = "amlogic,meson-g12a-clk-measure"; 538 reg = <0x0 0x18000 0x0 0x10>; 539 }; 540 541 uart_C: serial@22000 { 542 compatible = "amlogic,meson-gx-uart"; 543 reg = <0x0 0x22000 0x0 0x18>; 544 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 545 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 546 clock-names = "xtal", "pclk", "baud"; 547 status = "disabled"; 548 }; 549 550 uart_B: serial@23000 { 551 compatible = "amlogic,meson-gx-uart"; 552 reg = <0x0 0x23000 0x0 0x18>; 553 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 554 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 555 clock-names = "xtal", "pclk", "baud"; 556 status = "disabled"; 557 }; 558 559 uart_A: serial@24000 { 560 compatible = "amlogic,meson-gx-uart"; 561 reg = <0x0 0x24000 0x0 0x18>; 562 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 563 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 564 clock-names = "xtal", "pclk", "baud"; 565 status = "disabled"; 566 }; 567 }; 568 569 usb: usb@ffe09000 { 570 status = "disabled"; 571 compatible = "amlogic,meson-g12a-usb-ctrl"; 572 reg = <0x0 0xffe09000 0x0 0xa0>; 573 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 574 #address-cells = <2>; 575 #size-cells = <2>; 576 ranges; 577 578 clocks = <&clkc CLKID_USB>; 579 resets = <&reset RESET_USB>; 580 581 dr_mode = "otg"; 582 583 phys = <&usb2_phy0>, <&usb2_phy1>, 584 <&usb3_pcie_phy PHY_TYPE_USB3>; 585 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 586 587 dwc2: usb@ff400000 { 588 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 589 reg = <0x0 0xff400000 0x0 0x40000>; 590 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 592 clock-names = "ddr"; 593 phys = <&usb2_phy1>; 594 dr_mode = "peripheral"; 595 g-rx-fifo-size = <192>; 596 g-np-tx-fifo-size = <128>; 597 g-tx-fifo-size = <128 128 16 16 16>; 598 }; 599 600 dwc3: usb@ff500000 { 601 compatible = "snps,dwc3"; 602 reg = <0x0 0xff500000 0x0 0x100000>; 603 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 604 dr_mode = "host"; 605 snps,dis_u2_susphy_quirk; 606 snps,quirk-frame-length-adjustment; 607 }; 608 }; 609 610 mali: gpu@ffe40000 { 611 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 612 reg = <0x0 0xffe40000 0x0 0x40000>; 613 interrupt-parent = <&gic>; 614 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 617 interrupt-names = "gpu", "mmu", "job"; 618 clocks = <&clkc CLKID_MALI>; 619 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 620 621 /* 622 * Mali clocking is provided by two identical clock paths 623 * MALI_0 and MALI_1 muxed to a single clock by a glitch 624 * free mux to safely change frequency while running. 625 */ 626 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 627 <&clkc CLKID_MALI_0>, 628 <&clkc CLKID_MALI>; /* Glitch free mux */ 629 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 630 <0>, /* Do Nothing */ 631 <&clkc CLKID_MALI_0>; 632 assigned-clock-rates = <0>, /* Do Nothing */ 633 <800000000>, 634 <0>; /* Do Nothing */ 635 }; 636 }; 637 638 timer { 639 compatible = "arm,armv8-timer"; 640 interrupts = <GIC_PPI 13 641 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 642 <GIC_PPI 14 643 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 644 <GIC_PPI 11 645 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 646 <GIC_PPI 10 647 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 648 }; 649 650 xtal: xtal-clk { 651 compatible = "fixed-clock"; 652 clock-frequency = <24000000>; 653 clock-output-names = "xtal"; 654 #clock-cells = <0>; 655 }; 656 657}; 658