1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/phy/phy.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/clock/g12a-clkc.h>
9#include <dt-bindings/clock/g12a-aoclkc.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
13
14/ {
15	compatible = "amlogic,g12a";
16
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	cpus {
22		#address-cells = <0x2>;
23		#size-cells = <0x0>;
24
25		cpu0: cpu@0 {
26			device_type = "cpu";
27			compatible = "arm,cortex-a53";
28			reg = <0x0 0x0>;
29			enable-method = "psci";
30			next-level-cache = <&l2>;
31		};
32
33		cpu1: cpu@1 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a53";
36			reg = <0x0 0x1>;
37			enable-method = "psci";
38			next-level-cache = <&l2>;
39		};
40
41		cpu2: cpu@2 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53";
44			reg = <0x0 0x2>;
45			enable-method = "psci";
46			next-level-cache = <&l2>;
47		};
48
49		cpu3: cpu@3 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a53";
52			reg = <0x0 0x3>;
53			enable-method = "psci";
54			next-level-cache = <&l2>;
55		};
56
57		l2: l2-cache0 {
58			compatible = "cache";
59		};
60	};
61
62	efuse: efuse {
63		compatible = "amlogic,meson-gxbb-efuse";
64		clocks = <&clkc CLKID_EFUSE>;
65		#address-cells = <1>;
66		#size-cells = <1>;
67		read-only;
68	};
69
70	psci {
71		compatible = "arm,psci-1.0";
72		method = "smc";
73	};
74
75	reserved-memory {
76		#address-cells = <2>;
77		#size-cells = <2>;
78		ranges;
79
80		/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
81		secmon_reserved: secmon@5000000 {
82			reg = <0x0 0x05000000 0x0 0x300000>;
83			no-map;
84		};
85
86		linux,cma {
87			compatible = "shared-dma-pool";
88			reusable;
89			size = <0x0 0x10000000>;
90			alignment = <0x0 0x400000>;
91			linux,cma-default;
92		};
93	};
94
95	sm: secure-monitor {
96		compatible = "amlogic,meson-gxbb-sm";
97	};
98
99	soc {
100		compatible = "simple-bus";
101		#address-cells = <2>;
102		#size-cells = <2>;
103		ranges;
104
105		apb: bus@ff600000 {
106			compatible = "simple-bus";
107			reg = <0x0 0xff600000 0x0 0x200000>;
108			#address-cells = <2>;
109			#size-cells = <2>;
110			ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
111
112			hdmi_tx: hdmi-tx@0 {
113				compatible = "amlogic,meson-g12a-dw-hdmi";
114				reg = <0x0 0x0 0x0 0x10000>;
115				interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
116				resets = <&reset RESET_HDMITX_CAPB3>,
117					 <&reset RESET_HDMITX_PHY>,
118					 <&reset RESET_HDMITX>;
119				reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
120				clocks = <&clkc CLKID_HDMI>,
121					 <&clkc CLKID_HTX_PCLK>,
122					 <&clkc CLKID_VPU_INTR>;
123				clock-names = "isfr", "iahb", "venci";
124				#address-cells = <1>;
125				#size-cells = <0>;
126				status = "disabled";
127
128				/* VPU VENC Input */
129				hdmi_tx_venc_port: port@0 {
130					reg = <0>;
131
132					hdmi_tx_in: endpoint {
133						remote-endpoint = <&hdmi_tx_out>;
134					};
135				};
136
137				/* TMDS Output */
138				hdmi_tx_tmds_port: port@1 {
139					reg = <1>;
140				};
141			};
142
143			periphs: bus@34400 {
144				compatible = "simple-bus";
145				reg = <0x0 0x34400 0x0 0x400>;
146				#address-cells = <2>;
147				#size-cells = <2>;
148				ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
149
150				periphs_pinctrl: pinctrl@40 {
151					compatible = "amlogic,meson-g12a-periphs-pinctrl";
152					#address-cells = <2>;
153					#size-cells = <2>;
154					ranges;
155
156					gpio: bank@40 {
157						reg = <0x0 0x40  0x0 0x4c>,
158						      <0x0 0xe8  0x0 0x18>,
159						      <0x0 0x120 0x0 0x18>,
160						      <0x0 0x2c0 0x0 0x40>,
161						      <0x0 0x340 0x0 0x1c>;
162						reg-names = "gpio",
163							    "pull",
164							    "pull-enable",
165							    "mux",
166							    "ds";
167						gpio-controller;
168						#gpio-cells = <2>;
169						gpio-ranges = <&periphs_pinctrl 0 0 86>;
170					};
171
172					hdmitx_ddc_pins: hdmitx_ddc {
173						mux {
174							groups = "hdmitx_sda",
175								 "hdmitx_sck";
176							function = "hdmitx";
177							bias-disable;
178						};
179					};
180
181					hdmitx_hpd_pins: hdmitx_hpd {
182						mux {
183							groups = "hdmitx_hpd_in";
184							function = "hdmitx";
185							bias-disable;
186						};
187					};
188
189					uart_a_pins: uart-a {
190						mux {
191							groups = "uart_a_tx",
192								 "uart_a_rx";
193							function = "uart_a";
194							bias-disable;
195						};
196					};
197
198					uart_a_cts_rts_pins: uart-a-cts-rts {
199						mux {
200							groups = "uart_a_cts",
201								 "uart_a_rts";
202							function = "uart_a";
203							bias-disable;
204						};
205					};
206
207					uart_b_pins: uart-b {
208						mux {
209							groups = "uart_b_tx",
210								 "uart_b_rx";
211							function = "uart_b";
212							bias-disable;
213						};
214					};
215
216					uart_c_pins: uart-c {
217						mux {
218							groups = "uart_c_tx",
219								 "uart_c_rx";
220							function = "uart_c";
221							bias-disable;
222						};
223					};
224
225					uart_c_cts_rts_pins: uart-c-cts-rts {
226						mux {
227							groups = "uart_c_cts",
228								 "uart_c_rts";
229							function = "uart_c";
230							bias-disable;
231						};
232					};
233				};
234			};
235
236			usb2_phy0: phy@36000 {
237				compatible = "amlogic,g12a-usb2-phy";
238				reg = <0x0 0x36000 0x0 0x2000>;
239				clocks = <&xtal>;
240				clock-names = "xtal";
241				resets = <&reset RESET_USB_PHY20>;
242				reset-names = "phy";
243				#phy-cells = <0>;
244			};
245
246			dmc: bus@38000 {
247				compatible = "simple-bus";
248				reg = <0x0 0x38000 0x0 0x400>;
249				#address-cells = <2>;
250				#size-cells = <2>;
251				ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
252
253				canvas: video-lut@48 {
254					compatible = "amlogic,canvas";
255					reg = <0x0 0x48 0x0 0x14>;
256				};
257			};
258
259			usb2_phy1: phy@3a000 {
260				compatible = "amlogic,g12a-usb2-phy";
261				reg = <0x0 0x3a000 0x0 0x2000>;
262				clocks = <&xtal>;
263				clock-names = "xtal";
264				resets = <&reset RESET_USB_PHY21>;
265				reset-names = "phy";
266				#phy-cells = <0>;
267			};
268
269			hiu: bus@3c000 {
270				compatible = "simple-bus";
271				reg = <0x0 0x3c000 0x0 0x1400>;
272				#address-cells = <2>;
273				#size-cells = <2>;
274				ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
275
276				hhi: system-controller@0 {
277					compatible = "amlogic,meson-gx-hhi-sysctrl",
278						     "simple-mfd", "syscon";
279					reg = <0 0 0 0x400>;
280
281					clkc: clock-controller {
282						compatible = "amlogic,g12a-clkc";
283						#clock-cells = <1>;
284						clocks = <&xtal>;
285						clock-names = "xtal";
286					};
287				};
288			};
289
290			usb3_pcie_phy: phy@46000 {
291				compatible = "amlogic,g12a-usb3-pcie-phy";
292				reg = <0x0 0x46000 0x0 0x2000>;
293				clocks = <&clkc CLKID_PCIE_PLL>;
294				clock-names = "ref_clk";
295				resets = <&reset RESET_PCIE_PHY>;
296				reset-names = "phy";
297				assigned-clocks = <&clkc CLKID_PCIE_PLL>;
298				assigned-clock-rates = <100000000>;
299				#phy-cells = <1>;
300			};
301		};
302
303		aobus: bus@ff800000 {
304			compatible = "simple-bus";
305			reg = <0x0 0xff800000 0x0 0x100000>;
306			#address-cells = <2>;
307			#size-cells = <2>;
308			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
309
310			rti: sys-ctrl@0 {
311				compatible = "amlogic,meson-gx-ao-sysctrl",
312					     "simple-mfd", "syscon";
313				reg = <0x0 0x0 0x0 0x100>;
314				#address-cells = <2>;
315				#size-cells = <2>;
316				ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
317
318				clkc_AO: clock-controller {
319					compatible = "amlogic,meson-g12a-aoclkc";
320					#clock-cells = <1>;
321					#reset-cells = <1>;
322					clocks = <&xtal>, <&clkc CLKID_CLK81>;
323					clock-names = "xtal", "mpeg-clk";
324				};
325
326				pwrc_vpu: power-controller-vpu {
327					compatible = "amlogic,meson-g12a-pwrc-vpu";
328					#power-domain-cells = <0>;
329					amlogic,hhi-sysctrl = <&hhi>;
330					resets = <&reset RESET_VIU>,
331						 <&reset RESET_VENC>,
332						 <&reset RESET_VCBUS>,
333						 <&reset RESET_BT656>,
334						 <&reset RESET_RDMA>,
335						 <&reset RESET_VENCI>,
336						 <&reset RESET_VENCP>,
337						 <&reset RESET_VDAC>,
338						 <&reset RESET_VDI6>,
339						 <&reset RESET_VENCL>,
340						 <&reset RESET_VID_LOCK>;
341					clocks = <&clkc CLKID_VPU>,
342						 <&clkc CLKID_VAPB>;
343					clock-names = "vpu", "vapb";
344					/*
345					 * VPU clocking is provided by two identical clock paths
346					 * VPU_0 and VPU_1 muxed to a single clock by a glitch
347					 * free mux to safely change frequency while running.
348					 * Same for VAPB but with a final gate after the glitch free mux.
349					 */
350					assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
351							  <&clkc CLKID_VPU_0>,
352							  <&clkc CLKID_VPU>, /* Glitch free mux */
353							  <&clkc CLKID_VAPB_0_SEL>,
354							  <&clkc CLKID_VAPB_0>,
355							  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
356					assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
357								 <0>, /* Do Nothing */
358								 <&clkc CLKID_VPU_0>,
359								 <&clkc CLKID_FCLK_DIV4>,
360								 <0>, /* Do Nothing */
361								 <&clkc CLKID_VAPB_0>;
362					assigned-clock-rates = <0>, /* Do Nothing */
363							       <666666666>,
364							       <0>, /* Do Nothing */
365							       <0>, /* Do Nothing */
366							       <250000000>,
367							       <0>; /* Do Nothing */
368				};
369
370				ao_pinctrl: pinctrl@14 {
371					compatible = "amlogic,meson-g12a-aobus-pinctrl";
372					#address-cells = <2>;
373					#size-cells = <2>;
374					ranges;
375
376					gpio_ao: bank@14 {
377						reg = <0x0 0x14 0x0 0x8>,
378						      <0x0 0x1c 0x0 0x8>,
379						      <0x0 0x24 0x0 0x14>;
380						reg-names = "mux",
381							    "ds",
382							    "gpio";
383						gpio-controller;
384						#gpio-cells = <2>;
385						gpio-ranges = <&ao_pinctrl 0 0 15>;
386					};
387
388					uart_ao_a_pins: uart-a-ao {
389						mux {
390							groups = "uart_ao_a_tx",
391								 "uart_ao_a_rx";
392							function = "uart_ao_a";
393							bias-disable;
394						};
395					};
396
397					uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
398						mux {
399							groups = "uart_ao_a_cts",
400								 "uart_ao_a_rts";
401							function = "uart_ao_a";
402							bias-disable;
403						};
404					};
405				};
406			};
407
408			sec_AO: ao-secure@140 {
409				compatible = "amlogic,meson-gx-ao-secure", "syscon";
410				reg = <0x0 0x140 0x0 0x140>;
411				amlogic,has-chip-id;
412			};
413
414			uart_AO: serial@3000 {
415				compatible = "amlogic,meson-gx-uart",
416					     "amlogic,meson-ao-uart";
417				reg = <0x0 0x3000 0x0 0x18>;
418				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
419				clocks = <&xtal>, <&xtal>, <&xtal>;
420				clock-names = "xtal", "pclk", "baud";
421				status = "disabled";
422			};
423
424			uart_AO_B: serial@4000 {
425				compatible = "amlogic,meson-gx-uart",
426					     "amlogic,meson-ao-uart";
427				reg = <0x0 0x4000 0x0 0x18>;
428				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
429				clocks = <&xtal>, <&xtal>, <&xtal>;
430				clock-names = "xtal", "pclk", "baud";
431				status = "disabled";
432			};
433
434			saradc: adc@9000 {
435				compatible = "amlogic,meson-g12a-saradc",
436					     "amlogic,meson-saradc";
437				reg = <0x0 0x9000 0x0 0x48>;
438				#io-channel-cells = <1>;
439				interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
440				clocks = <&xtal>,
441					 <&clkc_AO CLKID_AO_SAR_ADC>,
442					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
443					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
444				clock-names = "clkin", "core", "adc_clk", "adc_sel";
445				status = "disabled";
446			};
447		};
448
449		vpu: vpu@ff900000 {
450			compatible = "amlogic,meson-g12a-vpu";
451			reg = <0x0 0xff900000 0x0 0x100000>,
452			      <0x0 0xff63c000 0x0 0x1000>;
453			reg-names = "vpu", "hhi";
454			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
455			#address-cells = <1>;
456			#size-cells = <0>;
457			amlogic,canvas = <&canvas>;
458			power-domains = <&pwrc_vpu>;
459
460			/* CVBS VDAC output port */
461			cvbs_vdac_port: port@0 {
462				reg = <0>;
463			};
464
465			/* HDMI-TX output port */
466			hdmi_tx_port: port@1 {
467				reg = <1>;
468
469				hdmi_tx_out: endpoint {
470					remote-endpoint = <&hdmi_tx_in>;
471				};
472			};
473		};
474
475		gic: interrupt-controller@ffc01000 {
476			compatible = "arm,gic-400";
477			reg = <0x0 0xffc01000 0 0x1000>,
478			      <0x0 0xffc02000 0 0x2000>,
479			      <0x0 0xffc04000 0 0x2000>,
480			      <0x0 0xffc06000 0 0x2000>;
481			interrupt-controller;
482			interrupts = <GIC_PPI 9
483				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
484			#interrupt-cells = <3>;
485			#address-cells = <0>;
486		};
487
488		cbus: bus@ffd00000 {
489			compatible = "simple-bus";
490			reg = <0x0 0xffd00000 0x0 0x100000>;
491			#address-cells = <2>;
492			#size-cells = <2>;
493			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
494
495			reset: reset-controller@1004 {
496				compatible = "amlogic,meson-g12a-reset",
497					     "amlogic,meson-axg-reset";
498				reg = <0x0 0x1004 0x0 0x9c>;
499				#reset-cells = <1>;
500			};
501
502			clk_msr: clock-measure@18000 {
503				compatible = "amlogic,meson-g12a-clk-measure";
504				reg = <0x0 0x18000 0x0 0x10>;
505			};
506
507			uart_C: serial@22000 {
508				compatible = "amlogic,meson-gx-uart";
509				reg = <0x0 0x22000 0x0 0x18>;
510				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
511				clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
512				clock-names = "xtal", "pclk", "baud";
513				status = "disabled";
514			};
515
516			uart_B: serial@23000 {
517				compatible = "amlogic,meson-gx-uart";
518				reg = <0x0 0x23000 0x0 0x18>;
519				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
520				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
521				clock-names = "xtal", "pclk", "baud";
522				status = "disabled";
523			};
524
525			uart_A: serial@24000 {
526				compatible = "amlogic,meson-gx-uart";
527				reg = <0x0 0x24000 0x0 0x18>;
528				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
529				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
530				clock-names = "xtal", "pclk", "baud";
531				status = "disabled";
532			};
533		};
534
535		usb: usb@ffe09000 {
536			status = "disabled";
537			compatible = "amlogic,meson-g12a-usb-ctrl";
538			reg = <0x0 0xffe09000 0x0 0xa0>;
539			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
540			#address-cells = <2>;
541			#size-cells = <2>;
542			ranges;
543
544			clocks = <&clkc CLKID_USB>;
545			resets = <&reset RESET_USB>;
546
547			dr_mode = "otg";
548
549			phys = <&usb2_phy0>, <&usb2_phy1>,
550			       <&usb3_pcie_phy PHY_TYPE_USB3>;
551			phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
552
553			dwc2: usb@ff400000 {
554				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
555				reg = <0x0 0xff400000 0x0 0x40000>;
556				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
557				clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
558				clock-names = "ddr";
559				phys = <&usb2_phy1>;
560				dr_mode = "peripheral";
561				g-rx-fifo-size = <192>;
562				g-np-tx-fifo-size = <128>;
563				g-tx-fifo-size = <128 128 16 16 16>;
564			};
565
566			dwc3: usb@ff500000 {
567				compatible = "snps,dwc3";
568				reg = <0x0 0xff500000 0x0 0x100000>;
569				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
570				dr_mode = "host";
571				snps,dis_u2_susphy_quirk;
572				snps,quirk-frame-length-adjustment;
573			};
574		};
575
576		mali: gpu@ffe40000 {
577			compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
578			reg = <0x0 0xffe40000 0x0 0x40000>;
579			interrupt-parent = <&gic>;
580			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
581				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
582				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
583			interrupt-names = "gpu", "mmu", "job";
584			clocks = <&clkc CLKID_MALI>;
585			resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
586
587			/*
588			 * Mali clocking is provided by two identical clock paths
589			 * MALI_0 and MALI_1 muxed to a single clock by a glitch
590			 * free mux to safely change frequency while running.
591			 */
592			assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
593					  <&clkc CLKID_MALI_0>,
594					  <&clkc CLKID_MALI>; /* Glitch free mux */
595			assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
596						 <0>, /* Do Nothing */
597						 <&clkc CLKID_MALI_0>;
598			assigned-clock-rates = <0>, /* Do Nothing */
599					       <800000000>,
600					       <0>; /* Do Nothing */
601		};
602	};
603
604	timer {
605		compatible = "arm,armv8-timer";
606		interrupts = <GIC_PPI 13
607			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
608			     <GIC_PPI 14
609			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
610			     <GIC_PPI 11
611			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
612			     <GIC_PPI 10
613			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
614	};
615
616	xtal: xtal-clk {
617		compatible = "fixed-clock";
618		clock-frequency = <24000000>;
619		clock-output-names = "xtal";
620		#clock-cells = <0>;
621	};
622
623};
624