xref: /openbmc/linux/arch/arm/net/bpf_jit_32.c (revision fc386ba7)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Just-In-Time compiler for eBPF filters on 32bit ARM
4  *
5  * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com>
6  * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>
7  */
8 
9 #include <linux/bpf.h>
10 #include <linux/bitops.h>
11 #include <linux/compiler.h>
12 #include <linux/errno.h>
13 #include <linux/filter.h>
14 #include <linux/netdevice.h>
15 #include <linux/string.h>
16 #include <linux/slab.h>
17 #include <linux/if_vlan.h>
18 
19 #include <asm/cacheflush.h>
20 #include <asm/hwcap.h>
21 #include <asm/opcodes.h>
22 #include <asm/system_info.h>
23 
24 #include "bpf_jit_32.h"
25 
26 /*
27  * eBPF prog stack layout:
28  *
29  *                         high
30  * original ARM_SP =>     +-----+
31  *                        |     | callee saved registers
32  *                        +-----+ <= (BPF_FP + SCRATCH_SIZE)
33  *                        | ... | eBPF JIT scratch space
34  * eBPF fp register =>    +-----+
35  *   (BPF_FP)             | ... | eBPF prog stack
36  *                        +-----+
37  *                        |RSVD | JIT scratchpad
38  * current ARM_SP =>      +-----+ <= (BPF_FP - STACK_SIZE + SCRATCH_SIZE)
39  *                        | ... | caller-saved registers
40  *                        +-----+
41  *                        | ... | arguments passed on stack
42  * ARM_SP during call =>  +-----|
43  *                        |     |
44  *                        | ... | Function call stack
45  *                        |     |
46  *                        +-----+
47  *                          low
48  *
49  * The callee saved registers depends on whether frame pointers are enabled.
50  * With frame pointers (to be compliant with the ABI):
51  *
52  *                              high
53  * original ARM_SP =>     +--------------+ \
54  *                        |      pc      | |
55  * current ARM_FP =>      +--------------+ } callee saved registers
56  *                        |r4-r9,fp,ip,lr| |
57  *                        +--------------+ /
58  *                              low
59  *
60  * Without frame pointers:
61  *
62  *                              high
63  * original ARM_SP =>     +--------------+
64  *                        |  r4-r9,fp,lr | callee saved registers
65  * current ARM_FP =>      +--------------+
66  *                              low
67  *
68  * When popping registers off the stack at the end of a BPF function, we
69  * reference them via the current ARM_FP register.
70  *
71  * Some eBPF operations are implemented via a call to a helper function.
72  * Such calls are "invisible" in the eBPF code, so it is up to the calling
73  * program to preserve any caller-saved ARM registers during the call. The
74  * JIT emits code to push and pop those registers onto the stack, immediately
75  * above the callee stack frame.
76  */
77 #define CALLEE_MASK	(1 << ARM_R4 | 1 << ARM_R5 | 1 << ARM_R6 | \
78 			 1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R9 | \
79 			 1 << ARM_FP)
80 #define CALLEE_PUSH_MASK (CALLEE_MASK | 1 << ARM_LR)
81 #define CALLEE_POP_MASK  (CALLEE_MASK | 1 << ARM_PC)
82 
83 #define CALLER_MASK	(1 << ARM_R0 | 1 << ARM_R1 | 1 << ARM_R2 | 1 << ARM_R3)
84 
85 enum {
86 	/* Stack layout - these are offsets from (top of stack - 4) */
87 	BPF_R2_HI,
88 	BPF_R2_LO,
89 	BPF_R3_HI,
90 	BPF_R3_LO,
91 	BPF_R4_HI,
92 	BPF_R4_LO,
93 	BPF_R5_HI,
94 	BPF_R5_LO,
95 	BPF_R7_HI,
96 	BPF_R7_LO,
97 	BPF_R8_HI,
98 	BPF_R8_LO,
99 	BPF_R9_HI,
100 	BPF_R9_LO,
101 	BPF_FP_HI,
102 	BPF_FP_LO,
103 	BPF_TC_HI,
104 	BPF_TC_LO,
105 	BPF_AX_HI,
106 	BPF_AX_LO,
107 	/* Stack space for BPF_REG_2, BPF_REG_3, BPF_REG_4,
108 	 * BPF_REG_5, BPF_REG_7, BPF_REG_8, BPF_REG_9,
109 	 * BPF_REG_FP and Tail call counts.
110 	 */
111 	BPF_JIT_SCRATCH_REGS,
112 };
113 
114 /*
115  * Negative "register" values indicate the register is stored on the stack
116  * and are the offset from the top of the eBPF JIT scratch space.
117  */
118 #define STACK_OFFSET(k)	(-4 - (k) * 4)
119 #define SCRATCH_SIZE	(BPF_JIT_SCRATCH_REGS * 4)
120 
121 #ifdef CONFIG_FRAME_POINTER
122 #define EBPF_SCRATCH_TO_ARM_FP(x) ((x) - 4 * hweight16(CALLEE_PUSH_MASK) - 4)
123 #else
124 #define EBPF_SCRATCH_TO_ARM_FP(x) (x)
125 #endif
126 
127 #define TMP_REG_1	(MAX_BPF_JIT_REG + 0)	/* TEMP Register 1 */
128 #define TMP_REG_2	(MAX_BPF_JIT_REG + 1)	/* TEMP Register 2 */
129 #define TCALL_CNT	(MAX_BPF_JIT_REG + 2)	/* Tail Call Count */
130 
131 #define FLAG_IMM_OVERFLOW	(1 << 0)
132 
133 /*
134  * Map eBPF registers to ARM 32bit registers or stack scratch space.
135  *
136  * 1. First argument is passed using the arm 32bit registers and rest of the
137  * arguments are passed on stack scratch space.
138  * 2. First callee-saved argument is mapped to arm 32 bit registers and rest
139  * arguments are mapped to scratch space on stack.
140  * 3. We need two 64 bit temp registers to do complex operations on eBPF
141  * registers.
142  *
143  * As the eBPF registers are all 64 bit registers and arm has only 32 bit
144  * registers, we have to map each eBPF registers with two arm 32 bit regs or
145  * scratch memory space and we have to build eBPF 64 bit register from those.
146  *
147  */
148 static const s8 bpf2a32[][2] = {
149 	/* return value from in-kernel function, and exit value from eBPF */
150 	[BPF_REG_0] = {ARM_R1, ARM_R0},
151 	/* arguments from eBPF program to in-kernel function */
152 	[BPF_REG_1] = {ARM_R3, ARM_R2},
153 	/* Stored on stack scratch space */
154 	[BPF_REG_2] = {STACK_OFFSET(BPF_R2_HI), STACK_OFFSET(BPF_R2_LO)},
155 	[BPF_REG_3] = {STACK_OFFSET(BPF_R3_HI), STACK_OFFSET(BPF_R3_LO)},
156 	[BPF_REG_4] = {STACK_OFFSET(BPF_R4_HI), STACK_OFFSET(BPF_R4_LO)},
157 	[BPF_REG_5] = {STACK_OFFSET(BPF_R5_HI), STACK_OFFSET(BPF_R5_LO)},
158 	/* callee saved registers that in-kernel function will preserve */
159 	[BPF_REG_6] = {ARM_R5, ARM_R4},
160 	/* Stored on stack scratch space */
161 	[BPF_REG_7] = {STACK_OFFSET(BPF_R7_HI), STACK_OFFSET(BPF_R7_LO)},
162 	[BPF_REG_8] = {STACK_OFFSET(BPF_R8_HI), STACK_OFFSET(BPF_R8_LO)},
163 	[BPF_REG_9] = {STACK_OFFSET(BPF_R9_HI), STACK_OFFSET(BPF_R9_LO)},
164 	/* Read only Frame Pointer to access Stack */
165 	[BPF_REG_FP] = {STACK_OFFSET(BPF_FP_HI), STACK_OFFSET(BPF_FP_LO)},
166 	/* Temporary Register for BPF JIT, can be used
167 	 * for constant blindings and others.
168 	 */
169 	[TMP_REG_1] = {ARM_R7, ARM_R6},
170 	[TMP_REG_2] = {ARM_R9, ARM_R8},
171 	/* Tail call count. Stored on stack scratch space. */
172 	[TCALL_CNT] = {STACK_OFFSET(BPF_TC_HI), STACK_OFFSET(BPF_TC_LO)},
173 	/* temporary register for blinding constants.
174 	 * Stored on stack scratch space.
175 	 */
176 	[BPF_REG_AX] = {STACK_OFFSET(BPF_AX_HI), STACK_OFFSET(BPF_AX_LO)},
177 };
178 
179 #define	dst_lo	dst[1]
180 #define dst_hi	dst[0]
181 #define src_lo	src[1]
182 #define src_hi	src[0]
183 
184 /*
185  * JIT Context:
186  *
187  * prog			:	bpf_prog
188  * idx			:	index of current last JITed instruction.
189  * prologue_bytes	:	bytes used in prologue.
190  * epilogue_offset	:	offset of epilogue starting.
191  * offsets		:	array of eBPF instruction offsets in
192  *				JITed code.
193  * target		:	final JITed code.
194  * epilogue_bytes	:	no of bytes used in epilogue.
195  * imm_count		:	no of immediate counts used for global
196  *				variables.
197  * imms			:	array of global variable addresses.
198  */
199 
200 struct jit_ctx {
201 	const struct bpf_prog *prog;
202 	unsigned int idx;
203 	unsigned int prologue_bytes;
204 	unsigned int epilogue_offset;
205 	unsigned int cpu_architecture;
206 	u32 flags;
207 	u32 *offsets;
208 	u32 *target;
209 	u32 stack_size;
210 #if __LINUX_ARM_ARCH__ < 7
211 	u16 epilogue_bytes;
212 	u16 imm_count;
213 	u32 *imms;
214 #endif
215 };
216 
217 /*
218  * Wrappers which handle both OABI and EABI and assures Thumb2 interworking
219  * (where the assembly routines like __aeabi_uidiv could cause problems).
220  */
jit_udiv32(u32 dividend,u32 divisor)221 static u32 jit_udiv32(u32 dividend, u32 divisor)
222 {
223 	return dividend / divisor;
224 }
225 
jit_mod32(u32 dividend,u32 divisor)226 static u32 jit_mod32(u32 dividend, u32 divisor)
227 {
228 	return dividend % divisor;
229 }
230 
_emit(int cond,u32 inst,struct jit_ctx * ctx)231 static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx)
232 {
233 	inst |= (cond << 28);
234 	inst = __opcode_to_mem_arm(inst);
235 
236 	if (ctx->target != NULL)
237 		ctx->target[ctx->idx] = inst;
238 
239 	ctx->idx++;
240 }
241 
242 /*
243  * Emit an instruction that will be executed unconditionally.
244  */
emit(u32 inst,struct jit_ctx * ctx)245 static inline void emit(u32 inst, struct jit_ctx *ctx)
246 {
247 	_emit(ARM_COND_AL, inst, ctx);
248 }
249 
250 /*
251  * This is rather horrid, but necessary to convert an integer constant
252  * to an immediate operand for the opcodes, and be able to detect at
253  * build time whether the constant can't be converted (iow, usable in
254  * BUILD_BUG_ON()).
255  */
256 #define imm12val(v, s) (rol32(v, (s)) | (s) << 7)
257 #define const_imm8m(x)					\
258 	({ int r;					\
259 	   u32 v = (x);					\
260 	   if (!(v & ~0x000000ff))			\
261 		r = imm12val(v, 0);			\
262 	   else if (!(v & ~0xc000003f))			\
263 		r = imm12val(v, 2);			\
264 	   else if (!(v & ~0xf000000f))			\
265 		r = imm12val(v, 4);			\
266 	   else if (!(v & ~0xfc000003))			\
267 		r = imm12val(v, 6);			\
268 	   else if (!(v & ~0xff000000))			\
269 		r = imm12val(v, 8);			\
270 	   else if (!(v & ~0x3fc00000))			\
271 		r = imm12val(v, 10);			\
272 	   else if (!(v & ~0x0ff00000))			\
273 		r = imm12val(v, 12);			\
274 	   else if (!(v & ~0x03fc0000))			\
275 		r = imm12val(v, 14);			\
276 	   else if (!(v & ~0x00ff0000))			\
277 		r = imm12val(v, 16);			\
278 	   else if (!(v & ~0x003fc000))			\
279 		r = imm12val(v, 18);			\
280 	   else if (!(v & ~0x000ff000))			\
281 		r = imm12val(v, 20);			\
282 	   else if (!(v & ~0x0003fc00))			\
283 		r = imm12val(v, 22);			\
284 	   else if (!(v & ~0x0000ff00))			\
285 		r = imm12val(v, 24);			\
286 	   else if (!(v & ~0x00003fc0))			\
287 		r = imm12val(v, 26);			\
288 	   else if (!(v & ~0x00000ff0))			\
289 		r = imm12val(v, 28);			\
290 	   else if (!(v & ~0x000003fc))			\
291 		r = imm12val(v, 30);			\
292 	   else						\
293 		r = -1;					\
294 	   r; })
295 
296 /*
297  * Checks if immediate value can be converted to imm12(12 bits) value.
298  */
imm8m(u32 x)299 static int imm8m(u32 x)
300 {
301 	u32 rot;
302 
303 	for (rot = 0; rot < 16; rot++)
304 		if ((x & ~ror32(0xff, 2 * rot)) == 0)
305 			return rol32(x, 2 * rot) | (rot << 8);
306 	return -1;
307 }
308 
309 #define imm8m(x) (__builtin_constant_p(x) ? const_imm8m(x) : imm8m(x))
310 
arm_bpf_ldst_imm12(u32 op,u8 rt,u8 rn,s16 imm12)311 static u32 arm_bpf_ldst_imm12(u32 op, u8 rt, u8 rn, s16 imm12)
312 {
313 	op |= rt << 12 | rn << 16;
314 	if (imm12 >= 0)
315 		op |= ARM_INST_LDST__U;
316 	else
317 		imm12 = -imm12;
318 	return op | (imm12 & ARM_INST_LDST__IMM12);
319 }
320 
arm_bpf_ldst_imm8(u32 op,u8 rt,u8 rn,s16 imm8)321 static u32 arm_bpf_ldst_imm8(u32 op, u8 rt, u8 rn, s16 imm8)
322 {
323 	op |= rt << 12 | rn << 16;
324 	if (imm8 >= 0)
325 		op |= ARM_INST_LDST__U;
326 	else
327 		imm8 = -imm8;
328 	return op | (imm8 & 0xf0) << 4 | (imm8 & 0x0f);
329 }
330 
331 #define ARM_LDR_I(rt, rn, off)	arm_bpf_ldst_imm12(ARM_INST_LDR_I, rt, rn, off)
332 #define ARM_LDRB_I(rt, rn, off)	arm_bpf_ldst_imm12(ARM_INST_LDRB_I, rt, rn, off)
333 #define ARM_LDRD_I(rt, rn, off)	arm_bpf_ldst_imm8(ARM_INST_LDRD_I, rt, rn, off)
334 #define ARM_LDRH_I(rt, rn, off)	arm_bpf_ldst_imm8(ARM_INST_LDRH_I, rt, rn, off)
335 
336 #define ARM_STR_I(rt, rn, off)	arm_bpf_ldst_imm12(ARM_INST_STR_I, rt, rn, off)
337 #define ARM_STRB_I(rt, rn, off)	arm_bpf_ldst_imm12(ARM_INST_STRB_I, rt, rn, off)
338 #define ARM_STRD_I(rt, rn, off)	arm_bpf_ldst_imm8(ARM_INST_STRD_I, rt, rn, off)
339 #define ARM_STRH_I(rt, rn, off)	arm_bpf_ldst_imm8(ARM_INST_STRH_I, rt, rn, off)
340 
341 /*
342  * Initializes the JIT space with undefined instructions.
343  */
jit_fill_hole(void * area,unsigned int size)344 static void jit_fill_hole(void *area, unsigned int size)
345 {
346 	u32 *ptr;
347 	/* We are guaranteed to have aligned memory. */
348 	for (ptr = area; size >= sizeof(u32); size -= sizeof(u32))
349 		*ptr++ = __opcode_to_mem_arm(ARM_INST_UDF);
350 }
351 
352 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
353 /* EABI requires the stack to be aligned to 64-bit boundaries */
354 #define STACK_ALIGNMENT	8
355 #else
356 /* Stack must be aligned to 32-bit boundaries */
357 #define STACK_ALIGNMENT	4
358 #endif
359 
360 /* total stack size used in JITed code */
361 #define _STACK_SIZE	(ctx->prog->aux->stack_depth + SCRATCH_SIZE)
362 #define STACK_SIZE	ALIGN(_STACK_SIZE, STACK_ALIGNMENT)
363 
364 #if __LINUX_ARM_ARCH__ < 7
365 
imm_offset(u32 k,struct jit_ctx * ctx)366 static u16 imm_offset(u32 k, struct jit_ctx *ctx)
367 {
368 	unsigned int i = 0, offset;
369 	u16 imm;
370 
371 	/* on the "fake" run we just count them (duplicates included) */
372 	if (ctx->target == NULL) {
373 		ctx->imm_count++;
374 		return 0;
375 	}
376 
377 	while ((i < ctx->imm_count) && ctx->imms[i]) {
378 		if (ctx->imms[i] == k)
379 			break;
380 		i++;
381 	}
382 
383 	if (ctx->imms[i] == 0)
384 		ctx->imms[i] = k;
385 
386 	/* constants go just after the epilogue */
387 	offset =  ctx->offsets[ctx->prog->len - 1] * 4;
388 	offset += ctx->prologue_bytes;
389 	offset += ctx->epilogue_bytes;
390 	offset += i * 4;
391 
392 	ctx->target[offset / 4] = k;
393 
394 	/* PC in ARM mode == address of the instruction + 8 */
395 	imm = offset - (8 + ctx->idx * 4);
396 
397 	if (imm & ~0xfff) {
398 		/*
399 		 * literal pool is too far, signal it into flags. we
400 		 * can only detect it on the second pass unfortunately.
401 		 */
402 		ctx->flags |= FLAG_IMM_OVERFLOW;
403 		return 0;
404 	}
405 
406 	return imm;
407 }
408 
409 #endif /* __LINUX_ARM_ARCH__ */
410 
bpf2a32_offset(int bpf_to,int bpf_from,const struct jit_ctx * ctx)411 static inline int bpf2a32_offset(int bpf_to, int bpf_from,
412 				 const struct jit_ctx *ctx) {
413 	int to, from;
414 
415 	if (ctx->target == NULL)
416 		return 0;
417 	to = ctx->offsets[bpf_to];
418 	from = ctx->offsets[bpf_from];
419 
420 	return to - from - 1;
421 }
422 
423 /*
424  * Move an immediate that's not an imm8m to a core register.
425  */
emit_mov_i_no8m(const u8 rd,u32 val,struct jit_ctx * ctx)426 static inline void emit_mov_i_no8m(const u8 rd, u32 val, struct jit_ctx *ctx)
427 {
428 #if __LINUX_ARM_ARCH__ < 7
429 	emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx);
430 #else
431 	emit(ARM_MOVW(rd, val & 0xffff), ctx);
432 	if (val > 0xffff)
433 		emit(ARM_MOVT(rd, val >> 16), ctx);
434 #endif
435 }
436 
emit_mov_i(const u8 rd,u32 val,struct jit_ctx * ctx)437 static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx)
438 {
439 	int imm12 = imm8m(val);
440 
441 	if (imm12 >= 0)
442 		emit(ARM_MOV_I(rd, imm12), ctx);
443 	else
444 		emit_mov_i_no8m(rd, val, ctx);
445 }
446 
emit_bx_r(u8 tgt_reg,struct jit_ctx * ctx)447 static void emit_bx_r(u8 tgt_reg, struct jit_ctx *ctx)
448 {
449 	if (elf_hwcap & HWCAP_THUMB)
450 		emit(ARM_BX(tgt_reg), ctx);
451 	else
452 		emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx);
453 }
454 
emit_blx_r(u8 tgt_reg,struct jit_ctx * ctx)455 static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx)
456 {
457 #if __LINUX_ARM_ARCH__ < 5
458 	emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx);
459 	emit_bx_r(tgt_reg, ctx);
460 #else
461 	emit(ARM_BLX_R(tgt_reg), ctx);
462 #endif
463 }
464 
epilogue_offset(const struct jit_ctx * ctx)465 static inline int epilogue_offset(const struct jit_ctx *ctx)
466 {
467 	int to, from;
468 	/* No need for 1st dummy run */
469 	if (ctx->target == NULL)
470 		return 0;
471 	to = ctx->epilogue_offset;
472 	from = ctx->idx;
473 
474 	return to - from - 2;
475 }
476 
emit_udivmod(u8 rd,u8 rm,u8 rn,struct jit_ctx * ctx,u8 op)477 static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op)
478 {
479 	const int exclude_mask = BIT(ARM_R0) | BIT(ARM_R1);
480 	const s8 *tmp = bpf2a32[TMP_REG_1];
481 
482 #if __LINUX_ARM_ARCH__ == 7
483 	if (elf_hwcap & HWCAP_IDIVA) {
484 		if (op == BPF_DIV)
485 			emit(ARM_UDIV(rd, rm, rn), ctx);
486 		else {
487 			emit(ARM_UDIV(ARM_IP, rm, rn), ctx);
488 			emit(ARM_MLS(rd, rn, ARM_IP, rm), ctx);
489 		}
490 		return;
491 	}
492 #endif
493 
494 	/*
495 	 * For BPF_ALU | BPF_DIV | BPF_K instructions
496 	 * As ARM_R1 and ARM_R0 contains 1st argument of bpf
497 	 * function, we need to save it on caller side to save
498 	 * it from getting destroyed within callee.
499 	 * After the return from the callee, we restore ARM_R0
500 	 * ARM_R1.
501 	 */
502 	if (rn != ARM_R1) {
503 		emit(ARM_MOV_R(tmp[0], ARM_R1), ctx);
504 		emit(ARM_MOV_R(ARM_R1, rn), ctx);
505 	}
506 	if (rm != ARM_R0) {
507 		emit(ARM_MOV_R(tmp[1], ARM_R0), ctx);
508 		emit(ARM_MOV_R(ARM_R0, rm), ctx);
509 	}
510 
511 	/* Push caller-saved registers on stack */
512 	emit(ARM_PUSH(CALLER_MASK & ~exclude_mask), ctx);
513 
514 	/* Call appropriate function */
515 	emit_mov_i(ARM_IP, op == BPF_DIV ?
516 		   (u32)jit_udiv32 : (u32)jit_mod32, ctx);
517 	emit_blx_r(ARM_IP, ctx);
518 
519 	/* Restore caller-saved registers from stack */
520 	emit(ARM_POP(CALLER_MASK & ~exclude_mask), ctx);
521 
522 	/* Save return value */
523 	if (rd != ARM_R0)
524 		emit(ARM_MOV_R(rd, ARM_R0), ctx);
525 
526 	/* Restore ARM_R0 and ARM_R1 */
527 	if (rn != ARM_R1)
528 		emit(ARM_MOV_R(ARM_R1, tmp[0]), ctx);
529 	if (rm != ARM_R0)
530 		emit(ARM_MOV_R(ARM_R0, tmp[1]), ctx);
531 }
532 
533 /* Is the translated BPF register on stack? */
is_stacked(s8 reg)534 static bool is_stacked(s8 reg)
535 {
536 	return reg < 0;
537 }
538 
539 /* If a BPF register is on the stack (stk is true), load it to the
540  * supplied temporary register and return the temporary register
541  * for subsequent operations, otherwise just use the CPU register.
542  */
arm_bpf_get_reg32(s8 reg,s8 tmp,struct jit_ctx * ctx)543 static s8 arm_bpf_get_reg32(s8 reg, s8 tmp, struct jit_ctx *ctx)
544 {
545 	if (is_stacked(reg)) {
546 		emit(ARM_LDR_I(tmp, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(reg)), ctx);
547 		reg = tmp;
548 	}
549 	return reg;
550 }
551 
arm_bpf_get_reg64(const s8 * reg,const s8 * tmp,struct jit_ctx * ctx)552 static const s8 *arm_bpf_get_reg64(const s8 *reg, const s8 *tmp,
553 				   struct jit_ctx *ctx)
554 {
555 	if (is_stacked(reg[1])) {
556 		if (__LINUX_ARM_ARCH__ >= 6 ||
557 		    ctx->cpu_architecture >= CPU_ARCH_ARMv5TE) {
558 			emit(ARM_LDRD_I(tmp[1], ARM_FP,
559 					EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
560 		} else {
561 			emit(ARM_LDR_I(tmp[1], ARM_FP,
562 				       EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
563 			emit(ARM_LDR_I(tmp[0], ARM_FP,
564 				       EBPF_SCRATCH_TO_ARM_FP(reg[0])), ctx);
565 		}
566 		reg = tmp;
567 	}
568 	return reg;
569 }
570 
571 /* If a BPF register is on the stack (stk is true), save the register
572  * back to the stack.  If the source register is not the same, then
573  * move it into the correct register.
574  */
arm_bpf_put_reg32(s8 reg,s8 src,struct jit_ctx * ctx)575 static void arm_bpf_put_reg32(s8 reg, s8 src, struct jit_ctx *ctx)
576 {
577 	if (is_stacked(reg))
578 		emit(ARM_STR_I(src, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(reg)), ctx);
579 	else if (reg != src)
580 		emit(ARM_MOV_R(reg, src), ctx);
581 }
582 
arm_bpf_put_reg64(const s8 * reg,const s8 * src,struct jit_ctx * ctx)583 static void arm_bpf_put_reg64(const s8 *reg, const s8 *src,
584 			      struct jit_ctx *ctx)
585 {
586 	if (is_stacked(reg[1])) {
587 		if (__LINUX_ARM_ARCH__ >= 6 ||
588 		    ctx->cpu_architecture >= CPU_ARCH_ARMv5TE) {
589 			emit(ARM_STRD_I(src[1], ARM_FP,
590 				       EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
591 		} else {
592 			emit(ARM_STR_I(src[1], ARM_FP,
593 				       EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
594 			emit(ARM_STR_I(src[0], ARM_FP,
595 				       EBPF_SCRATCH_TO_ARM_FP(reg[0])), ctx);
596 		}
597 	} else {
598 		if (reg[1] != src[1])
599 			emit(ARM_MOV_R(reg[1], src[1]), ctx);
600 		if (reg[0] != src[0])
601 			emit(ARM_MOV_R(reg[0], src[0]), ctx);
602 	}
603 }
604 
emit_a32_mov_i(const s8 dst,const u32 val,struct jit_ctx * ctx)605 static inline void emit_a32_mov_i(const s8 dst, const u32 val,
606 				  struct jit_ctx *ctx)
607 {
608 	const s8 *tmp = bpf2a32[TMP_REG_1];
609 
610 	if (is_stacked(dst)) {
611 		emit_mov_i(tmp[1], val, ctx);
612 		arm_bpf_put_reg32(dst, tmp[1], ctx);
613 	} else {
614 		emit_mov_i(dst, val, ctx);
615 	}
616 }
617 
emit_a32_mov_i64(const s8 dst[],u64 val,struct jit_ctx * ctx)618 static void emit_a32_mov_i64(const s8 dst[], u64 val, struct jit_ctx *ctx)
619 {
620 	const s8 *tmp = bpf2a32[TMP_REG_1];
621 	const s8 *rd = is_stacked(dst_lo) ? tmp : dst;
622 
623 	emit_mov_i(rd[1], (u32)val, ctx);
624 	emit_mov_i(rd[0], val >> 32, ctx);
625 
626 	arm_bpf_put_reg64(dst, rd, ctx);
627 }
628 
629 /* Sign extended move */
emit_a32_mov_se_i64(const bool is64,const s8 dst[],const u32 val,struct jit_ctx * ctx)630 static inline void emit_a32_mov_se_i64(const bool is64, const s8 dst[],
631 				       const u32 val, struct jit_ctx *ctx) {
632 	u64 val64 = val;
633 
634 	if (is64 && (val & (1<<31)))
635 		val64 |= 0xffffffff00000000ULL;
636 	emit_a32_mov_i64(dst, val64, ctx);
637 }
638 
emit_a32_add_r(const u8 dst,const u8 src,const bool is64,const bool hi,struct jit_ctx * ctx)639 static inline void emit_a32_add_r(const u8 dst, const u8 src,
640 			      const bool is64, const bool hi,
641 			      struct jit_ctx *ctx) {
642 	/* 64 bit :
643 	 *	adds dst_lo, dst_lo, src_lo
644 	 *	adc dst_hi, dst_hi, src_hi
645 	 * 32 bit :
646 	 *	add dst_lo, dst_lo, src_lo
647 	 */
648 	if (!hi && is64)
649 		emit(ARM_ADDS_R(dst, dst, src), ctx);
650 	else if (hi && is64)
651 		emit(ARM_ADC_R(dst, dst, src), ctx);
652 	else
653 		emit(ARM_ADD_R(dst, dst, src), ctx);
654 }
655 
emit_a32_sub_r(const u8 dst,const u8 src,const bool is64,const bool hi,struct jit_ctx * ctx)656 static inline void emit_a32_sub_r(const u8 dst, const u8 src,
657 				  const bool is64, const bool hi,
658 				  struct jit_ctx *ctx) {
659 	/* 64 bit :
660 	 *	subs dst_lo, dst_lo, src_lo
661 	 *	sbc dst_hi, dst_hi, src_hi
662 	 * 32 bit :
663 	 *	sub dst_lo, dst_lo, src_lo
664 	 */
665 	if (!hi && is64)
666 		emit(ARM_SUBS_R(dst, dst, src), ctx);
667 	else if (hi && is64)
668 		emit(ARM_SBC_R(dst, dst, src), ctx);
669 	else
670 		emit(ARM_SUB_R(dst, dst, src), ctx);
671 }
672 
emit_alu_r(const u8 dst,const u8 src,const bool is64,const bool hi,const u8 op,struct jit_ctx * ctx)673 static inline void emit_alu_r(const u8 dst, const u8 src, const bool is64,
674 			      const bool hi, const u8 op, struct jit_ctx *ctx){
675 	switch (BPF_OP(op)) {
676 	/* dst = dst + src */
677 	case BPF_ADD:
678 		emit_a32_add_r(dst, src, is64, hi, ctx);
679 		break;
680 	/* dst = dst - src */
681 	case BPF_SUB:
682 		emit_a32_sub_r(dst, src, is64, hi, ctx);
683 		break;
684 	/* dst = dst | src */
685 	case BPF_OR:
686 		emit(ARM_ORR_R(dst, dst, src), ctx);
687 		break;
688 	/* dst = dst & src */
689 	case BPF_AND:
690 		emit(ARM_AND_R(dst, dst, src), ctx);
691 		break;
692 	/* dst = dst ^ src */
693 	case BPF_XOR:
694 		emit(ARM_EOR_R(dst, dst, src), ctx);
695 		break;
696 	/* dst = dst * src */
697 	case BPF_MUL:
698 		emit(ARM_MUL(dst, dst, src), ctx);
699 		break;
700 	/* dst = dst << src */
701 	case BPF_LSH:
702 		emit(ARM_LSL_R(dst, dst, src), ctx);
703 		break;
704 	/* dst = dst >> src */
705 	case BPF_RSH:
706 		emit(ARM_LSR_R(dst, dst, src), ctx);
707 		break;
708 	/* dst = dst >> src (signed)*/
709 	case BPF_ARSH:
710 		emit(ARM_MOV_SR(dst, dst, SRTYPE_ASR, src), ctx);
711 		break;
712 	}
713 }
714 
715 /* ALU operation (64 bit) */
emit_a32_alu_r64(const bool is64,const s8 dst[],const s8 src[],struct jit_ctx * ctx,const u8 op)716 static inline void emit_a32_alu_r64(const bool is64, const s8 dst[],
717 				  const s8 src[], struct jit_ctx *ctx,
718 				  const u8 op) {
719 	const s8 *tmp = bpf2a32[TMP_REG_1];
720 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
721 	const s8 *rd;
722 
723 	rd = arm_bpf_get_reg64(dst, tmp, ctx);
724 	if (is64) {
725 		const s8 *rs;
726 
727 		rs = arm_bpf_get_reg64(src, tmp2, ctx);
728 
729 		/* ALU operation */
730 		emit_alu_r(rd[1], rs[1], true, false, op, ctx);
731 		emit_alu_r(rd[0], rs[0], true, true, op, ctx);
732 	} else {
733 		s8 rs;
734 
735 		rs = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
736 
737 		/* ALU operation */
738 		emit_alu_r(rd[1], rs, true, false, op, ctx);
739 		if (!ctx->prog->aux->verifier_zext)
740 			emit_a32_mov_i(rd[0], 0, ctx);
741 	}
742 
743 	arm_bpf_put_reg64(dst, rd, ctx);
744 }
745 
746 /* dst = src (4 bytes)*/
emit_a32_mov_r(const s8 dst,const s8 src,struct jit_ctx * ctx)747 static inline void emit_a32_mov_r(const s8 dst, const s8 src,
748 				  struct jit_ctx *ctx) {
749 	const s8 *tmp = bpf2a32[TMP_REG_1];
750 	s8 rt;
751 
752 	rt = arm_bpf_get_reg32(src, tmp[0], ctx);
753 	arm_bpf_put_reg32(dst, rt, ctx);
754 }
755 
756 /* dst = src */
emit_a32_mov_r64(const bool is64,const s8 dst[],const s8 src[],struct jit_ctx * ctx)757 static inline void emit_a32_mov_r64(const bool is64, const s8 dst[],
758 				  const s8 src[],
759 				  struct jit_ctx *ctx) {
760 	if (!is64) {
761 		emit_a32_mov_r(dst_lo, src_lo, ctx);
762 		if (!ctx->prog->aux->verifier_zext)
763 			/* Zero out high 4 bytes */
764 			emit_a32_mov_i(dst_hi, 0, ctx);
765 	} else if (__LINUX_ARM_ARCH__ < 6 &&
766 		   ctx->cpu_architecture < CPU_ARCH_ARMv5TE) {
767 		/* complete 8 byte move */
768 		emit_a32_mov_r(dst_lo, src_lo, ctx);
769 		emit_a32_mov_r(dst_hi, src_hi, ctx);
770 	} else if (is_stacked(src_lo) && is_stacked(dst_lo)) {
771 		const u8 *tmp = bpf2a32[TMP_REG_1];
772 
773 		emit(ARM_LDRD_I(tmp[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(src_lo)), ctx);
774 		emit(ARM_STRD_I(tmp[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(dst_lo)), ctx);
775 	} else if (is_stacked(src_lo)) {
776 		emit(ARM_LDRD_I(dst[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(src_lo)), ctx);
777 	} else if (is_stacked(dst_lo)) {
778 		emit(ARM_STRD_I(src[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(dst_lo)), ctx);
779 	} else {
780 		emit(ARM_MOV_R(dst[0], src[0]), ctx);
781 		emit(ARM_MOV_R(dst[1], src[1]), ctx);
782 	}
783 }
784 
785 /* Shift operations */
emit_a32_alu_i(const s8 dst,const u32 val,struct jit_ctx * ctx,const u8 op)786 static inline void emit_a32_alu_i(const s8 dst, const u32 val,
787 				struct jit_ctx *ctx, const u8 op) {
788 	const s8 *tmp = bpf2a32[TMP_REG_1];
789 	s8 rd;
790 
791 	rd = arm_bpf_get_reg32(dst, tmp[0], ctx);
792 
793 	/* Do shift operation */
794 	switch (op) {
795 	case BPF_LSH:
796 		emit(ARM_LSL_I(rd, rd, val), ctx);
797 		break;
798 	case BPF_RSH:
799 		emit(ARM_LSR_I(rd, rd, val), ctx);
800 		break;
801 	case BPF_ARSH:
802 		emit(ARM_ASR_I(rd, rd, val), ctx);
803 		break;
804 	case BPF_NEG:
805 		emit(ARM_RSB_I(rd, rd, val), ctx);
806 		break;
807 	}
808 
809 	arm_bpf_put_reg32(dst, rd, ctx);
810 }
811 
812 /* dst = ~dst (64 bit) */
emit_a32_neg64(const s8 dst[],struct jit_ctx * ctx)813 static inline void emit_a32_neg64(const s8 dst[],
814 				struct jit_ctx *ctx){
815 	const s8 *tmp = bpf2a32[TMP_REG_1];
816 	const s8 *rd;
817 
818 	/* Setup Operand */
819 	rd = arm_bpf_get_reg64(dst, tmp, ctx);
820 
821 	/* Do Negate Operation */
822 	emit(ARM_RSBS_I(rd[1], rd[1], 0), ctx);
823 	emit(ARM_RSC_I(rd[0], rd[0], 0), ctx);
824 
825 	arm_bpf_put_reg64(dst, rd, ctx);
826 }
827 
828 /* dst = dst << src */
emit_a32_lsh_r64(const s8 dst[],const s8 src[],struct jit_ctx * ctx)829 static inline void emit_a32_lsh_r64(const s8 dst[], const s8 src[],
830 				    struct jit_ctx *ctx) {
831 	const s8 *tmp = bpf2a32[TMP_REG_1];
832 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
833 	const s8 *rd;
834 	s8 rt;
835 
836 	/* Setup Operands */
837 	rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
838 	rd = arm_bpf_get_reg64(dst, tmp, ctx);
839 
840 	/* Do LSH operation */
841 	emit(ARM_SUB_I(ARM_IP, rt, 32), ctx);
842 	emit(ARM_RSB_I(tmp2[0], rt, 32), ctx);
843 	emit(ARM_MOV_SR(ARM_LR, rd[0], SRTYPE_ASL, rt), ctx);
844 	emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[1], SRTYPE_ASL, ARM_IP), ctx);
845 	emit(ARM_ORR_SR(ARM_IP, ARM_LR, rd[1], SRTYPE_LSR, tmp2[0]), ctx);
846 	emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_ASL, rt), ctx);
847 
848 	arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
849 	arm_bpf_put_reg32(dst_hi, ARM_IP, ctx);
850 }
851 
852 /* dst = dst >> src (signed)*/
emit_a32_arsh_r64(const s8 dst[],const s8 src[],struct jit_ctx * ctx)853 static inline void emit_a32_arsh_r64(const s8 dst[], const s8 src[],
854 				     struct jit_ctx *ctx) {
855 	const s8 *tmp = bpf2a32[TMP_REG_1];
856 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
857 	const s8 *rd;
858 	s8 rt;
859 
860 	/* Setup Operands */
861 	rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
862 	rd = arm_bpf_get_reg64(dst, tmp, ctx);
863 
864 	/* Do the ARSH operation */
865 	emit(ARM_RSB_I(ARM_IP, rt, 32), ctx);
866 	emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
867 	emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_LSR, rt), ctx);
868 	emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASL, ARM_IP), ctx);
869 	_emit(ARM_COND_PL,
870 	      ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASR, tmp2[0]), ctx);
871 	emit(ARM_MOV_SR(ARM_IP, rd[0], SRTYPE_ASR, rt), ctx);
872 
873 	arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
874 	arm_bpf_put_reg32(dst_hi, ARM_IP, ctx);
875 }
876 
877 /* dst = dst >> src */
emit_a32_rsh_r64(const s8 dst[],const s8 src[],struct jit_ctx * ctx)878 static inline void emit_a32_rsh_r64(const s8 dst[], const s8 src[],
879 				    struct jit_ctx *ctx) {
880 	const s8 *tmp = bpf2a32[TMP_REG_1];
881 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
882 	const s8 *rd;
883 	s8 rt;
884 
885 	/* Setup Operands */
886 	rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
887 	rd = arm_bpf_get_reg64(dst, tmp, ctx);
888 
889 	/* Do RSH operation */
890 	emit(ARM_RSB_I(ARM_IP, rt, 32), ctx);
891 	emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
892 	emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_LSR, rt), ctx);
893 	emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASL, ARM_IP), ctx);
894 	emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_LSR, tmp2[0]), ctx);
895 	emit(ARM_MOV_SR(ARM_IP, rd[0], SRTYPE_LSR, rt), ctx);
896 
897 	arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
898 	arm_bpf_put_reg32(dst_hi, ARM_IP, ctx);
899 }
900 
901 /* dst = dst << val */
emit_a32_lsh_i64(const s8 dst[],const u32 val,struct jit_ctx * ctx)902 static inline void emit_a32_lsh_i64(const s8 dst[],
903 				    const u32 val, struct jit_ctx *ctx){
904 	const s8 *tmp = bpf2a32[TMP_REG_1];
905 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
906 	const s8 *rd;
907 
908 	/* Setup operands */
909 	rd = arm_bpf_get_reg64(dst, tmp, ctx);
910 
911 	/* Do LSH operation */
912 	if (val < 32) {
913 		emit(ARM_MOV_SI(tmp2[0], rd[0], SRTYPE_ASL, val), ctx);
914 		emit(ARM_ORR_SI(rd[0], tmp2[0], rd[1], SRTYPE_LSR, 32 - val), ctx);
915 		emit(ARM_MOV_SI(rd[1], rd[1], SRTYPE_ASL, val), ctx);
916 	} else {
917 		if (val == 32)
918 			emit(ARM_MOV_R(rd[0], rd[1]), ctx);
919 		else
920 			emit(ARM_MOV_SI(rd[0], rd[1], SRTYPE_ASL, val - 32), ctx);
921 		emit(ARM_EOR_R(rd[1], rd[1], rd[1]), ctx);
922 	}
923 
924 	arm_bpf_put_reg64(dst, rd, ctx);
925 }
926 
927 /* dst = dst >> val */
emit_a32_rsh_i64(const s8 dst[],const u32 val,struct jit_ctx * ctx)928 static inline void emit_a32_rsh_i64(const s8 dst[],
929 				    const u32 val, struct jit_ctx *ctx) {
930 	const s8 *tmp = bpf2a32[TMP_REG_1];
931 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
932 	const s8 *rd;
933 
934 	/* Setup operands */
935 	rd = arm_bpf_get_reg64(dst, tmp, ctx);
936 
937 	/* Do LSR operation */
938 	if (val == 0) {
939 		/* An immediate value of 0 encodes a shift amount of 32
940 		 * for LSR. To shift by 0, don't do anything.
941 		 */
942 	} else if (val < 32) {
943 		emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx);
944 		emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx);
945 		emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_LSR, val), ctx);
946 	} else if (val == 32) {
947 		emit(ARM_MOV_R(rd[1], rd[0]), ctx);
948 		emit(ARM_MOV_I(rd[0], 0), ctx);
949 	} else {
950 		emit(ARM_MOV_SI(rd[1], rd[0], SRTYPE_LSR, val - 32), ctx);
951 		emit(ARM_MOV_I(rd[0], 0), ctx);
952 	}
953 
954 	arm_bpf_put_reg64(dst, rd, ctx);
955 }
956 
957 /* dst = dst >> val (signed) */
emit_a32_arsh_i64(const s8 dst[],const u32 val,struct jit_ctx * ctx)958 static inline void emit_a32_arsh_i64(const s8 dst[],
959 				     const u32 val, struct jit_ctx *ctx){
960 	const s8 *tmp = bpf2a32[TMP_REG_1];
961 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
962 	const s8 *rd;
963 
964 	/* Setup operands */
965 	rd = arm_bpf_get_reg64(dst, tmp, ctx);
966 
967 	/* Do ARSH operation */
968 	if (val == 0) {
969 		/* An immediate value of 0 encodes a shift amount of 32
970 		 * for ASR. To shift by 0, don't do anything.
971 		 */
972 	} else if (val < 32) {
973 		emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx);
974 		emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx);
975 		emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, val), ctx);
976 	} else if (val == 32) {
977 		emit(ARM_MOV_R(rd[1], rd[0]), ctx);
978 		emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, 31), ctx);
979 	} else {
980 		emit(ARM_MOV_SI(rd[1], rd[0], SRTYPE_ASR, val - 32), ctx);
981 		emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, 31), ctx);
982 	}
983 
984 	arm_bpf_put_reg64(dst, rd, ctx);
985 }
986 
emit_a32_mul_r64(const s8 dst[],const s8 src[],struct jit_ctx * ctx)987 static inline void emit_a32_mul_r64(const s8 dst[], const s8 src[],
988 				    struct jit_ctx *ctx) {
989 	const s8 *tmp = bpf2a32[TMP_REG_1];
990 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
991 	const s8 *rd, *rt;
992 
993 	/* Setup operands for multiplication */
994 	rd = arm_bpf_get_reg64(dst, tmp, ctx);
995 	rt = arm_bpf_get_reg64(src, tmp2, ctx);
996 
997 	/* Do Multiplication */
998 	emit(ARM_MUL(ARM_IP, rd[1], rt[0]), ctx);
999 	emit(ARM_MUL(ARM_LR, rd[0], rt[1]), ctx);
1000 	emit(ARM_ADD_R(ARM_LR, ARM_IP, ARM_LR), ctx);
1001 
1002 	emit(ARM_UMULL(ARM_IP, rd[0], rd[1], rt[1]), ctx);
1003 	emit(ARM_ADD_R(rd[0], ARM_LR, rd[0]), ctx);
1004 
1005 	arm_bpf_put_reg32(dst_lo, ARM_IP, ctx);
1006 	arm_bpf_put_reg32(dst_hi, rd[0], ctx);
1007 }
1008 
is_ldst_imm(s16 off,const u8 size)1009 static bool is_ldst_imm(s16 off, const u8 size)
1010 {
1011 	s16 off_max = 0;
1012 
1013 	switch (size) {
1014 	case BPF_B:
1015 	case BPF_W:
1016 		off_max = 0xfff;
1017 		break;
1018 	case BPF_H:
1019 		off_max = 0xff;
1020 		break;
1021 	case BPF_DW:
1022 		/* Need to make sure off+4 does not overflow. */
1023 		off_max = 0xfff - 4;
1024 		break;
1025 	}
1026 	return -off_max <= off && off <= off_max;
1027 }
1028 
1029 /* *(size *)(dst + off) = src */
emit_str_r(const s8 dst,const s8 src[],s16 off,struct jit_ctx * ctx,const u8 sz)1030 static inline void emit_str_r(const s8 dst, const s8 src[],
1031 			      s16 off, struct jit_ctx *ctx, const u8 sz){
1032 	const s8 *tmp = bpf2a32[TMP_REG_1];
1033 	s8 rd;
1034 
1035 	rd = arm_bpf_get_reg32(dst, tmp[1], ctx);
1036 
1037 	if (!is_ldst_imm(off, sz)) {
1038 		emit_a32_mov_i(tmp[0], off, ctx);
1039 		emit(ARM_ADD_R(tmp[0], tmp[0], rd), ctx);
1040 		rd = tmp[0];
1041 		off = 0;
1042 	}
1043 	switch (sz) {
1044 	case BPF_B:
1045 		/* Store a Byte */
1046 		emit(ARM_STRB_I(src_lo, rd, off), ctx);
1047 		break;
1048 	case BPF_H:
1049 		/* Store a HalfWord */
1050 		emit(ARM_STRH_I(src_lo, rd, off), ctx);
1051 		break;
1052 	case BPF_W:
1053 		/* Store a Word */
1054 		emit(ARM_STR_I(src_lo, rd, off), ctx);
1055 		break;
1056 	case BPF_DW:
1057 		/* Store a Double Word */
1058 		emit(ARM_STR_I(src_lo, rd, off), ctx);
1059 		emit(ARM_STR_I(src_hi, rd, off + 4), ctx);
1060 		break;
1061 	}
1062 }
1063 
1064 /* dst = *(size*)(src + off) */
emit_ldx_r(const s8 dst[],const s8 src,s16 off,struct jit_ctx * ctx,const u8 sz)1065 static inline void emit_ldx_r(const s8 dst[], const s8 src,
1066 			      s16 off, struct jit_ctx *ctx, const u8 sz){
1067 	const s8 *tmp = bpf2a32[TMP_REG_1];
1068 	const s8 *rd = is_stacked(dst_lo) ? tmp : dst;
1069 	s8 rm = src;
1070 
1071 	if (!is_ldst_imm(off, sz)) {
1072 		emit_a32_mov_i(tmp[0], off, ctx);
1073 		emit(ARM_ADD_R(tmp[0], tmp[0], src), ctx);
1074 		rm = tmp[0];
1075 		off = 0;
1076 	} else if (rd[1] == rm) {
1077 		emit(ARM_MOV_R(tmp[0], rm), ctx);
1078 		rm = tmp[0];
1079 	}
1080 	switch (sz) {
1081 	case BPF_B:
1082 		/* Load a Byte */
1083 		emit(ARM_LDRB_I(rd[1], rm, off), ctx);
1084 		if (!ctx->prog->aux->verifier_zext)
1085 			emit_a32_mov_i(rd[0], 0, ctx);
1086 		break;
1087 	case BPF_H:
1088 		/* Load a HalfWord */
1089 		emit(ARM_LDRH_I(rd[1], rm, off), ctx);
1090 		if (!ctx->prog->aux->verifier_zext)
1091 			emit_a32_mov_i(rd[0], 0, ctx);
1092 		break;
1093 	case BPF_W:
1094 		/* Load a Word */
1095 		emit(ARM_LDR_I(rd[1], rm, off), ctx);
1096 		if (!ctx->prog->aux->verifier_zext)
1097 			emit_a32_mov_i(rd[0], 0, ctx);
1098 		break;
1099 	case BPF_DW:
1100 		/* Load a Double Word */
1101 		emit(ARM_LDR_I(rd[1], rm, off), ctx);
1102 		emit(ARM_LDR_I(rd[0], rm, off + 4), ctx);
1103 		break;
1104 	}
1105 	arm_bpf_put_reg64(dst, rd, ctx);
1106 }
1107 
1108 /* Arithmatic Operation */
emit_ar_r(const u8 rd,const u8 rt,const u8 rm,const u8 rn,struct jit_ctx * ctx,u8 op,bool is_jmp64)1109 static inline void emit_ar_r(const u8 rd, const u8 rt, const u8 rm,
1110 			     const u8 rn, struct jit_ctx *ctx, u8 op,
1111 			     bool is_jmp64) {
1112 	switch (op) {
1113 	case BPF_JSET:
1114 		if (is_jmp64) {
1115 			emit(ARM_AND_R(ARM_IP, rt, rn), ctx);
1116 			emit(ARM_AND_R(ARM_LR, rd, rm), ctx);
1117 			emit(ARM_ORRS_R(ARM_IP, ARM_LR, ARM_IP), ctx);
1118 		} else {
1119 			emit(ARM_ANDS_R(ARM_IP, rt, rn), ctx);
1120 		}
1121 		break;
1122 	case BPF_JEQ:
1123 	case BPF_JNE:
1124 	case BPF_JGT:
1125 	case BPF_JGE:
1126 	case BPF_JLE:
1127 	case BPF_JLT:
1128 		if (is_jmp64) {
1129 			emit(ARM_CMP_R(rd, rm), ctx);
1130 			/* Only compare low halve if high halve are equal. */
1131 			_emit(ARM_COND_EQ, ARM_CMP_R(rt, rn), ctx);
1132 		} else {
1133 			emit(ARM_CMP_R(rt, rn), ctx);
1134 		}
1135 		break;
1136 	case BPF_JSLE:
1137 	case BPF_JSGT:
1138 		emit(ARM_CMP_R(rn, rt), ctx);
1139 		if (is_jmp64)
1140 			emit(ARM_SBCS_R(ARM_IP, rm, rd), ctx);
1141 		break;
1142 	case BPF_JSLT:
1143 	case BPF_JSGE:
1144 		emit(ARM_CMP_R(rt, rn), ctx);
1145 		if (is_jmp64)
1146 			emit(ARM_SBCS_R(ARM_IP, rd, rm), ctx);
1147 		break;
1148 	}
1149 }
1150 
1151 static int out_offset = -1; /* initialized on the first pass of build_body() */
emit_bpf_tail_call(struct jit_ctx * ctx)1152 static int emit_bpf_tail_call(struct jit_ctx *ctx)
1153 {
1154 
1155 	/* bpf_tail_call(void *prog_ctx, struct bpf_array *array, u64 index) */
1156 	const s8 *r2 = bpf2a32[BPF_REG_2];
1157 	const s8 *r3 = bpf2a32[BPF_REG_3];
1158 	const s8 *tmp = bpf2a32[TMP_REG_1];
1159 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
1160 	const s8 *tcc = bpf2a32[TCALL_CNT];
1161 	const s8 *tc;
1162 	const int idx0 = ctx->idx;
1163 #define cur_offset (ctx->idx - idx0)
1164 #define jmp_offset (out_offset - (cur_offset) - 2)
1165 	u32 lo, hi;
1166 	s8 r_array, r_index;
1167 	int off;
1168 
1169 	/* if (index >= array->map.max_entries)
1170 	 *	goto out;
1171 	 */
1172 	BUILD_BUG_ON(offsetof(struct bpf_array, map.max_entries) >
1173 		     ARM_INST_LDST__IMM12);
1174 	off = offsetof(struct bpf_array, map.max_entries);
1175 	r_array = arm_bpf_get_reg32(r2[1], tmp2[0], ctx);
1176 	/* index is 32-bit for arrays */
1177 	r_index = arm_bpf_get_reg32(r3[1], tmp2[1], ctx);
1178 	/* array->map.max_entries */
1179 	emit(ARM_LDR_I(tmp[1], r_array, off), ctx);
1180 	/* index >= array->map.max_entries */
1181 	emit(ARM_CMP_R(r_index, tmp[1]), ctx);
1182 	_emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
1183 
1184 	/* tmp2[0] = array, tmp2[1] = index */
1185 
1186 	/*
1187 	 * if (tail_call_cnt >= MAX_TAIL_CALL_CNT)
1188 	 *	goto out;
1189 	 * tail_call_cnt++;
1190 	 */
1191 	lo = (u32)MAX_TAIL_CALL_CNT;
1192 	hi = (u32)((u64)MAX_TAIL_CALL_CNT >> 32);
1193 	tc = arm_bpf_get_reg64(tcc, tmp, ctx);
1194 	emit(ARM_CMP_I(tc[0], hi), ctx);
1195 	_emit(ARM_COND_EQ, ARM_CMP_I(tc[1], lo), ctx);
1196 	_emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
1197 	emit(ARM_ADDS_I(tc[1], tc[1], 1), ctx);
1198 	emit(ARM_ADC_I(tc[0], tc[0], 0), ctx);
1199 	arm_bpf_put_reg64(tcc, tmp, ctx);
1200 
1201 	/* prog = array->ptrs[index]
1202 	 * if (prog == NULL)
1203 	 *	goto out;
1204 	 */
1205 	BUILD_BUG_ON(imm8m(offsetof(struct bpf_array, ptrs)) < 0);
1206 	off = imm8m(offsetof(struct bpf_array, ptrs));
1207 	emit(ARM_ADD_I(tmp[1], r_array, off), ctx);
1208 	emit(ARM_LDR_R_SI(tmp[1], tmp[1], r_index, SRTYPE_ASL, 2), ctx);
1209 	emit(ARM_CMP_I(tmp[1], 0), ctx);
1210 	_emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx);
1211 
1212 	/* goto *(prog->bpf_func + prologue_size); */
1213 	BUILD_BUG_ON(offsetof(struct bpf_prog, bpf_func) >
1214 		     ARM_INST_LDST__IMM12);
1215 	off = offsetof(struct bpf_prog, bpf_func);
1216 	emit(ARM_LDR_I(tmp[1], tmp[1], off), ctx);
1217 	emit(ARM_ADD_I(tmp[1], tmp[1], ctx->prologue_bytes), ctx);
1218 	emit_bx_r(tmp[1], ctx);
1219 
1220 	/* out: */
1221 	if (out_offset == -1)
1222 		out_offset = cur_offset;
1223 	if (cur_offset != out_offset) {
1224 		pr_err_once("tail_call out_offset = %d, expected %d!\n",
1225 			    cur_offset, out_offset);
1226 		return -1;
1227 	}
1228 	return 0;
1229 #undef cur_offset
1230 #undef jmp_offset
1231 }
1232 
1233 /* 0xabcd => 0xcdab */
emit_rev16(const u8 rd,const u8 rn,struct jit_ctx * ctx)1234 static inline void emit_rev16(const u8 rd, const u8 rn, struct jit_ctx *ctx)
1235 {
1236 #if __LINUX_ARM_ARCH__ < 6
1237 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
1238 
1239 	emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx);
1240 	emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 8), ctx);
1241 	emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx);
1242 	emit(ARM_ORR_SI(rd, tmp2[0], tmp2[1], SRTYPE_LSL, 8), ctx);
1243 #else /* ARMv6+ */
1244 	emit(ARM_REV16(rd, rn), ctx);
1245 #endif
1246 }
1247 
1248 /* 0xabcdefgh => 0xghefcdab */
emit_rev32(const u8 rd,const u8 rn,struct jit_ctx * ctx)1249 static inline void emit_rev32(const u8 rd, const u8 rn, struct jit_ctx *ctx)
1250 {
1251 #if __LINUX_ARM_ARCH__ < 6
1252 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
1253 
1254 	emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx);
1255 	emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 24), ctx);
1256 	emit(ARM_ORR_SI(ARM_IP, tmp2[0], tmp2[1], SRTYPE_LSL, 24), ctx);
1257 
1258 	emit(ARM_MOV_SI(tmp2[1], rn, SRTYPE_LSR, 8), ctx);
1259 	emit(ARM_AND_I(tmp2[1], tmp2[1], 0xff), ctx);
1260 	emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 16), ctx);
1261 	emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx);
1262 	emit(ARM_MOV_SI(tmp2[0], tmp2[0], SRTYPE_LSL, 8), ctx);
1263 	emit(ARM_ORR_SI(tmp2[0], tmp2[0], tmp2[1], SRTYPE_LSL, 16), ctx);
1264 	emit(ARM_ORR_R(rd, ARM_IP, tmp2[0]), ctx);
1265 
1266 #else /* ARMv6+ */
1267 	emit(ARM_REV(rd, rn), ctx);
1268 #endif
1269 }
1270 
1271 // push the scratch stack register on top of the stack
emit_push_r64(const s8 src[],struct jit_ctx * ctx)1272 static inline void emit_push_r64(const s8 src[], struct jit_ctx *ctx)
1273 {
1274 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
1275 	const s8 *rt;
1276 	u16 reg_set = 0;
1277 
1278 	rt = arm_bpf_get_reg64(src, tmp2, ctx);
1279 
1280 	reg_set = (1 << rt[1]) | (1 << rt[0]);
1281 	emit(ARM_PUSH(reg_set), ctx);
1282 }
1283 
build_prologue(struct jit_ctx * ctx)1284 static void build_prologue(struct jit_ctx *ctx)
1285 {
1286 	const s8 arm_r0 = bpf2a32[BPF_REG_0][1];
1287 	const s8 *bpf_r1 = bpf2a32[BPF_REG_1];
1288 	const s8 *bpf_fp = bpf2a32[BPF_REG_FP];
1289 	const s8 *tcc = bpf2a32[TCALL_CNT];
1290 
1291 	/* Save callee saved registers. */
1292 #ifdef CONFIG_FRAME_POINTER
1293 	u16 reg_set = CALLEE_PUSH_MASK | 1 << ARM_IP | 1 << ARM_PC;
1294 	emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx);
1295 	emit(ARM_PUSH(reg_set), ctx);
1296 	emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx);
1297 #else
1298 	emit(ARM_PUSH(CALLEE_PUSH_MASK), ctx);
1299 	emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx);
1300 #endif
1301 	/* mov r3, #0 */
1302 	/* sub r2, sp, #SCRATCH_SIZE */
1303 	emit(ARM_MOV_I(bpf_r1[0], 0), ctx);
1304 	emit(ARM_SUB_I(bpf_r1[1], ARM_SP, SCRATCH_SIZE), ctx);
1305 
1306 	ctx->stack_size = imm8m(STACK_SIZE);
1307 
1308 	/* Set up function call stack */
1309 	emit(ARM_SUB_I(ARM_SP, ARM_SP, ctx->stack_size), ctx);
1310 
1311 	/* Set up BPF prog stack base register */
1312 	emit_a32_mov_r64(true, bpf_fp, bpf_r1, ctx);
1313 
1314 	/* Initialize Tail Count */
1315 	emit(ARM_MOV_I(bpf_r1[1], 0), ctx);
1316 	emit_a32_mov_r64(true, tcc, bpf_r1, ctx);
1317 
1318 	/* Move BPF_CTX to BPF_R1 */
1319 	emit(ARM_MOV_R(bpf_r1[1], arm_r0), ctx);
1320 
1321 	/* end of prologue */
1322 }
1323 
1324 /* restore callee saved registers. */
build_epilogue(struct jit_ctx * ctx)1325 static void build_epilogue(struct jit_ctx *ctx)
1326 {
1327 #ifdef CONFIG_FRAME_POINTER
1328 	/* When using frame pointers, some additional registers need to
1329 	 * be loaded. */
1330 	u16 reg_set = CALLEE_POP_MASK | 1 << ARM_SP;
1331 	emit(ARM_SUB_I(ARM_SP, ARM_FP, hweight16(reg_set) * 4), ctx);
1332 	emit(ARM_LDM(ARM_SP, reg_set), ctx);
1333 #else
1334 	/* Restore callee saved registers. */
1335 	emit(ARM_MOV_R(ARM_SP, ARM_FP), ctx);
1336 	emit(ARM_POP(CALLEE_POP_MASK), ctx);
1337 #endif
1338 }
1339 
1340 /*
1341  * Convert an eBPF instruction to native instruction, i.e
1342  * JITs an eBPF instruction.
1343  * Returns :
1344  *	0  - Successfully JITed an 8-byte eBPF instruction
1345  *	>0 - Successfully JITed a 16-byte eBPF instruction
1346  *	<0 - Failed to JIT.
1347  */
build_insn(const struct bpf_insn * insn,struct jit_ctx * ctx)1348 static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
1349 {
1350 	const u8 code = insn->code;
1351 	const s8 *dst = bpf2a32[insn->dst_reg];
1352 	const s8 *src = bpf2a32[insn->src_reg];
1353 	const s8 *tmp = bpf2a32[TMP_REG_1];
1354 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
1355 	const s16 off = insn->off;
1356 	const s32 imm = insn->imm;
1357 	const int i = insn - ctx->prog->insnsi;
1358 	const bool is64 = BPF_CLASS(code) == BPF_ALU64;
1359 	const s8 *rd, *rs;
1360 	s8 rd_lo, rt, rm, rn;
1361 	s32 jmp_offset;
1362 
1363 #define check_imm(bits, imm) do {				\
1364 	if ((imm) >= (1 << ((bits) - 1)) ||			\
1365 	    (imm) < -(1 << ((bits) - 1))) {			\
1366 		pr_info("[%2d] imm=%d(0x%x) out of range\n",	\
1367 			i, imm, imm);				\
1368 		return -EINVAL;					\
1369 	}							\
1370 } while (0)
1371 #define check_imm24(imm) check_imm(24, imm)
1372 
1373 	switch (code) {
1374 	/* ALU operations */
1375 
1376 	/* dst = src */
1377 	case BPF_ALU | BPF_MOV | BPF_K:
1378 	case BPF_ALU | BPF_MOV | BPF_X:
1379 	case BPF_ALU64 | BPF_MOV | BPF_K:
1380 	case BPF_ALU64 | BPF_MOV | BPF_X:
1381 		switch (BPF_SRC(code)) {
1382 		case BPF_X:
1383 			if (imm == 1) {
1384 				/* Special mov32 for zext */
1385 				emit_a32_mov_i(dst_hi, 0, ctx);
1386 				break;
1387 			}
1388 			emit_a32_mov_r64(is64, dst, src, ctx);
1389 			break;
1390 		case BPF_K:
1391 			/* Sign-extend immediate value to destination reg */
1392 			emit_a32_mov_se_i64(is64, dst, imm, ctx);
1393 			break;
1394 		}
1395 		break;
1396 	/* dst = dst + src/imm */
1397 	/* dst = dst - src/imm */
1398 	/* dst = dst | src/imm */
1399 	/* dst = dst & src/imm */
1400 	/* dst = dst ^ src/imm */
1401 	/* dst = dst * src/imm */
1402 	/* dst = dst << src */
1403 	/* dst = dst >> src */
1404 	case BPF_ALU | BPF_ADD | BPF_K:
1405 	case BPF_ALU | BPF_ADD | BPF_X:
1406 	case BPF_ALU | BPF_SUB | BPF_K:
1407 	case BPF_ALU | BPF_SUB | BPF_X:
1408 	case BPF_ALU | BPF_OR | BPF_K:
1409 	case BPF_ALU | BPF_OR | BPF_X:
1410 	case BPF_ALU | BPF_AND | BPF_K:
1411 	case BPF_ALU | BPF_AND | BPF_X:
1412 	case BPF_ALU | BPF_XOR | BPF_K:
1413 	case BPF_ALU | BPF_XOR | BPF_X:
1414 	case BPF_ALU | BPF_MUL | BPF_K:
1415 	case BPF_ALU | BPF_MUL | BPF_X:
1416 	case BPF_ALU | BPF_LSH | BPF_X:
1417 	case BPF_ALU | BPF_RSH | BPF_X:
1418 	case BPF_ALU | BPF_ARSH | BPF_X:
1419 	case BPF_ALU64 | BPF_ADD | BPF_K:
1420 	case BPF_ALU64 | BPF_ADD | BPF_X:
1421 	case BPF_ALU64 | BPF_SUB | BPF_K:
1422 	case BPF_ALU64 | BPF_SUB | BPF_X:
1423 	case BPF_ALU64 | BPF_OR | BPF_K:
1424 	case BPF_ALU64 | BPF_OR | BPF_X:
1425 	case BPF_ALU64 | BPF_AND | BPF_K:
1426 	case BPF_ALU64 | BPF_AND | BPF_X:
1427 	case BPF_ALU64 | BPF_XOR | BPF_K:
1428 	case BPF_ALU64 | BPF_XOR | BPF_X:
1429 		switch (BPF_SRC(code)) {
1430 		case BPF_X:
1431 			emit_a32_alu_r64(is64, dst, src, ctx, BPF_OP(code));
1432 			break;
1433 		case BPF_K:
1434 			/* Move immediate value to the temporary register
1435 			 * and then do the ALU operation on the temporary
1436 			 * register as this will sign-extend the immediate
1437 			 * value into temporary reg and then it would be
1438 			 * safe to do the operation on it.
1439 			 */
1440 			emit_a32_mov_se_i64(is64, tmp2, imm, ctx);
1441 			emit_a32_alu_r64(is64, dst, tmp2, ctx, BPF_OP(code));
1442 			break;
1443 		}
1444 		break;
1445 	/* dst = dst / src(imm) */
1446 	/* dst = dst % src(imm) */
1447 	case BPF_ALU | BPF_DIV | BPF_K:
1448 	case BPF_ALU | BPF_DIV | BPF_X:
1449 	case BPF_ALU | BPF_MOD | BPF_K:
1450 	case BPF_ALU | BPF_MOD | BPF_X:
1451 		rd_lo = arm_bpf_get_reg32(dst_lo, tmp2[1], ctx);
1452 		switch (BPF_SRC(code)) {
1453 		case BPF_X:
1454 			rt = arm_bpf_get_reg32(src_lo, tmp2[0], ctx);
1455 			break;
1456 		case BPF_K:
1457 			rt = tmp2[0];
1458 			emit_a32_mov_i(rt, imm, ctx);
1459 			break;
1460 		default:
1461 			rt = src_lo;
1462 			break;
1463 		}
1464 		emit_udivmod(rd_lo, rd_lo, rt, ctx, BPF_OP(code));
1465 		arm_bpf_put_reg32(dst_lo, rd_lo, ctx);
1466 		if (!ctx->prog->aux->verifier_zext)
1467 			emit_a32_mov_i(dst_hi, 0, ctx);
1468 		break;
1469 	case BPF_ALU64 | BPF_DIV | BPF_K:
1470 	case BPF_ALU64 | BPF_DIV | BPF_X:
1471 	case BPF_ALU64 | BPF_MOD | BPF_K:
1472 	case BPF_ALU64 | BPF_MOD | BPF_X:
1473 		goto notyet;
1474 	/* dst = dst << imm */
1475 	/* dst = dst >> imm */
1476 	/* dst = dst >> imm (signed) */
1477 	case BPF_ALU | BPF_LSH | BPF_K:
1478 	case BPF_ALU | BPF_RSH | BPF_K:
1479 	case BPF_ALU | BPF_ARSH | BPF_K:
1480 		if (unlikely(imm > 31))
1481 			return -EINVAL;
1482 		if (imm)
1483 			emit_a32_alu_i(dst_lo, imm, ctx, BPF_OP(code));
1484 		if (!ctx->prog->aux->verifier_zext)
1485 			emit_a32_mov_i(dst_hi, 0, ctx);
1486 		break;
1487 	/* dst = dst << imm */
1488 	case BPF_ALU64 | BPF_LSH | BPF_K:
1489 		if (unlikely(imm > 63))
1490 			return -EINVAL;
1491 		emit_a32_lsh_i64(dst, imm, ctx);
1492 		break;
1493 	/* dst = dst >> imm */
1494 	case BPF_ALU64 | BPF_RSH | BPF_K:
1495 		if (unlikely(imm > 63))
1496 			return -EINVAL;
1497 		emit_a32_rsh_i64(dst, imm, ctx);
1498 		break;
1499 	/* dst = dst << src */
1500 	case BPF_ALU64 | BPF_LSH | BPF_X:
1501 		emit_a32_lsh_r64(dst, src, ctx);
1502 		break;
1503 	/* dst = dst >> src */
1504 	case BPF_ALU64 | BPF_RSH | BPF_X:
1505 		emit_a32_rsh_r64(dst, src, ctx);
1506 		break;
1507 	/* dst = dst >> src (signed) */
1508 	case BPF_ALU64 | BPF_ARSH | BPF_X:
1509 		emit_a32_arsh_r64(dst, src, ctx);
1510 		break;
1511 	/* dst = dst >> imm (signed) */
1512 	case BPF_ALU64 | BPF_ARSH | BPF_K:
1513 		if (unlikely(imm > 63))
1514 			return -EINVAL;
1515 		emit_a32_arsh_i64(dst, imm, ctx);
1516 		break;
1517 	/* dst = ~dst */
1518 	case BPF_ALU | BPF_NEG:
1519 		emit_a32_alu_i(dst_lo, 0, ctx, BPF_OP(code));
1520 		if (!ctx->prog->aux->verifier_zext)
1521 			emit_a32_mov_i(dst_hi, 0, ctx);
1522 		break;
1523 	/* dst = ~dst (64 bit) */
1524 	case BPF_ALU64 | BPF_NEG:
1525 		emit_a32_neg64(dst, ctx);
1526 		break;
1527 	/* dst = dst * src/imm */
1528 	case BPF_ALU64 | BPF_MUL | BPF_X:
1529 	case BPF_ALU64 | BPF_MUL | BPF_K:
1530 		switch (BPF_SRC(code)) {
1531 		case BPF_X:
1532 			emit_a32_mul_r64(dst, src, ctx);
1533 			break;
1534 		case BPF_K:
1535 			/* Move immediate value to the temporary register
1536 			 * and then do the multiplication on it as this
1537 			 * will sign-extend the immediate value into temp
1538 			 * reg then it would be safe to do the operation
1539 			 * on it.
1540 			 */
1541 			emit_a32_mov_se_i64(is64, tmp2, imm, ctx);
1542 			emit_a32_mul_r64(dst, tmp2, ctx);
1543 			break;
1544 		}
1545 		break;
1546 	/* dst = htole(dst) */
1547 	/* dst = htobe(dst) */
1548 	case BPF_ALU | BPF_END | BPF_FROM_LE:
1549 	case BPF_ALU | BPF_END | BPF_FROM_BE:
1550 		rd = arm_bpf_get_reg64(dst, tmp, ctx);
1551 		if (BPF_SRC(code) == BPF_FROM_LE)
1552 			goto emit_bswap_uxt;
1553 		switch (imm) {
1554 		case 16:
1555 			emit_rev16(rd[1], rd[1], ctx);
1556 			goto emit_bswap_uxt;
1557 		case 32:
1558 			emit_rev32(rd[1], rd[1], ctx);
1559 			goto emit_bswap_uxt;
1560 		case 64:
1561 			emit_rev32(ARM_LR, rd[1], ctx);
1562 			emit_rev32(rd[1], rd[0], ctx);
1563 			emit(ARM_MOV_R(rd[0], ARM_LR), ctx);
1564 			break;
1565 		}
1566 		goto exit;
1567 emit_bswap_uxt:
1568 		switch (imm) {
1569 		case 16:
1570 			/* zero-extend 16 bits into 64 bits */
1571 #if __LINUX_ARM_ARCH__ < 6
1572 			emit_a32_mov_i(tmp2[1], 0xffff, ctx);
1573 			emit(ARM_AND_R(rd[1], rd[1], tmp2[1]), ctx);
1574 #else /* ARMv6+ */
1575 			emit(ARM_UXTH(rd[1], rd[1]), ctx);
1576 #endif
1577 			if (!ctx->prog->aux->verifier_zext)
1578 				emit(ARM_EOR_R(rd[0], rd[0], rd[0]), ctx);
1579 			break;
1580 		case 32:
1581 			/* zero-extend 32 bits into 64 bits */
1582 			if (!ctx->prog->aux->verifier_zext)
1583 				emit(ARM_EOR_R(rd[0], rd[0], rd[0]), ctx);
1584 			break;
1585 		case 64:
1586 			/* nop */
1587 			break;
1588 		}
1589 exit:
1590 		arm_bpf_put_reg64(dst, rd, ctx);
1591 		break;
1592 	/* dst = imm64 */
1593 	case BPF_LD | BPF_IMM | BPF_DW:
1594 	{
1595 		u64 val = (u32)imm | (u64)insn[1].imm << 32;
1596 
1597 		emit_a32_mov_i64(dst, val, ctx);
1598 
1599 		return 1;
1600 	}
1601 	/* LDX: dst = *(size *)(src + off) */
1602 	case BPF_LDX | BPF_MEM | BPF_W:
1603 	case BPF_LDX | BPF_MEM | BPF_H:
1604 	case BPF_LDX | BPF_MEM | BPF_B:
1605 	case BPF_LDX | BPF_MEM | BPF_DW:
1606 		rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
1607 		emit_ldx_r(dst, rn, off, ctx, BPF_SIZE(code));
1608 		break;
1609 	/* speculation barrier */
1610 	case BPF_ST | BPF_NOSPEC:
1611 		break;
1612 	/* ST: *(size *)(dst + off) = imm */
1613 	case BPF_ST | BPF_MEM | BPF_W:
1614 	case BPF_ST | BPF_MEM | BPF_H:
1615 	case BPF_ST | BPF_MEM | BPF_B:
1616 	case BPF_ST | BPF_MEM | BPF_DW:
1617 		switch (BPF_SIZE(code)) {
1618 		case BPF_DW:
1619 			/* Sign-extend immediate value into temp reg */
1620 			emit_a32_mov_se_i64(true, tmp2, imm, ctx);
1621 			break;
1622 		case BPF_W:
1623 		case BPF_H:
1624 		case BPF_B:
1625 			emit_a32_mov_i(tmp2[1], imm, ctx);
1626 			break;
1627 		}
1628 		emit_str_r(dst_lo, tmp2, off, ctx, BPF_SIZE(code));
1629 		break;
1630 	/* Atomic ops */
1631 	case BPF_STX | BPF_ATOMIC | BPF_W:
1632 	case BPF_STX | BPF_ATOMIC | BPF_DW:
1633 		goto notyet;
1634 	/* STX: *(size *)(dst + off) = src */
1635 	case BPF_STX | BPF_MEM | BPF_W:
1636 	case BPF_STX | BPF_MEM | BPF_H:
1637 	case BPF_STX | BPF_MEM | BPF_B:
1638 	case BPF_STX | BPF_MEM | BPF_DW:
1639 		rs = arm_bpf_get_reg64(src, tmp2, ctx);
1640 		emit_str_r(dst_lo, rs, off, ctx, BPF_SIZE(code));
1641 		break;
1642 	/* PC += off if dst == src */
1643 	/* PC += off if dst > src */
1644 	/* PC += off if dst >= src */
1645 	/* PC += off if dst < src */
1646 	/* PC += off if dst <= src */
1647 	/* PC += off if dst != src */
1648 	/* PC += off if dst > src (signed) */
1649 	/* PC += off if dst >= src (signed) */
1650 	/* PC += off if dst < src (signed) */
1651 	/* PC += off if dst <= src (signed) */
1652 	/* PC += off if dst & src */
1653 	case BPF_JMP | BPF_JEQ | BPF_X:
1654 	case BPF_JMP | BPF_JGT | BPF_X:
1655 	case BPF_JMP | BPF_JGE | BPF_X:
1656 	case BPF_JMP | BPF_JNE | BPF_X:
1657 	case BPF_JMP | BPF_JSGT | BPF_X:
1658 	case BPF_JMP | BPF_JSGE | BPF_X:
1659 	case BPF_JMP | BPF_JSET | BPF_X:
1660 	case BPF_JMP | BPF_JLE | BPF_X:
1661 	case BPF_JMP | BPF_JLT | BPF_X:
1662 	case BPF_JMP | BPF_JSLT | BPF_X:
1663 	case BPF_JMP | BPF_JSLE | BPF_X:
1664 	case BPF_JMP32 | BPF_JEQ | BPF_X:
1665 	case BPF_JMP32 | BPF_JGT | BPF_X:
1666 	case BPF_JMP32 | BPF_JGE | BPF_X:
1667 	case BPF_JMP32 | BPF_JNE | BPF_X:
1668 	case BPF_JMP32 | BPF_JSGT | BPF_X:
1669 	case BPF_JMP32 | BPF_JSGE | BPF_X:
1670 	case BPF_JMP32 | BPF_JSET | BPF_X:
1671 	case BPF_JMP32 | BPF_JLE | BPF_X:
1672 	case BPF_JMP32 | BPF_JLT | BPF_X:
1673 	case BPF_JMP32 | BPF_JSLT | BPF_X:
1674 	case BPF_JMP32 | BPF_JSLE | BPF_X:
1675 		/* Setup source registers */
1676 		rm = arm_bpf_get_reg32(src_hi, tmp2[0], ctx);
1677 		rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
1678 		goto go_jmp;
1679 	/* PC += off if dst == imm */
1680 	/* PC += off if dst > imm */
1681 	/* PC += off if dst >= imm */
1682 	/* PC += off if dst < imm */
1683 	/* PC += off if dst <= imm */
1684 	/* PC += off if dst != imm */
1685 	/* PC += off if dst > imm (signed) */
1686 	/* PC += off if dst >= imm (signed) */
1687 	/* PC += off if dst < imm (signed) */
1688 	/* PC += off if dst <= imm (signed) */
1689 	/* PC += off if dst & imm */
1690 	case BPF_JMP | BPF_JEQ | BPF_K:
1691 	case BPF_JMP | BPF_JGT | BPF_K:
1692 	case BPF_JMP | BPF_JGE | BPF_K:
1693 	case BPF_JMP | BPF_JNE | BPF_K:
1694 	case BPF_JMP | BPF_JSGT | BPF_K:
1695 	case BPF_JMP | BPF_JSGE | BPF_K:
1696 	case BPF_JMP | BPF_JSET | BPF_K:
1697 	case BPF_JMP | BPF_JLT | BPF_K:
1698 	case BPF_JMP | BPF_JLE | BPF_K:
1699 	case BPF_JMP | BPF_JSLT | BPF_K:
1700 	case BPF_JMP | BPF_JSLE | BPF_K:
1701 	case BPF_JMP32 | BPF_JEQ | BPF_K:
1702 	case BPF_JMP32 | BPF_JGT | BPF_K:
1703 	case BPF_JMP32 | BPF_JGE | BPF_K:
1704 	case BPF_JMP32 | BPF_JNE | BPF_K:
1705 	case BPF_JMP32 | BPF_JSGT | BPF_K:
1706 	case BPF_JMP32 | BPF_JSGE | BPF_K:
1707 	case BPF_JMP32 | BPF_JSET | BPF_K:
1708 	case BPF_JMP32 | BPF_JLT | BPF_K:
1709 	case BPF_JMP32 | BPF_JLE | BPF_K:
1710 	case BPF_JMP32 | BPF_JSLT | BPF_K:
1711 	case BPF_JMP32 | BPF_JSLE | BPF_K:
1712 		if (off == 0)
1713 			break;
1714 		rm = tmp2[0];
1715 		rn = tmp2[1];
1716 		/* Sign-extend immediate value */
1717 		emit_a32_mov_se_i64(true, tmp2, imm, ctx);
1718 go_jmp:
1719 		/* Setup destination register */
1720 		rd = arm_bpf_get_reg64(dst, tmp, ctx);
1721 
1722 		/* Check for the condition */
1723 		emit_ar_r(rd[0], rd[1], rm, rn, ctx, BPF_OP(code),
1724 			  BPF_CLASS(code) == BPF_JMP);
1725 
1726 		/* Setup JUMP instruction */
1727 		jmp_offset = bpf2a32_offset(i+off, i, ctx);
1728 		switch (BPF_OP(code)) {
1729 		case BPF_JNE:
1730 		case BPF_JSET:
1731 			_emit(ARM_COND_NE, ARM_B(jmp_offset), ctx);
1732 			break;
1733 		case BPF_JEQ:
1734 			_emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx);
1735 			break;
1736 		case BPF_JGT:
1737 			_emit(ARM_COND_HI, ARM_B(jmp_offset), ctx);
1738 			break;
1739 		case BPF_JGE:
1740 			_emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
1741 			break;
1742 		case BPF_JSGT:
1743 			_emit(ARM_COND_LT, ARM_B(jmp_offset), ctx);
1744 			break;
1745 		case BPF_JSGE:
1746 			_emit(ARM_COND_GE, ARM_B(jmp_offset), ctx);
1747 			break;
1748 		case BPF_JLE:
1749 			_emit(ARM_COND_LS, ARM_B(jmp_offset), ctx);
1750 			break;
1751 		case BPF_JLT:
1752 			_emit(ARM_COND_CC, ARM_B(jmp_offset), ctx);
1753 			break;
1754 		case BPF_JSLT:
1755 			_emit(ARM_COND_LT, ARM_B(jmp_offset), ctx);
1756 			break;
1757 		case BPF_JSLE:
1758 			_emit(ARM_COND_GE, ARM_B(jmp_offset), ctx);
1759 			break;
1760 		}
1761 		break;
1762 	/* JMP OFF */
1763 	case BPF_JMP | BPF_JA:
1764 	{
1765 		if (off == 0)
1766 			break;
1767 		jmp_offset = bpf2a32_offset(i+off, i, ctx);
1768 		check_imm24(jmp_offset);
1769 		emit(ARM_B(jmp_offset), ctx);
1770 		break;
1771 	}
1772 	/* tail call */
1773 	case BPF_JMP | BPF_TAIL_CALL:
1774 		if (emit_bpf_tail_call(ctx))
1775 			return -EFAULT;
1776 		break;
1777 	/* function call */
1778 	case BPF_JMP | BPF_CALL:
1779 	{
1780 		const s8 *r0 = bpf2a32[BPF_REG_0];
1781 		const s8 *r1 = bpf2a32[BPF_REG_1];
1782 		const s8 *r2 = bpf2a32[BPF_REG_2];
1783 		const s8 *r3 = bpf2a32[BPF_REG_3];
1784 		const s8 *r4 = bpf2a32[BPF_REG_4];
1785 		const s8 *r5 = bpf2a32[BPF_REG_5];
1786 		const u32 func = (u32)__bpf_call_base + (u32)imm;
1787 
1788 		emit_a32_mov_r64(true, r0, r1, ctx);
1789 		emit_a32_mov_r64(true, r1, r2, ctx);
1790 		emit_push_r64(r5, ctx);
1791 		emit_push_r64(r4, ctx);
1792 		emit_push_r64(r3, ctx);
1793 
1794 		emit_a32_mov_i(tmp[1], func, ctx);
1795 		emit_blx_r(tmp[1], ctx);
1796 
1797 		emit(ARM_ADD_I(ARM_SP, ARM_SP, imm8m(24)), ctx); // callee clean
1798 		break;
1799 	}
1800 	/* function return */
1801 	case BPF_JMP | BPF_EXIT:
1802 		/* Optimization: when last instruction is EXIT
1803 		 * simply fallthrough to epilogue.
1804 		 */
1805 		if (i == ctx->prog->len - 1)
1806 			break;
1807 		jmp_offset = epilogue_offset(ctx);
1808 		check_imm24(jmp_offset);
1809 		emit(ARM_B(jmp_offset), ctx);
1810 		break;
1811 notyet:
1812 		pr_info_once("*** NOT YET: opcode %02x ***\n", code);
1813 		return -EFAULT;
1814 	default:
1815 		pr_err_once("unknown opcode %02x\n", code);
1816 		return -EINVAL;
1817 	}
1818 
1819 	if (ctx->flags & FLAG_IMM_OVERFLOW)
1820 		/*
1821 		 * this instruction generated an overflow when
1822 		 * trying to access the literal pool, so
1823 		 * delegate this filter to the kernel interpreter.
1824 		 */
1825 		return -1;
1826 	return 0;
1827 }
1828 
build_body(struct jit_ctx * ctx)1829 static int build_body(struct jit_ctx *ctx)
1830 {
1831 	const struct bpf_prog *prog = ctx->prog;
1832 	unsigned int i;
1833 
1834 	for (i = 0; i < prog->len; i++) {
1835 		const struct bpf_insn *insn = &(prog->insnsi[i]);
1836 		int ret;
1837 
1838 		ret = build_insn(insn, ctx);
1839 
1840 		/* It's used with loading the 64 bit immediate value. */
1841 		if (ret > 0) {
1842 			i++;
1843 			if (ctx->target == NULL)
1844 				ctx->offsets[i] = ctx->idx;
1845 			continue;
1846 		}
1847 
1848 		if (ctx->target == NULL)
1849 			ctx->offsets[i] = ctx->idx;
1850 
1851 		/* If unsuccesful, return with error code */
1852 		if (ret)
1853 			return ret;
1854 	}
1855 	return 0;
1856 }
1857 
validate_code(struct jit_ctx * ctx)1858 static int validate_code(struct jit_ctx *ctx)
1859 {
1860 	int i;
1861 
1862 	for (i = 0; i < ctx->idx; i++) {
1863 		if (ctx->target[i] == __opcode_to_mem_arm(ARM_INST_UDF))
1864 			return -1;
1865 	}
1866 
1867 	return 0;
1868 }
1869 
bpf_jit_needs_zext(void)1870 bool bpf_jit_needs_zext(void)
1871 {
1872 	return true;
1873 }
1874 
bpf_int_jit_compile(struct bpf_prog * prog)1875 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
1876 {
1877 	struct bpf_prog *tmp, *orig_prog = prog;
1878 	struct bpf_binary_header *header;
1879 	bool tmp_blinded = false;
1880 	struct jit_ctx ctx;
1881 	unsigned int tmp_idx;
1882 	unsigned int image_size;
1883 	u8 *image_ptr;
1884 
1885 	/* If BPF JIT was not enabled then we must fall back to
1886 	 * the interpreter.
1887 	 */
1888 	if (!prog->jit_requested)
1889 		return orig_prog;
1890 
1891 	/* If constant blinding was enabled and we failed during blinding
1892 	 * then we must fall back to the interpreter. Otherwise, we save
1893 	 * the new JITed code.
1894 	 */
1895 	tmp = bpf_jit_blind_constants(prog);
1896 
1897 	if (IS_ERR(tmp))
1898 		return orig_prog;
1899 	if (tmp != prog) {
1900 		tmp_blinded = true;
1901 		prog = tmp;
1902 	}
1903 
1904 	memset(&ctx, 0, sizeof(ctx));
1905 	ctx.prog = prog;
1906 	ctx.cpu_architecture = cpu_architecture();
1907 
1908 	/* Not able to allocate memory for offsets[] , then
1909 	 * we must fall back to the interpreter
1910 	 */
1911 	ctx.offsets = kcalloc(prog->len, sizeof(int), GFP_KERNEL);
1912 	if (ctx.offsets == NULL) {
1913 		prog = orig_prog;
1914 		goto out;
1915 	}
1916 
1917 	/* 1) fake pass to find in the length of the JITed code,
1918 	 * to compute ctx->offsets and other context variables
1919 	 * needed to compute final JITed code.
1920 	 * Also, calculate random starting pointer/start of JITed code
1921 	 * which is prefixed by random number of fault instructions.
1922 	 *
1923 	 * If the first pass fails then there is no chance of it
1924 	 * being successful in the second pass, so just fall back
1925 	 * to the interpreter.
1926 	 */
1927 	if (build_body(&ctx)) {
1928 		prog = orig_prog;
1929 		goto out_off;
1930 	}
1931 
1932 	tmp_idx = ctx.idx;
1933 	build_prologue(&ctx);
1934 	ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
1935 
1936 	ctx.epilogue_offset = ctx.idx;
1937 
1938 #if __LINUX_ARM_ARCH__ < 7
1939 	tmp_idx = ctx.idx;
1940 	build_epilogue(&ctx);
1941 	ctx.epilogue_bytes = (ctx.idx - tmp_idx) * 4;
1942 
1943 	ctx.idx += ctx.imm_count;
1944 	if (ctx.imm_count) {
1945 		ctx.imms = kcalloc(ctx.imm_count, sizeof(u32), GFP_KERNEL);
1946 		if (ctx.imms == NULL) {
1947 			prog = orig_prog;
1948 			goto out_off;
1949 		}
1950 	}
1951 #else
1952 	/* there's nothing about the epilogue on ARMv7 */
1953 	build_epilogue(&ctx);
1954 #endif
1955 	/* Now we can get the actual image size of the JITed arm code.
1956 	 * Currently, we are not considering the THUMB-2 instructions
1957 	 * for jit, although it can decrease the size of the image.
1958 	 *
1959 	 * As each arm instruction is of length 32bit, we are translating
1960 	 * number of JITed instructions into the size required to store these
1961 	 * JITed code.
1962 	 */
1963 	image_size = sizeof(u32) * ctx.idx;
1964 
1965 	/* Now we know the size of the structure to make */
1966 	header = bpf_jit_binary_alloc(image_size, &image_ptr,
1967 				      sizeof(u32), jit_fill_hole);
1968 	/* Not able to allocate memory for the structure then
1969 	 * we must fall back to the interpretation
1970 	 */
1971 	if (header == NULL) {
1972 		prog = orig_prog;
1973 		goto out_imms;
1974 	}
1975 
1976 	/* 2.) Actual pass to generate final JIT code */
1977 	ctx.target = (u32 *) image_ptr;
1978 	ctx.idx = 0;
1979 
1980 	build_prologue(&ctx);
1981 
1982 	/* If building the body of the JITed code fails somehow,
1983 	 * we fall back to the interpretation.
1984 	 */
1985 	if (build_body(&ctx) < 0) {
1986 		image_ptr = NULL;
1987 		bpf_jit_binary_free(header);
1988 		prog = orig_prog;
1989 		goto out_imms;
1990 	}
1991 	build_epilogue(&ctx);
1992 
1993 	/* 3.) Extra pass to validate JITed Code */
1994 	if (validate_code(&ctx)) {
1995 		image_ptr = NULL;
1996 		bpf_jit_binary_free(header);
1997 		prog = orig_prog;
1998 		goto out_imms;
1999 	}
2000 	flush_icache_range((u32)header, (u32)(ctx.target + ctx.idx));
2001 
2002 	if (bpf_jit_enable > 1)
2003 		/* there are 2 passes here */
2004 		bpf_jit_dump(prog->len, image_size, 2, ctx.target);
2005 
2006 	bpf_jit_binary_lock_ro(header);
2007 	prog->bpf_func = (void *)ctx.target;
2008 	prog->jited = 1;
2009 	prog->jited_len = image_size;
2010 
2011 out_imms:
2012 #if __LINUX_ARM_ARCH__ < 7
2013 	if (ctx.imm_count)
2014 		kfree(ctx.imms);
2015 #endif
2016 out_off:
2017 	kfree(ctx.offsets);
2018 out:
2019 	if (tmp_blinded)
2020 		bpf_jit_prog_release_other(prog, prog == orig_prog ?
2021 					   tmp : orig_prog);
2022 	return prog;
2023 }
2024 
2025