1 /* 2 * linux/arch/arm/mm/mmu.c 3 * 4 * Copyright (C) 1995-2005 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/module.h> 11 #include <linux/kernel.h> 12 #include <linux/errno.h> 13 #include <linux/init.h> 14 #include <linux/mman.h> 15 #include <linux/nodemask.h> 16 #include <linux/memblock.h> 17 #include <linux/fs.h> 18 #include <linux/vmalloc.h> 19 #include <linux/sizes.h> 20 21 #include <asm/cp15.h> 22 #include <asm/cputype.h> 23 #include <asm/sections.h> 24 #include <asm/cachetype.h> 25 #include <asm/fixmap.h> 26 #include <asm/sections.h> 27 #include <asm/setup.h> 28 #include <asm/smp_plat.h> 29 #include <asm/tlb.h> 30 #include <asm/highmem.h> 31 #include <asm/system_info.h> 32 #include <asm/traps.h> 33 #include <asm/procinfo.h> 34 #include <asm/memory.h> 35 36 #include <asm/mach/arch.h> 37 #include <asm/mach/map.h> 38 #include <asm/mach/pci.h> 39 #include <asm/fixmap.h> 40 41 #include "mm.h" 42 #include "tcm.h" 43 44 /* 45 * empty_zero_page is a special page that is used for 46 * zero-initialized data and COW. 47 */ 48 struct page *empty_zero_page; 49 EXPORT_SYMBOL(empty_zero_page); 50 51 /* 52 * The pmd table for the upper-most set of pages. 53 */ 54 pmd_t *top_pmd; 55 56 #define CPOLICY_UNCACHED 0 57 #define CPOLICY_BUFFERED 1 58 #define CPOLICY_WRITETHROUGH 2 59 #define CPOLICY_WRITEBACK 3 60 #define CPOLICY_WRITEALLOC 4 61 62 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; 63 static unsigned int ecc_mask __initdata = 0; 64 pgprot_t pgprot_user; 65 pgprot_t pgprot_kernel; 66 pgprot_t pgprot_hyp_device; 67 pgprot_t pgprot_s2; 68 pgprot_t pgprot_s2_device; 69 70 EXPORT_SYMBOL(pgprot_user); 71 EXPORT_SYMBOL(pgprot_kernel); 72 73 struct cachepolicy { 74 const char policy[16]; 75 unsigned int cr_mask; 76 pmdval_t pmd; 77 pteval_t pte; 78 pteval_t pte_s2; 79 }; 80 81 #ifdef CONFIG_ARM_LPAE 82 #define s2_policy(policy) policy 83 #else 84 #define s2_policy(policy) 0 85 #endif 86 87 static struct cachepolicy cache_policies[] __initdata = { 88 { 89 .policy = "uncached", 90 .cr_mask = CR_W|CR_C, 91 .pmd = PMD_SECT_UNCACHED, 92 .pte = L_PTE_MT_UNCACHED, 93 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), 94 }, { 95 .policy = "buffered", 96 .cr_mask = CR_C, 97 .pmd = PMD_SECT_BUFFERED, 98 .pte = L_PTE_MT_BUFFERABLE, 99 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), 100 }, { 101 .policy = "writethrough", 102 .cr_mask = 0, 103 .pmd = PMD_SECT_WT, 104 .pte = L_PTE_MT_WRITETHROUGH, 105 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH), 106 }, { 107 .policy = "writeback", 108 .cr_mask = 0, 109 .pmd = PMD_SECT_WB, 110 .pte = L_PTE_MT_WRITEBACK, 111 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), 112 }, { 113 .policy = "writealloc", 114 .cr_mask = 0, 115 .pmd = PMD_SECT_WBWA, 116 .pte = L_PTE_MT_WRITEALLOC, 117 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), 118 } 119 }; 120 121 #ifdef CONFIG_CPU_CP15 122 static unsigned long initial_pmd_value __initdata = 0; 123 124 /* 125 * Initialise the cache_policy variable with the initial state specified 126 * via the "pmd" value. This is used to ensure that on ARMv6 and later, 127 * the C code sets the page tables up with the same policy as the head 128 * assembly code, which avoids an illegal state where the TLBs can get 129 * confused. See comments in early_cachepolicy() for more information. 130 */ 131 void __init init_default_cache_policy(unsigned long pmd) 132 { 133 int i; 134 135 initial_pmd_value = pmd; 136 137 pmd &= PMD_SECT_TEX(1) | PMD_SECT_BUFFERABLE | PMD_SECT_CACHEABLE; 138 139 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) 140 if (cache_policies[i].pmd == pmd) { 141 cachepolicy = i; 142 break; 143 } 144 145 if (i == ARRAY_SIZE(cache_policies)) 146 pr_err("ERROR: could not find cache policy\n"); 147 } 148 149 /* 150 * These are useful for identifying cache coherency problems by allowing 151 * the cache or the cache and writebuffer to be turned off. (Note: the 152 * write buffer should not be on and the cache off). 153 */ 154 static int __init early_cachepolicy(char *p) 155 { 156 int i, selected = -1; 157 158 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { 159 int len = strlen(cache_policies[i].policy); 160 161 if (memcmp(p, cache_policies[i].policy, len) == 0) { 162 selected = i; 163 break; 164 } 165 } 166 167 if (selected == -1) 168 pr_err("ERROR: unknown or unsupported cache policy\n"); 169 170 /* 171 * This restriction is partly to do with the way we boot; it is 172 * unpredictable to have memory mapped using two different sets of 173 * memory attributes (shared, type, and cache attribs). We can not 174 * change these attributes once the initial assembly has setup the 175 * page tables. 176 */ 177 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) { 178 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n", 179 cache_policies[cachepolicy].policy); 180 return 0; 181 } 182 183 if (selected != cachepolicy) { 184 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask); 185 cachepolicy = selected; 186 flush_cache_all(); 187 set_cr(cr); 188 } 189 return 0; 190 } 191 early_param("cachepolicy", early_cachepolicy); 192 193 static int __init early_nocache(char *__unused) 194 { 195 char *p = "buffered"; 196 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); 197 early_cachepolicy(p); 198 return 0; 199 } 200 early_param("nocache", early_nocache); 201 202 static int __init early_nowrite(char *__unused) 203 { 204 char *p = "uncached"; 205 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); 206 early_cachepolicy(p); 207 return 0; 208 } 209 early_param("nowb", early_nowrite); 210 211 #ifndef CONFIG_ARM_LPAE 212 static int __init early_ecc(char *p) 213 { 214 if (memcmp(p, "on", 2) == 0) 215 ecc_mask = PMD_PROTECTION; 216 else if (memcmp(p, "off", 3) == 0) 217 ecc_mask = 0; 218 return 0; 219 } 220 early_param("ecc", early_ecc); 221 #endif 222 223 #else /* ifdef CONFIG_CPU_CP15 */ 224 225 static int __init early_cachepolicy(char *p) 226 { 227 pr_warning("cachepolicy kernel parameter not supported without cp15\n"); 228 } 229 early_param("cachepolicy", early_cachepolicy); 230 231 static int __init noalign_setup(char *__unused) 232 { 233 pr_warning("noalign kernel parameter not supported without cp15\n"); 234 } 235 __setup("noalign", noalign_setup); 236 237 #endif /* ifdef CONFIG_CPU_CP15 / else */ 238 239 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN 240 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE 241 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE 242 243 static struct mem_type mem_types[] = { 244 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ 245 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | 246 L_PTE_SHARED, 247 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) | 248 s2_policy(L_PTE_S2_MT_DEV_SHARED) | 249 L_PTE_SHARED, 250 .prot_l1 = PMD_TYPE_TABLE, 251 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, 252 .domain = DOMAIN_IO, 253 }, 254 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ 255 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, 256 .prot_l1 = PMD_TYPE_TABLE, 257 .prot_sect = PROT_SECT_DEVICE, 258 .domain = DOMAIN_IO, 259 }, 260 [MT_DEVICE_CACHED] = { /* ioremap_cached */ 261 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, 262 .prot_l1 = PMD_TYPE_TABLE, 263 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, 264 .domain = DOMAIN_IO, 265 }, 266 [MT_DEVICE_WC] = { /* ioremap_wc */ 267 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, 268 .prot_l1 = PMD_TYPE_TABLE, 269 .prot_sect = PROT_SECT_DEVICE, 270 .domain = DOMAIN_IO, 271 }, 272 [MT_UNCACHED] = { 273 .prot_pte = PROT_PTE_DEVICE, 274 .prot_l1 = PMD_TYPE_TABLE, 275 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 276 .domain = DOMAIN_IO, 277 }, 278 [MT_CACHECLEAN] = { 279 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 280 .domain = DOMAIN_KERNEL, 281 }, 282 #ifndef CONFIG_ARM_LPAE 283 [MT_MINICLEAN] = { 284 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, 285 .domain = DOMAIN_KERNEL, 286 }, 287 #endif 288 [MT_LOW_VECTORS] = { 289 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 290 L_PTE_RDONLY, 291 .prot_l1 = PMD_TYPE_TABLE, 292 .domain = DOMAIN_USER, 293 }, 294 [MT_HIGH_VECTORS] = { 295 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 296 L_PTE_USER | L_PTE_RDONLY, 297 .prot_l1 = PMD_TYPE_TABLE, 298 .domain = DOMAIN_USER, 299 }, 300 [MT_MEMORY_RWX] = { 301 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 302 .prot_l1 = PMD_TYPE_TABLE, 303 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 304 .domain = DOMAIN_KERNEL, 305 }, 306 [MT_MEMORY_RW] = { 307 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 308 L_PTE_XN, 309 .prot_l1 = PMD_TYPE_TABLE, 310 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 311 .domain = DOMAIN_KERNEL, 312 }, 313 [MT_ROM] = { 314 .prot_sect = PMD_TYPE_SECT, 315 .domain = DOMAIN_KERNEL, 316 }, 317 [MT_MEMORY_RWX_NONCACHED] = { 318 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 319 L_PTE_MT_BUFFERABLE, 320 .prot_l1 = PMD_TYPE_TABLE, 321 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 322 .domain = DOMAIN_KERNEL, 323 }, 324 [MT_MEMORY_RW_DTCM] = { 325 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 326 L_PTE_XN, 327 .prot_l1 = PMD_TYPE_TABLE, 328 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 329 .domain = DOMAIN_KERNEL, 330 }, 331 [MT_MEMORY_RWX_ITCM] = { 332 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 333 .prot_l1 = PMD_TYPE_TABLE, 334 .domain = DOMAIN_KERNEL, 335 }, 336 [MT_MEMORY_RW_SO] = { 337 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 338 L_PTE_MT_UNCACHED | L_PTE_XN, 339 .prot_l1 = PMD_TYPE_TABLE, 340 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | 341 PMD_SECT_UNCACHED | PMD_SECT_XN, 342 .domain = DOMAIN_KERNEL, 343 }, 344 [MT_MEMORY_DMA_READY] = { 345 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 346 L_PTE_XN, 347 .prot_l1 = PMD_TYPE_TABLE, 348 .domain = DOMAIN_KERNEL, 349 }, 350 }; 351 352 const struct mem_type *get_mem_type(unsigned int type) 353 { 354 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; 355 } 356 EXPORT_SYMBOL(get_mem_type); 357 358 #define PTE_SET_FN(_name, pteop) \ 359 static int pte_set_##_name(pte_t *ptep, pgtable_t token, unsigned long addr, \ 360 void *data) \ 361 { \ 362 pte_t pte = pteop(*ptep); \ 363 \ 364 set_pte_ext(ptep, pte, 0); \ 365 return 0; \ 366 } \ 367 368 #define SET_MEMORY_FN(_name, callback) \ 369 int set_memory_##_name(unsigned long addr, int numpages) \ 370 { \ 371 unsigned long start = addr; \ 372 unsigned long size = PAGE_SIZE*numpages; \ 373 unsigned end = start + size; \ 374 \ 375 if (start < MODULES_VADDR || start >= MODULES_END) \ 376 return -EINVAL;\ 377 \ 378 if (end < MODULES_VADDR || end >= MODULES_END) \ 379 return -EINVAL; \ 380 \ 381 apply_to_page_range(&init_mm, start, size, callback, NULL); \ 382 flush_tlb_kernel_range(start, end); \ 383 return 0;\ 384 } 385 386 PTE_SET_FN(ro, pte_wrprotect) 387 PTE_SET_FN(rw, pte_mkwrite) 388 PTE_SET_FN(x, pte_mkexec) 389 PTE_SET_FN(nx, pte_mknexec) 390 391 SET_MEMORY_FN(ro, pte_set_ro) 392 SET_MEMORY_FN(rw, pte_set_rw) 393 SET_MEMORY_FN(x, pte_set_x) 394 SET_MEMORY_FN(nx, pte_set_nx) 395 396 /* 397 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range(). 398 * As a result, this can only be called with preemption disabled, as under 399 * stop_machine(). 400 */ 401 void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) 402 { 403 unsigned long vaddr = __fix_to_virt(idx); 404 pte_t *pte = pte_offset_kernel(pmd_off_k(vaddr), vaddr); 405 406 /* Make sure fixmap region does not exceed available allocation. */ 407 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) > 408 FIXADDR_END); 409 BUG_ON(idx >= __end_of_fixed_addresses); 410 411 if (pgprot_val(prot)) 412 set_pte_at(NULL, vaddr, pte, 413 pfn_pte(phys >> PAGE_SHIFT, prot)); 414 else 415 pte_clear(NULL, vaddr, pte); 416 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE); 417 } 418 419 /* 420 * Adjust the PMD section entries according to the CPU in use. 421 */ 422 static void __init build_mem_type_table(void) 423 { 424 struct cachepolicy *cp; 425 unsigned int cr = get_cr(); 426 pteval_t user_pgprot, kern_pgprot, vecs_pgprot; 427 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot; 428 int cpu_arch = cpu_architecture(); 429 int i; 430 431 if (cpu_arch < CPU_ARCH_ARMv6) { 432 #if defined(CONFIG_CPU_DCACHE_DISABLE) 433 if (cachepolicy > CPOLICY_BUFFERED) 434 cachepolicy = CPOLICY_BUFFERED; 435 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) 436 if (cachepolicy > CPOLICY_WRITETHROUGH) 437 cachepolicy = CPOLICY_WRITETHROUGH; 438 #endif 439 } 440 if (cpu_arch < CPU_ARCH_ARMv5) { 441 if (cachepolicy >= CPOLICY_WRITEALLOC) 442 cachepolicy = CPOLICY_WRITEBACK; 443 ecc_mask = 0; 444 } 445 446 if (is_smp()) { 447 if (cachepolicy != CPOLICY_WRITEALLOC) { 448 pr_warn("Forcing write-allocate cache policy for SMP\n"); 449 cachepolicy = CPOLICY_WRITEALLOC; 450 } 451 if (!(initial_pmd_value & PMD_SECT_S)) { 452 pr_warn("Forcing shared mappings for SMP\n"); 453 initial_pmd_value |= PMD_SECT_S; 454 } 455 } 456 457 /* 458 * Strip out features not present on earlier architectures. 459 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those 460 * without extended page tables don't have the 'Shared' bit. 461 */ 462 if (cpu_arch < CPU_ARCH_ARMv5) 463 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 464 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); 465 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) 466 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 467 mem_types[i].prot_sect &= ~PMD_SECT_S; 468 469 /* 470 * ARMv5 and lower, bit 4 must be set for page tables (was: cache 471 * "update-able on write" bit on ARM610). However, Xscale and 472 * Xscale3 require this bit to be cleared. 473 */ 474 if (cpu_is_xscale() || cpu_is_xsc3()) { 475 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 476 mem_types[i].prot_sect &= ~PMD_BIT4; 477 mem_types[i].prot_l1 &= ~PMD_BIT4; 478 } 479 } else if (cpu_arch < CPU_ARCH_ARMv6) { 480 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 481 if (mem_types[i].prot_l1) 482 mem_types[i].prot_l1 |= PMD_BIT4; 483 if (mem_types[i].prot_sect) 484 mem_types[i].prot_sect |= PMD_BIT4; 485 } 486 } 487 488 /* 489 * Mark the device areas according to the CPU/architecture. 490 */ 491 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { 492 if (!cpu_is_xsc3()) { 493 /* 494 * Mark device regions on ARMv6+ as execute-never 495 * to prevent speculative instruction fetches. 496 */ 497 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; 498 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; 499 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; 500 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; 501 502 /* Also setup NX memory mapping */ 503 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN; 504 } 505 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 506 /* 507 * For ARMv7 with TEX remapping, 508 * - shared device is SXCB=1100 509 * - nonshared device is SXCB=0100 510 * - write combine device mem is SXCB=0001 511 * (Uncached Normal memory) 512 */ 513 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); 514 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); 515 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 516 } else if (cpu_is_xsc3()) { 517 /* 518 * For Xscale3, 519 * - shared device is TEXCB=00101 520 * - nonshared device is TEXCB=01000 521 * - write combine device mem is TEXCB=00100 522 * (Inner/Outer Uncacheable in xsc3 parlance) 523 */ 524 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; 525 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 526 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 527 } else { 528 /* 529 * For ARMv6 and ARMv7 without TEX remapping, 530 * - shared device is TEXCB=00001 531 * - nonshared device is TEXCB=01000 532 * - write combine device mem is TEXCB=00100 533 * (Uncached Normal in ARMv6 parlance). 534 */ 535 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 536 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 537 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 538 } 539 } else { 540 /* 541 * On others, write combining is "Uncached/Buffered" 542 */ 543 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 544 } 545 546 /* 547 * Now deal with the memory-type mappings 548 */ 549 cp = &cache_policies[cachepolicy]; 550 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; 551 s2_pgprot = cp->pte_s2; 552 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte; 553 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2; 554 555 /* 556 * We don't use domains on ARMv6 (since this causes problems with 557 * v6/v7 kernels), so we must use a separate memory type for user 558 * r/o, kernel r/w to map the vectors page. 559 */ 560 #ifndef CONFIG_ARM_LPAE 561 if (cpu_arch == CPU_ARCH_ARMv6) 562 vecs_pgprot |= L_PTE_MT_VECTORS; 563 #endif 564 565 /* 566 * ARMv6 and above have extended page tables. 567 */ 568 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { 569 #ifndef CONFIG_ARM_LPAE 570 /* 571 * Mark cache clean areas and XIP ROM read only 572 * from SVC mode and no access from userspace. 573 */ 574 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 575 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 576 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 577 #endif 578 579 /* 580 * If the initial page tables were created with the S bit 581 * set, then we need to do the same here for the same 582 * reasons given in early_cachepolicy(). 583 */ 584 if (initial_pmd_value & PMD_SECT_S) { 585 user_pgprot |= L_PTE_SHARED; 586 kern_pgprot |= L_PTE_SHARED; 587 vecs_pgprot |= L_PTE_SHARED; 588 s2_pgprot |= L_PTE_SHARED; 589 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; 590 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; 591 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; 592 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; 593 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S; 594 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED; 595 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S; 596 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED; 597 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; 598 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S; 599 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED; 600 } 601 } 602 603 /* 604 * Non-cacheable Normal - intended for memory areas that must 605 * not cause dirty cache line writebacks when used 606 */ 607 if (cpu_arch >= CPU_ARCH_ARMv6) { 608 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 609 /* Non-cacheable Normal is XCB = 001 */ 610 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= 611 PMD_SECT_BUFFERED; 612 } else { 613 /* For both ARMv6 and non-TEX-remapping ARMv7 */ 614 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= 615 PMD_SECT_TEX(1); 616 } 617 } else { 618 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; 619 } 620 621 #ifdef CONFIG_ARM_LPAE 622 /* 623 * Do not generate access flag faults for the kernel mappings. 624 */ 625 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 626 mem_types[i].prot_pte |= PTE_EXT_AF; 627 if (mem_types[i].prot_sect) 628 mem_types[i].prot_sect |= PMD_SECT_AF; 629 } 630 kern_pgprot |= PTE_EXT_AF; 631 vecs_pgprot |= PTE_EXT_AF; 632 #endif 633 634 for (i = 0; i < 16; i++) { 635 pteval_t v = pgprot_val(protection_map[i]); 636 protection_map[i] = __pgprot(v | user_pgprot); 637 } 638 639 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; 640 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; 641 642 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); 643 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | 644 L_PTE_DIRTY | kern_pgprot); 645 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot); 646 pgprot_s2_device = __pgprot(s2_device_pgprot); 647 pgprot_hyp_device = __pgprot(hyp_device_pgprot); 648 649 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; 650 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; 651 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd; 652 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; 653 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; 654 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; 655 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; 656 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; 657 mem_types[MT_ROM].prot_sect |= cp->pmd; 658 659 switch (cp->pmd) { 660 case PMD_SECT_WT: 661 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; 662 break; 663 case PMD_SECT_WB: 664 case PMD_SECT_WBWA: 665 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; 666 break; 667 } 668 pr_info("Memory policy: %sData cache %s\n", 669 ecc_mask ? "ECC enabled, " : "", cp->policy); 670 671 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 672 struct mem_type *t = &mem_types[i]; 673 if (t->prot_l1) 674 t->prot_l1 |= PMD_DOMAIN(t->domain); 675 if (t->prot_sect) 676 t->prot_sect |= PMD_DOMAIN(t->domain); 677 } 678 } 679 680 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 681 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 682 unsigned long size, pgprot_t vma_prot) 683 { 684 if (!pfn_valid(pfn)) 685 return pgprot_noncached(vma_prot); 686 else if (file->f_flags & O_SYNC) 687 return pgprot_writecombine(vma_prot); 688 return vma_prot; 689 } 690 EXPORT_SYMBOL(phys_mem_access_prot); 691 #endif 692 693 #define vectors_base() (vectors_high() ? 0xffff0000 : 0) 694 695 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) 696 { 697 void *ptr = __va(memblock_alloc(sz, align)); 698 memset(ptr, 0, sz); 699 return ptr; 700 } 701 702 static void __init *early_alloc(unsigned long sz) 703 { 704 return early_alloc_aligned(sz, sz); 705 } 706 707 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) 708 { 709 if (pmd_none(*pmd)) { 710 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); 711 __pmd_populate(pmd, __pa(pte), prot); 712 } 713 BUG_ON(pmd_bad(*pmd)); 714 return pte_offset_kernel(pmd, addr); 715 } 716 717 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, 718 unsigned long end, unsigned long pfn, 719 const struct mem_type *type) 720 { 721 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); 722 do { 723 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); 724 pfn++; 725 } while (pte++, addr += PAGE_SIZE, addr != end); 726 } 727 728 static void __init __map_init_section(pmd_t *pmd, unsigned long addr, 729 unsigned long end, phys_addr_t phys, 730 const struct mem_type *type) 731 { 732 pmd_t *p = pmd; 733 734 #ifndef CONFIG_ARM_LPAE 735 /* 736 * In classic MMU format, puds and pmds are folded in to 737 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a 738 * group of L1 entries making up one logical pointer to 739 * an L2 table (2MB), where as PMDs refer to the individual 740 * L1 entries (1MB). Hence increment to get the correct 741 * offset for odd 1MB sections. 742 * (See arch/arm/include/asm/pgtable-2level.h) 743 */ 744 if (addr & SECTION_SIZE) 745 pmd++; 746 #endif 747 do { 748 *pmd = __pmd(phys | type->prot_sect); 749 phys += SECTION_SIZE; 750 } while (pmd++, addr += SECTION_SIZE, addr != end); 751 752 flush_pmd_entry(p); 753 } 754 755 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, 756 unsigned long end, phys_addr_t phys, 757 const struct mem_type *type) 758 { 759 pmd_t *pmd = pmd_offset(pud, addr); 760 unsigned long next; 761 762 do { 763 /* 764 * With LPAE, we must loop over to map 765 * all the pmds for the given range. 766 */ 767 next = pmd_addr_end(addr, end); 768 769 /* 770 * Try a section mapping - addr, next and phys must all be 771 * aligned to a section boundary. 772 */ 773 if (type->prot_sect && 774 ((addr | next | phys) & ~SECTION_MASK) == 0) { 775 __map_init_section(pmd, addr, next, phys, type); 776 } else { 777 alloc_init_pte(pmd, addr, next, 778 __phys_to_pfn(phys), type); 779 } 780 781 phys += next - addr; 782 783 } while (pmd++, addr = next, addr != end); 784 } 785 786 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, 787 unsigned long end, phys_addr_t phys, 788 const struct mem_type *type) 789 { 790 pud_t *pud = pud_offset(pgd, addr); 791 unsigned long next; 792 793 do { 794 next = pud_addr_end(addr, end); 795 alloc_init_pmd(pud, addr, next, phys, type); 796 phys += next - addr; 797 } while (pud++, addr = next, addr != end); 798 } 799 800 #ifndef CONFIG_ARM_LPAE 801 static void __init create_36bit_mapping(struct map_desc *md, 802 const struct mem_type *type) 803 { 804 unsigned long addr, length, end; 805 phys_addr_t phys; 806 pgd_t *pgd; 807 808 addr = md->virtual; 809 phys = __pfn_to_phys(md->pfn); 810 length = PAGE_ALIGN(md->length); 811 812 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { 813 printk(KERN_ERR "MM: CPU does not support supersection " 814 "mapping for 0x%08llx at 0x%08lx\n", 815 (long long)__pfn_to_phys((u64)md->pfn), addr); 816 return; 817 } 818 819 /* N.B. ARMv6 supersections are only defined to work with domain 0. 820 * Since domain assignments can in fact be arbitrary, the 821 * 'domain == 0' check below is required to insure that ARMv6 822 * supersections are only allocated for domain 0 regardless 823 * of the actual domain assignments in use. 824 */ 825 if (type->domain) { 826 printk(KERN_ERR "MM: invalid domain in supersection " 827 "mapping for 0x%08llx at 0x%08lx\n", 828 (long long)__pfn_to_phys((u64)md->pfn), addr); 829 return; 830 } 831 832 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { 833 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" 834 " at 0x%08lx invalid alignment\n", 835 (long long)__pfn_to_phys((u64)md->pfn), addr); 836 return; 837 } 838 839 /* 840 * Shift bits [35:32] of address into bits [23:20] of PMD 841 * (See ARMv6 spec). 842 */ 843 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); 844 845 pgd = pgd_offset_k(addr); 846 end = addr + length; 847 do { 848 pud_t *pud = pud_offset(pgd, addr); 849 pmd_t *pmd = pmd_offset(pud, addr); 850 int i; 851 852 for (i = 0; i < 16; i++) 853 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); 854 855 addr += SUPERSECTION_SIZE; 856 phys += SUPERSECTION_SIZE; 857 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; 858 } while (addr != end); 859 } 860 #endif /* !CONFIG_ARM_LPAE */ 861 862 /* 863 * Create the page directory entries and any necessary 864 * page tables for the mapping specified by `md'. We 865 * are able to cope here with varying sizes and address 866 * offsets, and we take full advantage of sections and 867 * supersections. 868 */ 869 static void __init create_mapping(struct map_desc *md) 870 { 871 unsigned long addr, length, end; 872 phys_addr_t phys; 873 const struct mem_type *type; 874 pgd_t *pgd; 875 876 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { 877 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" 878 " at 0x%08lx in user region\n", 879 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 880 return; 881 } 882 883 if ((md->type == MT_DEVICE || md->type == MT_ROM) && 884 md->virtual >= PAGE_OFFSET && 885 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { 886 printk(KERN_WARNING "BUG: mapping for 0x%08llx" 887 " at 0x%08lx out of vmalloc space\n", 888 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 889 } 890 891 type = &mem_types[md->type]; 892 893 #ifndef CONFIG_ARM_LPAE 894 /* 895 * Catch 36-bit addresses 896 */ 897 if (md->pfn >= 0x100000) { 898 create_36bit_mapping(md, type); 899 return; 900 } 901 #endif 902 903 addr = md->virtual & PAGE_MASK; 904 phys = __pfn_to_phys(md->pfn); 905 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 906 907 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { 908 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " 909 "be mapped using pages, ignoring.\n", 910 (long long)__pfn_to_phys(md->pfn), addr); 911 return; 912 } 913 914 pgd = pgd_offset_k(addr); 915 end = addr + length; 916 do { 917 unsigned long next = pgd_addr_end(addr, end); 918 919 alloc_init_pud(pgd, addr, next, phys, type); 920 921 phys += next - addr; 922 addr = next; 923 } while (pgd++, addr != end); 924 } 925 926 /* 927 * Create the architecture specific mappings 928 */ 929 void __init iotable_init(struct map_desc *io_desc, int nr) 930 { 931 struct map_desc *md; 932 struct vm_struct *vm; 933 struct static_vm *svm; 934 935 if (!nr) 936 return; 937 938 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm)); 939 940 for (md = io_desc; nr; md++, nr--) { 941 create_mapping(md); 942 943 vm = &svm->vm; 944 vm->addr = (void *)(md->virtual & PAGE_MASK); 945 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 946 vm->phys_addr = __pfn_to_phys(md->pfn); 947 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 948 vm->flags |= VM_ARM_MTYPE(md->type); 949 vm->caller = iotable_init; 950 add_static_vm_early(svm++); 951 } 952 } 953 954 void __init vm_reserve_area_early(unsigned long addr, unsigned long size, 955 void *caller) 956 { 957 struct vm_struct *vm; 958 struct static_vm *svm; 959 960 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm)); 961 962 vm = &svm->vm; 963 vm->addr = (void *)addr; 964 vm->size = size; 965 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; 966 vm->caller = caller; 967 add_static_vm_early(svm); 968 } 969 970 #ifndef CONFIG_ARM_LPAE 971 972 /* 973 * The Linux PMD is made of two consecutive section entries covering 2MB 974 * (see definition in include/asm/pgtable-2level.h). However a call to 975 * create_mapping() may optimize static mappings by using individual 976 * 1MB section mappings. This leaves the actual PMD potentially half 977 * initialized if the top or bottom section entry isn't used, leaving it 978 * open to problems if a subsequent ioremap() or vmalloc() tries to use 979 * the virtual space left free by that unused section entry. 980 * 981 * Let's avoid the issue by inserting dummy vm entries covering the unused 982 * PMD halves once the static mappings are in place. 983 */ 984 985 static void __init pmd_empty_section_gap(unsigned long addr) 986 { 987 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); 988 } 989 990 static void __init fill_pmd_gaps(void) 991 { 992 struct static_vm *svm; 993 struct vm_struct *vm; 994 unsigned long addr, next = 0; 995 pmd_t *pmd; 996 997 list_for_each_entry(svm, &static_vmlist, list) { 998 vm = &svm->vm; 999 addr = (unsigned long)vm->addr; 1000 if (addr < next) 1001 continue; 1002 1003 /* 1004 * Check if this vm starts on an odd section boundary. 1005 * If so and the first section entry for this PMD is free 1006 * then we block the corresponding virtual address. 1007 */ 1008 if ((addr & ~PMD_MASK) == SECTION_SIZE) { 1009 pmd = pmd_off_k(addr); 1010 if (pmd_none(*pmd)) 1011 pmd_empty_section_gap(addr & PMD_MASK); 1012 } 1013 1014 /* 1015 * Then check if this vm ends on an odd section boundary. 1016 * If so and the second section entry for this PMD is empty 1017 * then we block the corresponding virtual address. 1018 */ 1019 addr += vm->size; 1020 if ((addr & ~PMD_MASK) == SECTION_SIZE) { 1021 pmd = pmd_off_k(addr) + 1; 1022 if (pmd_none(*pmd)) 1023 pmd_empty_section_gap(addr); 1024 } 1025 1026 /* no need to look at any vm entry until we hit the next PMD */ 1027 next = (addr + PMD_SIZE - 1) & PMD_MASK; 1028 } 1029 } 1030 1031 #else 1032 #define fill_pmd_gaps() do { } while (0) 1033 #endif 1034 1035 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) 1036 static void __init pci_reserve_io(void) 1037 { 1038 struct static_vm *svm; 1039 1040 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); 1041 if (svm) 1042 return; 1043 1044 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); 1045 } 1046 #else 1047 #define pci_reserve_io() do { } while (0) 1048 #endif 1049 1050 #ifdef CONFIG_DEBUG_LL 1051 void __init debug_ll_io_init(void) 1052 { 1053 struct map_desc map; 1054 1055 debug_ll_addr(&map.pfn, &map.virtual); 1056 if (!map.pfn || !map.virtual) 1057 return; 1058 map.pfn = __phys_to_pfn(map.pfn); 1059 map.virtual &= PAGE_MASK; 1060 map.length = PAGE_SIZE; 1061 map.type = MT_DEVICE; 1062 iotable_init(&map, 1); 1063 } 1064 #endif 1065 1066 static void * __initdata vmalloc_min = 1067 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); 1068 1069 /* 1070 * vmalloc=size forces the vmalloc area to be exactly 'size' 1071 * bytes. This can be used to increase (or decrease) the vmalloc 1072 * area - the default is 240m. 1073 */ 1074 static int __init early_vmalloc(char *arg) 1075 { 1076 unsigned long vmalloc_reserve = memparse(arg, NULL); 1077 1078 if (vmalloc_reserve < SZ_16M) { 1079 vmalloc_reserve = SZ_16M; 1080 printk(KERN_WARNING 1081 "vmalloc area too small, limiting to %luMB\n", 1082 vmalloc_reserve >> 20); 1083 } 1084 1085 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { 1086 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); 1087 printk(KERN_WARNING 1088 "vmalloc area is too big, limiting to %luMB\n", 1089 vmalloc_reserve >> 20); 1090 } 1091 1092 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); 1093 return 0; 1094 } 1095 early_param("vmalloc", early_vmalloc); 1096 1097 phys_addr_t arm_lowmem_limit __initdata = 0; 1098 1099 void __init sanity_check_meminfo(void) 1100 { 1101 phys_addr_t memblock_limit = 0; 1102 int highmem = 0; 1103 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1; 1104 struct memblock_region *reg; 1105 1106 for_each_memblock(memory, reg) { 1107 phys_addr_t block_start = reg->base; 1108 phys_addr_t block_end = reg->base + reg->size; 1109 phys_addr_t size_limit = reg->size; 1110 1111 if (reg->base >= vmalloc_limit) 1112 highmem = 1; 1113 else 1114 size_limit = vmalloc_limit - reg->base; 1115 1116 1117 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) { 1118 1119 if (highmem) { 1120 pr_notice("Ignoring RAM at %pa-%pa (!CONFIG_HIGHMEM)\n", 1121 &block_start, &block_end); 1122 memblock_remove(reg->base, reg->size); 1123 continue; 1124 } 1125 1126 if (reg->size > size_limit) { 1127 phys_addr_t overlap_size = reg->size - size_limit; 1128 1129 pr_notice("Truncating RAM at %pa-%pa to -%pa", 1130 &block_start, &block_end, &vmalloc_limit); 1131 memblock_remove(vmalloc_limit, overlap_size); 1132 block_end = vmalloc_limit; 1133 } 1134 } 1135 1136 if (!highmem) { 1137 if (block_end > arm_lowmem_limit) { 1138 if (reg->size > size_limit) 1139 arm_lowmem_limit = vmalloc_limit; 1140 else 1141 arm_lowmem_limit = block_end; 1142 } 1143 1144 /* 1145 * Find the first non-section-aligned page, and point 1146 * memblock_limit at it. This relies on rounding the 1147 * limit down to be section-aligned, which happens at 1148 * the end of this function. 1149 * 1150 * With this algorithm, the start or end of almost any 1151 * bank can be non-section-aligned. The only exception 1152 * is that the start of the bank 0 must be section- 1153 * aligned, since otherwise memory would need to be 1154 * allocated when mapping the start of bank 0, which 1155 * occurs before any free memory is mapped. 1156 */ 1157 if (!memblock_limit) { 1158 if (!IS_ALIGNED(block_start, SECTION_SIZE)) 1159 memblock_limit = block_start; 1160 else if (!IS_ALIGNED(block_end, SECTION_SIZE)) 1161 memblock_limit = arm_lowmem_limit; 1162 } 1163 1164 } 1165 } 1166 1167 high_memory = __va(arm_lowmem_limit - 1) + 1; 1168 1169 /* 1170 * Round the memblock limit down to a section size. This 1171 * helps to ensure that we will allocate memory from the 1172 * last full section, which should be mapped. 1173 */ 1174 if (memblock_limit) 1175 memblock_limit = round_down(memblock_limit, SECTION_SIZE); 1176 if (!memblock_limit) 1177 memblock_limit = arm_lowmem_limit; 1178 1179 memblock_set_current_limit(memblock_limit); 1180 } 1181 1182 static inline void prepare_page_table(void) 1183 { 1184 unsigned long addr; 1185 phys_addr_t end; 1186 1187 /* 1188 * Clear out all the mappings below the kernel image. 1189 */ 1190 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) 1191 pmd_clear(pmd_off_k(addr)); 1192 1193 #ifdef CONFIG_XIP_KERNEL 1194 /* The XIP kernel is mapped in the module area -- skip over it */ 1195 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; 1196 #endif 1197 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) 1198 pmd_clear(pmd_off_k(addr)); 1199 1200 /* 1201 * Find the end of the first block of lowmem. 1202 */ 1203 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; 1204 if (end >= arm_lowmem_limit) 1205 end = arm_lowmem_limit; 1206 1207 /* 1208 * Clear out all the kernel space mappings, except for the first 1209 * memory bank, up to the vmalloc region. 1210 */ 1211 for (addr = __phys_to_virt(end); 1212 addr < VMALLOC_START; addr += PMD_SIZE) 1213 pmd_clear(pmd_off_k(addr)); 1214 } 1215 1216 #ifdef CONFIG_ARM_LPAE 1217 /* the first page is reserved for pgd */ 1218 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ 1219 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) 1220 #else 1221 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) 1222 #endif 1223 1224 /* 1225 * Reserve the special regions of memory 1226 */ 1227 void __init arm_mm_memblock_reserve(void) 1228 { 1229 /* 1230 * Reserve the page tables. These are already in use, 1231 * and can only be in node 0. 1232 */ 1233 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); 1234 1235 #ifdef CONFIG_SA1111 1236 /* 1237 * Because of the SA1111 DMA bug, we want to preserve our 1238 * precious DMA-able memory... 1239 */ 1240 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); 1241 #endif 1242 } 1243 1244 /* 1245 * Set up the device mappings. Since we clear out the page tables for all 1246 * mappings above VMALLOC_START, we will remove any debug device mappings. 1247 * This means you have to be careful how you debug this function, or any 1248 * called function. This means you can't use any function or debugging 1249 * method which may touch any device, otherwise the kernel _will_ crash. 1250 */ 1251 static void __init devicemaps_init(const struct machine_desc *mdesc) 1252 { 1253 struct map_desc map; 1254 unsigned long addr; 1255 void *vectors; 1256 1257 /* 1258 * Allocate the vector page early. 1259 */ 1260 vectors = early_alloc(PAGE_SIZE * 2); 1261 1262 early_trap_init(vectors); 1263 1264 for (addr = VMALLOC_START; addr; addr += PMD_SIZE) 1265 pmd_clear(pmd_off_k(addr)); 1266 1267 /* 1268 * Map the kernel if it is XIP. 1269 * It is always first in the modulearea. 1270 */ 1271 #ifdef CONFIG_XIP_KERNEL 1272 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); 1273 map.virtual = MODULES_VADDR; 1274 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; 1275 map.type = MT_ROM; 1276 create_mapping(&map); 1277 #endif 1278 1279 /* 1280 * Map the cache flushing regions. 1281 */ 1282 #ifdef FLUSH_BASE 1283 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); 1284 map.virtual = FLUSH_BASE; 1285 map.length = SZ_1M; 1286 map.type = MT_CACHECLEAN; 1287 create_mapping(&map); 1288 #endif 1289 #ifdef FLUSH_BASE_MINICACHE 1290 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); 1291 map.virtual = FLUSH_BASE_MINICACHE; 1292 map.length = SZ_1M; 1293 map.type = MT_MINICLEAN; 1294 create_mapping(&map); 1295 #endif 1296 1297 /* 1298 * Create a mapping for the machine vectors at the high-vectors 1299 * location (0xffff0000). If we aren't using high-vectors, also 1300 * create a mapping at the low-vectors virtual address. 1301 */ 1302 map.pfn = __phys_to_pfn(virt_to_phys(vectors)); 1303 map.virtual = 0xffff0000; 1304 map.length = PAGE_SIZE; 1305 #ifdef CONFIG_KUSER_HELPERS 1306 map.type = MT_HIGH_VECTORS; 1307 #else 1308 map.type = MT_LOW_VECTORS; 1309 #endif 1310 create_mapping(&map); 1311 1312 if (!vectors_high()) { 1313 map.virtual = 0; 1314 map.length = PAGE_SIZE * 2; 1315 map.type = MT_LOW_VECTORS; 1316 create_mapping(&map); 1317 } 1318 1319 /* Now create a kernel read-only mapping */ 1320 map.pfn += 1; 1321 map.virtual = 0xffff0000 + PAGE_SIZE; 1322 map.length = PAGE_SIZE; 1323 map.type = MT_LOW_VECTORS; 1324 create_mapping(&map); 1325 1326 /* 1327 * Ask the machine support to map in the statically mapped devices. 1328 */ 1329 if (mdesc->map_io) 1330 mdesc->map_io(); 1331 else 1332 debug_ll_io_init(); 1333 fill_pmd_gaps(); 1334 1335 /* Reserve fixed i/o space in VMALLOC region */ 1336 pci_reserve_io(); 1337 1338 /* 1339 * Finally flush the caches and tlb to ensure that we're in a 1340 * consistent state wrt the writebuffer. This also ensures that 1341 * any write-allocated cache lines in the vector page are written 1342 * back. After this point, we can start to touch devices again. 1343 */ 1344 local_flush_tlb_all(); 1345 flush_cache_all(); 1346 } 1347 1348 static void __init kmap_init(void) 1349 { 1350 #ifdef CONFIG_HIGHMEM 1351 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), 1352 PKMAP_BASE, _PAGE_KERNEL_TABLE); 1353 #endif 1354 1355 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START, 1356 _PAGE_KERNEL_TABLE); 1357 } 1358 1359 static void __init map_lowmem(void) 1360 { 1361 struct memblock_region *reg; 1362 unsigned long kernel_x_start = round_down(__pa(_stext), SECTION_SIZE); 1363 unsigned long kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); 1364 1365 /* Map all the lowmem memory banks. */ 1366 for_each_memblock(memory, reg) { 1367 phys_addr_t start = reg->base; 1368 phys_addr_t end = start + reg->size; 1369 struct map_desc map; 1370 1371 if (end > arm_lowmem_limit) 1372 end = arm_lowmem_limit; 1373 if (start >= end) 1374 break; 1375 1376 if (end < kernel_x_start || start >= kernel_x_end) { 1377 map.pfn = __phys_to_pfn(start); 1378 map.virtual = __phys_to_virt(start); 1379 map.length = end - start; 1380 map.type = MT_MEMORY_RWX; 1381 1382 create_mapping(&map); 1383 } else { 1384 /* This better cover the entire kernel */ 1385 if (start < kernel_x_start) { 1386 map.pfn = __phys_to_pfn(start); 1387 map.virtual = __phys_to_virt(start); 1388 map.length = kernel_x_start - start; 1389 map.type = MT_MEMORY_RW; 1390 1391 create_mapping(&map); 1392 } 1393 1394 map.pfn = __phys_to_pfn(kernel_x_start); 1395 map.virtual = __phys_to_virt(kernel_x_start); 1396 map.length = kernel_x_end - kernel_x_start; 1397 map.type = MT_MEMORY_RWX; 1398 1399 create_mapping(&map); 1400 1401 if (kernel_x_end < end) { 1402 map.pfn = __phys_to_pfn(kernel_x_end); 1403 map.virtual = __phys_to_virt(kernel_x_end); 1404 map.length = end - kernel_x_end; 1405 map.type = MT_MEMORY_RW; 1406 1407 create_mapping(&map); 1408 } 1409 } 1410 } 1411 } 1412 1413 #ifdef CONFIG_ARM_LPAE 1414 /* 1415 * early_paging_init() recreates boot time page table setup, allowing machines 1416 * to switch over to a high (>4G) address space on LPAE systems 1417 */ 1418 void __init early_paging_init(const struct machine_desc *mdesc, 1419 struct proc_info_list *procinfo) 1420 { 1421 pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags; 1422 unsigned long map_start, map_end; 1423 pgd_t *pgd0, *pgdk; 1424 pud_t *pud0, *pudk, *pud_start; 1425 pmd_t *pmd0, *pmdk; 1426 phys_addr_t phys; 1427 int i; 1428 1429 if (!(mdesc->init_meminfo)) 1430 return; 1431 1432 /* remap kernel code and data */ 1433 map_start = init_mm.start_code & PMD_MASK; 1434 map_end = ALIGN(init_mm.brk, PMD_SIZE); 1435 1436 /* get a handle on things... */ 1437 pgd0 = pgd_offset_k(0); 1438 pud_start = pud0 = pud_offset(pgd0, 0); 1439 pmd0 = pmd_offset(pud0, 0); 1440 1441 pgdk = pgd_offset_k(map_start); 1442 pudk = pud_offset(pgdk, map_start); 1443 pmdk = pmd_offset(pudk, map_start); 1444 1445 mdesc->init_meminfo(); 1446 1447 /* Run the patch stub to update the constants */ 1448 fixup_pv_table(&__pv_table_begin, 1449 (&__pv_table_end - &__pv_table_begin) << 2); 1450 1451 /* 1452 * Cache cleaning operations for self-modifying code 1453 * We should clean the entries by MVA but running a 1454 * for loop over every pv_table entry pointer would 1455 * just complicate the code. 1456 */ 1457 flush_cache_louis(); 1458 dsb(ishst); 1459 isb(); 1460 1461 /* 1462 * FIXME: This code is not architecturally compliant: we modify 1463 * the mappings in-place, indeed while they are in use by this 1464 * very same code. This may lead to unpredictable behaviour of 1465 * the CPU. 1466 * 1467 * Even modifying the mappings in a separate page table does 1468 * not resolve this. 1469 * 1470 * The architecture strongly recommends that when a mapping is 1471 * changed, that it is changed by first going via an invalid 1472 * mapping and back to the new mapping. This is to ensure that 1473 * no TLB conflicts (caused by the TLB having more than one TLB 1474 * entry match a translation) can occur. However, doing that 1475 * here will result in unmapping the code we are running. 1476 */ 1477 pr_warn("WARNING: unsafe modification of in-place page tables - tainting kernel\n"); 1478 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1479 1480 /* 1481 * Remap level 1 table. This changes the physical addresses 1482 * used to refer to the level 2 page tables to the high 1483 * physical address alias, leaving everything else the same. 1484 */ 1485 for (i = 0; i < PTRS_PER_PGD; pud0++, i++) { 1486 set_pud(pud0, 1487 __pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER)); 1488 pmd0 += PTRS_PER_PMD; 1489 } 1490 1491 /* 1492 * Remap the level 2 table, pointing the mappings at the high 1493 * physical address alias of these pages. 1494 */ 1495 phys = __pa(map_start); 1496 do { 1497 *pmdk++ = __pmd(phys | pmdprot); 1498 phys += PMD_SIZE; 1499 } while (phys < map_end); 1500 1501 /* 1502 * Ensure that the above updates are flushed out of the cache. 1503 * This is not strictly correct; on a system where the caches 1504 * are coherent with each other, but the MMU page table walks 1505 * may not be coherent, flush_cache_all() may be a no-op, and 1506 * this will fail. 1507 */ 1508 flush_cache_all(); 1509 1510 /* 1511 * Re-write the TTBR values to point them at the high physical 1512 * alias of the page tables. We expect __va() will work on 1513 * cpu_get_pgd(), which returns the value of TTBR0. 1514 */ 1515 cpu_switch_mm(pgd0, &init_mm); 1516 cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET); 1517 1518 /* Finally flush any stale TLB values. */ 1519 local_flush_bp_all(); 1520 local_flush_tlb_all(); 1521 } 1522 1523 #else 1524 1525 void __init early_paging_init(const struct machine_desc *mdesc, 1526 struct proc_info_list *procinfo) 1527 { 1528 if (mdesc->init_meminfo) 1529 mdesc->init_meminfo(); 1530 } 1531 1532 #endif 1533 1534 /* 1535 * paging_init() sets up the page tables, initialises the zone memory 1536 * maps, and sets up the zero page, bad page and bad page tables. 1537 */ 1538 void __init paging_init(const struct machine_desc *mdesc) 1539 { 1540 void *zero_page; 1541 1542 build_mem_type_table(); 1543 prepare_page_table(); 1544 map_lowmem(); 1545 dma_contiguous_remap(); 1546 devicemaps_init(mdesc); 1547 kmap_init(); 1548 tcm_init(); 1549 1550 top_pmd = pmd_off_k(0xffff0000); 1551 1552 /* allocate the zero page. */ 1553 zero_page = early_alloc(PAGE_SIZE); 1554 1555 bootmem_init(); 1556 1557 empty_zero_page = virt_to_page(zero_page); 1558 __flush_dcache_page(NULL, empty_zero_page); 1559 } 1560