1 /* 2 * linux/arch/arm/mm/mmu.c 3 * 4 * Copyright (C) 1995-2005 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/module.h> 11 #include <linux/kernel.h> 12 #include <linux/errno.h> 13 #include <linux/init.h> 14 #include <linux/mman.h> 15 #include <linux/nodemask.h> 16 #include <linux/memblock.h> 17 #include <linux/fs.h> 18 #include <linux/vmalloc.h> 19 #include <linux/sizes.h> 20 21 #include <asm/cp15.h> 22 #include <asm/cputype.h> 23 #include <asm/sections.h> 24 #include <asm/cachetype.h> 25 #include <asm/setup.h> 26 #include <asm/smp_plat.h> 27 #include <asm/tlb.h> 28 #include <asm/highmem.h> 29 #include <asm/system_info.h> 30 #include <asm/traps.h> 31 32 #include <asm/mach/arch.h> 33 #include <asm/mach/map.h> 34 #include <asm/mach/pci.h> 35 36 #include "mm.h" 37 #include "tcm.h" 38 39 /* 40 * empty_zero_page is a special page that is used for 41 * zero-initialized data and COW. 42 */ 43 struct page *empty_zero_page; 44 EXPORT_SYMBOL(empty_zero_page); 45 46 /* 47 * The pmd table for the upper-most set of pages. 48 */ 49 pmd_t *top_pmd; 50 51 #define CPOLICY_UNCACHED 0 52 #define CPOLICY_BUFFERED 1 53 #define CPOLICY_WRITETHROUGH 2 54 #define CPOLICY_WRITEBACK 3 55 #define CPOLICY_WRITEALLOC 4 56 57 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; 58 static unsigned int ecc_mask __initdata = 0; 59 pgprot_t pgprot_user; 60 pgprot_t pgprot_kernel; 61 pgprot_t pgprot_hyp_device; 62 pgprot_t pgprot_s2; 63 pgprot_t pgprot_s2_device; 64 65 EXPORT_SYMBOL(pgprot_user); 66 EXPORT_SYMBOL(pgprot_kernel); 67 68 struct cachepolicy { 69 const char policy[16]; 70 unsigned int cr_mask; 71 pmdval_t pmd; 72 pteval_t pte; 73 pteval_t pte_s2; 74 }; 75 76 #ifdef CONFIG_ARM_LPAE 77 #define s2_policy(policy) policy 78 #else 79 #define s2_policy(policy) 0 80 #endif 81 82 static struct cachepolicy cache_policies[] __initdata = { 83 { 84 .policy = "uncached", 85 .cr_mask = CR_W|CR_C, 86 .pmd = PMD_SECT_UNCACHED, 87 .pte = L_PTE_MT_UNCACHED, 88 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), 89 }, { 90 .policy = "buffered", 91 .cr_mask = CR_C, 92 .pmd = PMD_SECT_BUFFERED, 93 .pte = L_PTE_MT_BUFFERABLE, 94 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), 95 }, { 96 .policy = "writethrough", 97 .cr_mask = 0, 98 .pmd = PMD_SECT_WT, 99 .pte = L_PTE_MT_WRITETHROUGH, 100 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH), 101 }, { 102 .policy = "writeback", 103 .cr_mask = 0, 104 .pmd = PMD_SECT_WB, 105 .pte = L_PTE_MT_WRITEBACK, 106 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), 107 }, { 108 .policy = "writealloc", 109 .cr_mask = 0, 110 .pmd = PMD_SECT_WBWA, 111 .pte = L_PTE_MT_WRITEALLOC, 112 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), 113 } 114 }; 115 116 #ifdef CONFIG_CPU_CP15 117 /* 118 * These are useful for identifying cache coherency 119 * problems by allowing the cache or the cache and 120 * writebuffer to be turned off. (Note: the write 121 * buffer should not be on and the cache off). 122 */ 123 static int __init early_cachepolicy(char *p) 124 { 125 int i; 126 127 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { 128 int len = strlen(cache_policies[i].policy); 129 130 if (memcmp(p, cache_policies[i].policy, len) == 0) { 131 cachepolicy = i; 132 cr_alignment &= ~cache_policies[i].cr_mask; 133 cr_no_alignment &= ~cache_policies[i].cr_mask; 134 break; 135 } 136 } 137 if (i == ARRAY_SIZE(cache_policies)) 138 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); 139 /* 140 * This restriction is partly to do with the way we boot; it is 141 * unpredictable to have memory mapped using two different sets of 142 * memory attributes (shared, type, and cache attribs). We can not 143 * change these attributes once the initial assembly has setup the 144 * page tables. 145 */ 146 if (cpu_architecture() >= CPU_ARCH_ARMv6) { 147 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); 148 cachepolicy = CPOLICY_WRITEBACK; 149 } 150 flush_cache_all(); 151 set_cr(cr_alignment); 152 return 0; 153 } 154 early_param("cachepolicy", early_cachepolicy); 155 156 static int __init early_nocache(char *__unused) 157 { 158 char *p = "buffered"; 159 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); 160 early_cachepolicy(p); 161 return 0; 162 } 163 early_param("nocache", early_nocache); 164 165 static int __init early_nowrite(char *__unused) 166 { 167 char *p = "uncached"; 168 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); 169 early_cachepolicy(p); 170 return 0; 171 } 172 early_param("nowb", early_nowrite); 173 174 #ifndef CONFIG_ARM_LPAE 175 static int __init early_ecc(char *p) 176 { 177 if (memcmp(p, "on", 2) == 0) 178 ecc_mask = PMD_PROTECTION; 179 else if (memcmp(p, "off", 3) == 0) 180 ecc_mask = 0; 181 return 0; 182 } 183 early_param("ecc", early_ecc); 184 #endif 185 186 static int __init noalign_setup(char *__unused) 187 { 188 cr_alignment &= ~CR_A; 189 cr_no_alignment &= ~CR_A; 190 set_cr(cr_alignment); 191 return 1; 192 } 193 __setup("noalign", noalign_setup); 194 195 #ifndef CONFIG_SMP 196 void adjust_cr(unsigned long mask, unsigned long set) 197 { 198 unsigned long flags; 199 200 mask &= ~CR_A; 201 202 set &= mask; 203 204 local_irq_save(flags); 205 206 cr_no_alignment = (cr_no_alignment & ~mask) | set; 207 cr_alignment = (cr_alignment & ~mask) | set; 208 209 set_cr((get_cr() & ~mask) | set); 210 211 local_irq_restore(flags); 212 } 213 #endif 214 215 #else /* ifdef CONFIG_CPU_CP15 */ 216 217 static int __init early_cachepolicy(char *p) 218 { 219 pr_warning("cachepolicy kernel parameter not supported without cp15\n"); 220 } 221 early_param("cachepolicy", early_cachepolicy); 222 223 static int __init noalign_setup(char *__unused) 224 { 225 pr_warning("noalign kernel parameter not supported without cp15\n"); 226 } 227 __setup("noalign", noalign_setup); 228 229 #endif /* ifdef CONFIG_CPU_CP15 / else */ 230 231 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN 232 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE 233 234 static struct mem_type mem_types[] = { 235 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ 236 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | 237 L_PTE_SHARED, 238 .prot_l1 = PMD_TYPE_TABLE, 239 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, 240 .domain = DOMAIN_IO, 241 }, 242 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ 243 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, 244 .prot_l1 = PMD_TYPE_TABLE, 245 .prot_sect = PROT_SECT_DEVICE, 246 .domain = DOMAIN_IO, 247 }, 248 [MT_DEVICE_CACHED] = { /* ioremap_cached */ 249 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, 250 .prot_l1 = PMD_TYPE_TABLE, 251 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, 252 .domain = DOMAIN_IO, 253 }, 254 [MT_DEVICE_WC] = { /* ioremap_wc */ 255 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, 256 .prot_l1 = PMD_TYPE_TABLE, 257 .prot_sect = PROT_SECT_DEVICE, 258 .domain = DOMAIN_IO, 259 }, 260 [MT_UNCACHED] = { 261 .prot_pte = PROT_PTE_DEVICE, 262 .prot_l1 = PMD_TYPE_TABLE, 263 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 264 .domain = DOMAIN_IO, 265 }, 266 [MT_CACHECLEAN] = { 267 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 268 .domain = DOMAIN_KERNEL, 269 }, 270 #ifndef CONFIG_ARM_LPAE 271 [MT_MINICLEAN] = { 272 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, 273 .domain = DOMAIN_KERNEL, 274 }, 275 #endif 276 [MT_LOW_VECTORS] = { 277 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 278 L_PTE_RDONLY, 279 .prot_l1 = PMD_TYPE_TABLE, 280 .domain = DOMAIN_USER, 281 }, 282 [MT_HIGH_VECTORS] = { 283 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 284 L_PTE_USER | L_PTE_RDONLY, 285 .prot_l1 = PMD_TYPE_TABLE, 286 .domain = DOMAIN_USER, 287 }, 288 [MT_MEMORY] = { 289 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 290 .prot_l1 = PMD_TYPE_TABLE, 291 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 292 .domain = DOMAIN_KERNEL, 293 }, 294 [MT_ROM] = { 295 .prot_sect = PMD_TYPE_SECT, 296 .domain = DOMAIN_KERNEL, 297 }, 298 [MT_MEMORY_NONCACHED] = { 299 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 300 L_PTE_MT_BUFFERABLE, 301 .prot_l1 = PMD_TYPE_TABLE, 302 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 303 .domain = DOMAIN_KERNEL, 304 }, 305 [MT_MEMORY_DTCM] = { 306 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 307 L_PTE_XN, 308 .prot_l1 = PMD_TYPE_TABLE, 309 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 310 .domain = DOMAIN_KERNEL, 311 }, 312 [MT_MEMORY_ITCM] = { 313 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 314 .prot_l1 = PMD_TYPE_TABLE, 315 .domain = DOMAIN_KERNEL, 316 }, 317 [MT_MEMORY_SO] = { 318 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 319 L_PTE_MT_UNCACHED | L_PTE_XN, 320 .prot_l1 = PMD_TYPE_TABLE, 321 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | 322 PMD_SECT_UNCACHED | PMD_SECT_XN, 323 .domain = DOMAIN_KERNEL, 324 }, 325 [MT_MEMORY_DMA_READY] = { 326 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 327 .prot_l1 = PMD_TYPE_TABLE, 328 .domain = DOMAIN_KERNEL, 329 }, 330 }; 331 332 const struct mem_type *get_mem_type(unsigned int type) 333 { 334 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; 335 } 336 EXPORT_SYMBOL(get_mem_type); 337 338 /* 339 * Adjust the PMD section entries according to the CPU in use. 340 */ 341 static void __init build_mem_type_table(void) 342 { 343 struct cachepolicy *cp; 344 unsigned int cr = get_cr(); 345 pteval_t user_pgprot, kern_pgprot, vecs_pgprot; 346 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot; 347 int cpu_arch = cpu_architecture(); 348 int i; 349 350 if (cpu_arch < CPU_ARCH_ARMv6) { 351 #if defined(CONFIG_CPU_DCACHE_DISABLE) 352 if (cachepolicy > CPOLICY_BUFFERED) 353 cachepolicy = CPOLICY_BUFFERED; 354 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) 355 if (cachepolicy > CPOLICY_WRITETHROUGH) 356 cachepolicy = CPOLICY_WRITETHROUGH; 357 #endif 358 } 359 if (cpu_arch < CPU_ARCH_ARMv5) { 360 if (cachepolicy >= CPOLICY_WRITEALLOC) 361 cachepolicy = CPOLICY_WRITEBACK; 362 ecc_mask = 0; 363 } 364 if (is_smp()) 365 cachepolicy = CPOLICY_WRITEALLOC; 366 367 /* 368 * Strip out features not present on earlier architectures. 369 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those 370 * without extended page tables don't have the 'Shared' bit. 371 */ 372 if (cpu_arch < CPU_ARCH_ARMv5) 373 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 374 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); 375 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) 376 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 377 mem_types[i].prot_sect &= ~PMD_SECT_S; 378 379 /* 380 * ARMv5 and lower, bit 4 must be set for page tables (was: cache 381 * "update-able on write" bit on ARM610). However, Xscale and 382 * Xscale3 require this bit to be cleared. 383 */ 384 if (cpu_is_xscale() || cpu_is_xsc3()) { 385 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 386 mem_types[i].prot_sect &= ~PMD_BIT4; 387 mem_types[i].prot_l1 &= ~PMD_BIT4; 388 } 389 } else if (cpu_arch < CPU_ARCH_ARMv6) { 390 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 391 if (mem_types[i].prot_l1) 392 mem_types[i].prot_l1 |= PMD_BIT4; 393 if (mem_types[i].prot_sect) 394 mem_types[i].prot_sect |= PMD_BIT4; 395 } 396 } 397 398 /* 399 * Mark the device areas according to the CPU/architecture. 400 */ 401 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { 402 if (!cpu_is_xsc3()) { 403 /* 404 * Mark device regions on ARMv6+ as execute-never 405 * to prevent speculative instruction fetches. 406 */ 407 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; 408 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; 409 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; 410 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; 411 } 412 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 413 /* 414 * For ARMv7 with TEX remapping, 415 * - shared device is SXCB=1100 416 * - nonshared device is SXCB=0100 417 * - write combine device mem is SXCB=0001 418 * (Uncached Normal memory) 419 */ 420 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); 421 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); 422 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 423 } else if (cpu_is_xsc3()) { 424 /* 425 * For Xscale3, 426 * - shared device is TEXCB=00101 427 * - nonshared device is TEXCB=01000 428 * - write combine device mem is TEXCB=00100 429 * (Inner/Outer Uncacheable in xsc3 parlance) 430 */ 431 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; 432 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 433 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 434 } else { 435 /* 436 * For ARMv6 and ARMv7 without TEX remapping, 437 * - shared device is TEXCB=00001 438 * - nonshared device is TEXCB=01000 439 * - write combine device mem is TEXCB=00100 440 * (Uncached Normal in ARMv6 parlance). 441 */ 442 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 443 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 444 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 445 } 446 } else { 447 /* 448 * On others, write combining is "Uncached/Buffered" 449 */ 450 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 451 } 452 453 /* 454 * Now deal with the memory-type mappings 455 */ 456 cp = &cache_policies[cachepolicy]; 457 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; 458 s2_pgprot = cp->pte_s2; 459 hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte; 460 461 /* 462 * ARMv6 and above have extended page tables. 463 */ 464 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { 465 #ifndef CONFIG_ARM_LPAE 466 /* 467 * Mark cache clean areas and XIP ROM read only 468 * from SVC mode and no access from userspace. 469 */ 470 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 471 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 472 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 473 #endif 474 475 if (is_smp()) { 476 /* 477 * Mark memory with the "shared" attribute 478 * for SMP systems 479 */ 480 user_pgprot |= L_PTE_SHARED; 481 kern_pgprot |= L_PTE_SHARED; 482 vecs_pgprot |= L_PTE_SHARED; 483 s2_pgprot |= L_PTE_SHARED; 484 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; 485 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; 486 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; 487 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; 488 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 489 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; 490 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; 491 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; 492 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; 493 } 494 } 495 496 /* 497 * Non-cacheable Normal - intended for memory areas that must 498 * not cause dirty cache line writebacks when used 499 */ 500 if (cpu_arch >= CPU_ARCH_ARMv6) { 501 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 502 /* Non-cacheable Normal is XCB = 001 */ 503 mem_types[MT_MEMORY_NONCACHED].prot_sect |= 504 PMD_SECT_BUFFERED; 505 } else { 506 /* For both ARMv6 and non-TEX-remapping ARMv7 */ 507 mem_types[MT_MEMORY_NONCACHED].prot_sect |= 508 PMD_SECT_TEX(1); 509 } 510 } else { 511 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; 512 } 513 514 #ifdef CONFIG_ARM_LPAE 515 /* 516 * Do not generate access flag faults for the kernel mappings. 517 */ 518 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 519 mem_types[i].prot_pte |= PTE_EXT_AF; 520 if (mem_types[i].prot_sect) 521 mem_types[i].prot_sect |= PMD_SECT_AF; 522 } 523 kern_pgprot |= PTE_EXT_AF; 524 vecs_pgprot |= PTE_EXT_AF; 525 #endif 526 527 for (i = 0; i < 16; i++) { 528 pteval_t v = pgprot_val(protection_map[i]); 529 protection_map[i] = __pgprot(v | user_pgprot); 530 } 531 532 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; 533 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; 534 535 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); 536 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | 537 L_PTE_DIRTY | kern_pgprot); 538 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot); 539 pgprot_s2_device = __pgprot(s2_device_pgprot); 540 pgprot_hyp_device = __pgprot(hyp_device_pgprot); 541 542 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; 543 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; 544 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; 545 mem_types[MT_MEMORY].prot_pte |= kern_pgprot; 546 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; 547 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; 548 mem_types[MT_ROM].prot_sect |= cp->pmd; 549 550 switch (cp->pmd) { 551 case PMD_SECT_WT: 552 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; 553 break; 554 case PMD_SECT_WB: 555 case PMD_SECT_WBWA: 556 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; 557 break; 558 } 559 printk("Memory policy: ECC %sabled, Data cache %s\n", 560 ecc_mask ? "en" : "dis", cp->policy); 561 562 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 563 struct mem_type *t = &mem_types[i]; 564 if (t->prot_l1) 565 t->prot_l1 |= PMD_DOMAIN(t->domain); 566 if (t->prot_sect) 567 t->prot_sect |= PMD_DOMAIN(t->domain); 568 } 569 } 570 571 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 572 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 573 unsigned long size, pgprot_t vma_prot) 574 { 575 if (!pfn_valid(pfn)) 576 return pgprot_noncached(vma_prot); 577 else if (file->f_flags & O_SYNC) 578 return pgprot_writecombine(vma_prot); 579 return vma_prot; 580 } 581 EXPORT_SYMBOL(phys_mem_access_prot); 582 #endif 583 584 #define vectors_base() (vectors_high() ? 0xffff0000 : 0) 585 586 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) 587 { 588 void *ptr = __va(memblock_alloc(sz, align)); 589 memset(ptr, 0, sz); 590 return ptr; 591 } 592 593 static void __init *early_alloc(unsigned long sz) 594 { 595 return early_alloc_aligned(sz, sz); 596 } 597 598 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) 599 { 600 if (pmd_none(*pmd)) { 601 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); 602 __pmd_populate(pmd, __pa(pte), prot); 603 } 604 BUG_ON(pmd_bad(*pmd)); 605 return pte_offset_kernel(pmd, addr); 606 } 607 608 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, 609 unsigned long end, unsigned long pfn, 610 const struct mem_type *type) 611 { 612 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); 613 do { 614 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); 615 pfn++; 616 } while (pte++, addr += PAGE_SIZE, addr != end); 617 } 618 619 static void __init map_init_section(pmd_t *pmd, unsigned long addr, 620 unsigned long end, phys_addr_t phys, 621 const struct mem_type *type) 622 { 623 #ifndef CONFIG_ARM_LPAE 624 /* 625 * In classic MMU format, puds and pmds are folded in to 626 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a 627 * group of L1 entries making up one logical pointer to 628 * an L2 table (2MB), where as PMDs refer to the individual 629 * L1 entries (1MB). Hence increment to get the correct 630 * offset for odd 1MB sections. 631 * (See arch/arm/include/asm/pgtable-2level.h) 632 */ 633 if (addr & SECTION_SIZE) 634 pmd++; 635 #endif 636 do { 637 *pmd = __pmd(phys | type->prot_sect); 638 phys += SECTION_SIZE; 639 } while (pmd++, addr += SECTION_SIZE, addr != end); 640 641 flush_pmd_entry(pmd); 642 } 643 644 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, 645 unsigned long end, phys_addr_t phys, 646 const struct mem_type *type) 647 { 648 pmd_t *pmd = pmd_offset(pud, addr); 649 unsigned long next; 650 651 do { 652 /* 653 * With LPAE, we must loop over to map 654 * all the pmds for the given range. 655 */ 656 next = pmd_addr_end(addr, end); 657 658 /* 659 * Try a section mapping - addr, next and phys must all be 660 * aligned to a section boundary. 661 */ 662 if (type->prot_sect && 663 ((addr | next | phys) & ~SECTION_MASK) == 0) { 664 map_init_section(pmd, addr, next, phys, type); 665 } else { 666 alloc_init_pte(pmd, addr, next, 667 __phys_to_pfn(phys), type); 668 } 669 670 phys += next - addr; 671 672 } while (pmd++, addr = next, addr != end); 673 } 674 675 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, 676 unsigned long end, unsigned long phys, const struct mem_type *type) 677 { 678 pud_t *pud = pud_offset(pgd, addr); 679 unsigned long next; 680 681 do { 682 next = pud_addr_end(addr, end); 683 alloc_init_pmd(pud, addr, next, phys, type); 684 phys += next - addr; 685 } while (pud++, addr = next, addr != end); 686 } 687 688 #ifndef CONFIG_ARM_LPAE 689 static void __init create_36bit_mapping(struct map_desc *md, 690 const struct mem_type *type) 691 { 692 unsigned long addr, length, end; 693 phys_addr_t phys; 694 pgd_t *pgd; 695 696 addr = md->virtual; 697 phys = __pfn_to_phys(md->pfn); 698 length = PAGE_ALIGN(md->length); 699 700 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { 701 printk(KERN_ERR "MM: CPU does not support supersection " 702 "mapping for 0x%08llx at 0x%08lx\n", 703 (long long)__pfn_to_phys((u64)md->pfn), addr); 704 return; 705 } 706 707 /* N.B. ARMv6 supersections are only defined to work with domain 0. 708 * Since domain assignments can in fact be arbitrary, the 709 * 'domain == 0' check below is required to insure that ARMv6 710 * supersections are only allocated for domain 0 regardless 711 * of the actual domain assignments in use. 712 */ 713 if (type->domain) { 714 printk(KERN_ERR "MM: invalid domain in supersection " 715 "mapping for 0x%08llx at 0x%08lx\n", 716 (long long)__pfn_to_phys((u64)md->pfn), addr); 717 return; 718 } 719 720 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { 721 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" 722 " at 0x%08lx invalid alignment\n", 723 (long long)__pfn_to_phys((u64)md->pfn), addr); 724 return; 725 } 726 727 /* 728 * Shift bits [35:32] of address into bits [23:20] of PMD 729 * (See ARMv6 spec). 730 */ 731 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); 732 733 pgd = pgd_offset_k(addr); 734 end = addr + length; 735 do { 736 pud_t *pud = pud_offset(pgd, addr); 737 pmd_t *pmd = pmd_offset(pud, addr); 738 int i; 739 740 for (i = 0; i < 16; i++) 741 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); 742 743 addr += SUPERSECTION_SIZE; 744 phys += SUPERSECTION_SIZE; 745 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; 746 } while (addr != end); 747 } 748 #endif /* !CONFIG_ARM_LPAE */ 749 750 /* 751 * Create the page directory entries and any necessary 752 * page tables for the mapping specified by `md'. We 753 * are able to cope here with varying sizes and address 754 * offsets, and we take full advantage of sections and 755 * supersections. 756 */ 757 static void __init create_mapping(struct map_desc *md) 758 { 759 unsigned long addr, length, end; 760 phys_addr_t phys; 761 const struct mem_type *type; 762 pgd_t *pgd; 763 764 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { 765 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" 766 " at 0x%08lx in user region\n", 767 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 768 return; 769 } 770 771 if ((md->type == MT_DEVICE || md->type == MT_ROM) && 772 md->virtual >= PAGE_OFFSET && 773 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { 774 printk(KERN_WARNING "BUG: mapping for 0x%08llx" 775 " at 0x%08lx out of vmalloc space\n", 776 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 777 } 778 779 type = &mem_types[md->type]; 780 781 #ifndef CONFIG_ARM_LPAE 782 /* 783 * Catch 36-bit addresses 784 */ 785 if (md->pfn >= 0x100000) { 786 create_36bit_mapping(md, type); 787 return; 788 } 789 #endif 790 791 addr = md->virtual & PAGE_MASK; 792 phys = __pfn_to_phys(md->pfn); 793 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 794 795 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { 796 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " 797 "be mapped using pages, ignoring.\n", 798 (long long)__pfn_to_phys(md->pfn), addr); 799 return; 800 } 801 802 pgd = pgd_offset_k(addr); 803 end = addr + length; 804 do { 805 unsigned long next = pgd_addr_end(addr, end); 806 807 alloc_init_pud(pgd, addr, next, phys, type); 808 809 phys += next - addr; 810 addr = next; 811 } while (pgd++, addr != end); 812 } 813 814 /* 815 * Create the architecture specific mappings 816 */ 817 void __init iotable_init(struct map_desc *io_desc, int nr) 818 { 819 struct map_desc *md; 820 struct vm_struct *vm; 821 struct static_vm *svm; 822 823 if (!nr) 824 return; 825 826 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm)); 827 828 for (md = io_desc; nr; md++, nr--) { 829 create_mapping(md); 830 831 vm = &svm->vm; 832 vm->addr = (void *)(md->virtual & PAGE_MASK); 833 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 834 vm->phys_addr = __pfn_to_phys(md->pfn); 835 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 836 vm->flags |= VM_ARM_MTYPE(md->type); 837 vm->caller = iotable_init; 838 add_static_vm_early(svm++); 839 } 840 } 841 842 void __init vm_reserve_area_early(unsigned long addr, unsigned long size, 843 void *caller) 844 { 845 struct vm_struct *vm; 846 struct static_vm *svm; 847 848 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm)); 849 850 vm = &svm->vm; 851 vm->addr = (void *)addr; 852 vm->size = size; 853 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; 854 vm->caller = caller; 855 add_static_vm_early(svm); 856 } 857 858 #ifndef CONFIG_ARM_LPAE 859 860 /* 861 * The Linux PMD is made of two consecutive section entries covering 2MB 862 * (see definition in include/asm/pgtable-2level.h). However a call to 863 * create_mapping() may optimize static mappings by using individual 864 * 1MB section mappings. This leaves the actual PMD potentially half 865 * initialized if the top or bottom section entry isn't used, leaving it 866 * open to problems if a subsequent ioremap() or vmalloc() tries to use 867 * the virtual space left free by that unused section entry. 868 * 869 * Let's avoid the issue by inserting dummy vm entries covering the unused 870 * PMD halves once the static mappings are in place. 871 */ 872 873 static void __init pmd_empty_section_gap(unsigned long addr) 874 { 875 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); 876 } 877 878 static void __init fill_pmd_gaps(void) 879 { 880 struct static_vm *svm; 881 struct vm_struct *vm; 882 unsigned long addr, next = 0; 883 pmd_t *pmd; 884 885 list_for_each_entry(svm, &static_vmlist, list) { 886 vm = &svm->vm; 887 addr = (unsigned long)vm->addr; 888 if (addr < next) 889 continue; 890 891 /* 892 * Check if this vm starts on an odd section boundary. 893 * If so and the first section entry for this PMD is free 894 * then we block the corresponding virtual address. 895 */ 896 if ((addr & ~PMD_MASK) == SECTION_SIZE) { 897 pmd = pmd_off_k(addr); 898 if (pmd_none(*pmd)) 899 pmd_empty_section_gap(addr & PMD_MASK); 900 } 901 902 /* 903 * Then check if this vm ends on an odd section boundary. 904 * If so and the second section entry for this PMD is empty 905 * then we block the corresponding virtual address. 906 */ 907 addr += vm->size; 908 if ((addr & ~PMD_MASK) == SECTION_SIZE) { 909 pmd = pmd_off_k(addr) + 1; 910 if (pmd_none(*pmd)) 911 pmd_empty_section_gap(addr); 912 } 913 914 /* no need to look at any vm entry until we hit the next PMD */ 915 next = (addr + PMD_SIZE - 1) & PMD_MASK; 916 } 917 } 918 919 #else 920 #define fill_pmd_gaps() do { } while (0) 921 #endif 922 923 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) 924 static void __init pci_reserve_io(void) 925 { 926 struct static_vm *svm; 927 928 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); 929 if (svm) 930 return; 931 932 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); 933 } 934 #else 935 #define pci_reserve_io() do { } while (0) 936 #endif 937 938 #ifdef CONFIG_DEBUG_LL 939 void __init debug_ll_io_init(void) 940 { 941 struct map_desc map; 942 943 debug_ll_addr(&map.pfn, &map.virtual); 944 if (!map.pfn || !map.virtual) 945 return; 946 map.pfn = __phys_to_pfn(map.pfn); 947 map.virtual &= PAGE_MASK; 948 map.length = PAGE_SIZE; 949 map.type = MT_DEVICE; 950 create_mapping(&map); 951 } 952 #endif 953 954 static void * __initdata vmalloc_min = 955 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); 956 957 /* 958 * vmalloc=size forces the vmalloc area to be exactly 'size' 959 * bytes. This can be used to increase (or decrease) the vmalloc 960 * area - the default is 240m. 961 */ 962 static int __init early_vmalloc(char *arg) 963 { 964 unsigned long vmalloc_reserve = memparse(arg, NULL); 965 966 if (vmalloc_reserve < SZ_16M) { 967 vmalloc_reserve = SZ_16M; 968 printk(KERN_WARNING 969 "vmalloc area too small, limiting to %luMB\n", 970 vmalloc_reserve >> 20); 971 } 972 973 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { 974 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); 975 printk(KERN_WARNING 976 "vmalloc area is too big, limiting to %luMB\n", 977 vmalloc_reserve >> 20); 978 } 979 980 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); 981 return 0; 982 } 983 early_param("vmalloc", early_vmalloc); 984 985 phys_addr_t arm_lowmem_limit __initdata = 0; 986 987 void __init sanity_check_meminfo(void) 988 { 989 int i, j, highmem = 0; 990 991 for (i = 0, j = 0; i < meminfo.nr_banks; i++) { 992 struct membank *bank = &meminfo.bank[j]; 993 *bank = meminfo.bank[i]; 994 995 if (bank->start > ULONG_MAX) 996 highmem = 1; 997 998 #ifdef CONFIG_HIGHMEM 999 if (__va(bank->start) >= vmalloc_min || 1000 __va(bank->start) < (void *)PAGE_OFFSET) 1001 highmem = 1; 1002 1003 bank->highmem = highmem; 1004 1005 /* 1006 * Split those memory banks which are partially overlapping 1007 * the vmalloc area greatly simplifying things later. 1008 */ 1009 if (!highmem && __va(bank->start) < vmalloc_min && 1010 bank->size > vmalloc_min - __va(bank->start)) { 1011 if (meminfo.nr_banks >= NR_BANKS) { 1012 printk(KERN_CRIT "NR_BANKS too low, " 1013 "ignoring high memory\n"); 1014 } else { 1015 memmove(bank + 1, bank, 1016 (meminfo.nr_banks - i) * sizeof(*bank)); 1017 meminfo.nr_banks++; 1018 i++; 1019 bank[1].size -= vmalloc_min - __va(bank->start); 1020 bank[1].start = __pa(vmalloc_min - 1) + 1; 1021 bank[1].highmem = highmem = 1; 1022 j++; 1023 } 1024 bank->size = vmalloc_min - __va(bank->start); 1025 } 1026 #else 1027 bank->highmem = highmem; 1028 1029 /* 1030 * Highmem banks not allowed with !CONFIG_HIGHMEM. 1031 */ 1032 if (highmem) { 1033 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " 1034 "(!CONFIG_HIGHMEM).\n", 1035 (unsigned long long)bank->start, 1036 (unsigned long long)bank->start + bank->size - 1); 1037 continue; 1038 } 1039 1040 /* 1041 * Check whether this memory bank would entirely overlap 1042 * the vmalloc area. 1043 */ 1044 if (__va(bank->start) >= vmalloc_min || 1045 __va(bank->start) < (void *)PAGE_OFFSET) { 1046 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " 1047 "(vmalloc region overlap).\n", 1048 (unsigned long long)bank->start, 1049 (unsigned long long)bank->start + bank->size - 1); 1050 continue; 1051 } 1052 1053 /* 1054 * Check whether this memory bank would partially overlap 1055 * the vmalloc area. 1056 */ 1057 if (__va(bank->start + bank->size - 1) >= vmalloc_min || 1058 __va(bank->start + bank->size - 1) <= __va(bank->start)) { 1059 unsigned long newsize = vmalloc_min - __va(bank->start); 1060 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " 1061 "to -%.8llx (vmalloc region overlap).\n", 1062 (unsigned long long)bank->start, 1063 (unsigned long long)bank->start + bank->size - 1, 1064 (unsigned long long)bank->start + newsize - 1); 1065 bank->size = newsize; 1066 } 1067 #endif 1068 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit) 1069 arm_lowmem_limit = bank->start + bank->size; 1070 1071 j++; 1072 } 1073 #ifdef CONFIG_HIGHMEM 1074 if (highmem) { 1075 const char *reason = NULL; 1076 1077 if (cache_is_vipt_aliasing()) { 1078 /* 1079 * Interactions between kmap and other mappings 1080 * make highmem support with aliasing VIPT caches 1081 * rather difficult. 1082 */ 1083 reason = "with VIPT aliasing cache"; 1084 } 1085 if (reason) { 1086 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", 1087 reason); 1088 while (j > 0 && meminfo.bank[j - 1].highmem) 1089 j--; 1090 } 1091 } 1092 #endif 1093 meminfo.nr_banks = j; 1094 high_memory = __va(arm_lowmem_limit - 1) + 1; 1095 memblock_set_current_limit(arm_lowmem_limit); 1096 } 1097 1098 static inline void prepare_page_table(void) 1099 { 1100 unsigned long addr; 1101 phys_addr_t end; 1102 1103 /* 1104 * Clear out all the mappings below the kernel image. 1105 */ 1106 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) 1107 pmd_clear(pmd_off_k(addr)); 1108 1109 #ifdef CONFIG_XIP_KERNEL 1110 /* The XIP kernel is mapped in the module area -- skip over it */ 1111 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; 1112 #endif 1113 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) 1114 pmd_clear(pmd_off_k(addr)); 1115 1116 /* 1117 * Find the end of the first block of lowmem. 1118 */ 1119 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; 1120 if (end >= arm_lowmem_limit) 1121 end = arm_lowmem_limit; 1122 1123 /* 1124 * Clear out all the kernel space mappings, except for the first 1125 * memory bank, up to the vmalloc region. 1126 */ 1127 for (addr = __phys_to_virt(end); 1128 addr < VMALLOC_START; addr += PMD_SIZE) 1129 pmd_clear(pmd_off_k(addr)); 1130 } 1131 1132 #ifdef CONFIG_ARM_LPAE 1133 /* the first page is reserved for pgd */ 1134 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ 1135 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) 1136 #else 1137 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) 1138 #endif 1139 1140 /* 1141 * Reserve the special regions of memory 1142 */ 1143 void __init arm_mm_memblock_reserve(void) 1144 { 1145 /* 1146 * Reserve the page tables. These are already in use, 1147 * and can only be in node 0. 1148 */ 1149 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); 1150 1151 #ifdef CONFIG_SA1111 1152 /* 1153 * Because of the SA1111 DMA bug, we want to preserve our 1154 * precious DMA-able memory... 1155 */ 1156 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); 1157 #endif 1158 } 1159 1160 /* 1161 * Set up the device mappings. Since we clear out the page tables for all 1162 * mappings above VMALLOC_START, we will remove any debug device mappings. 1163 * This means you have to be careful how you debug this function, or any 1164 * called function. This means you can't use any function or debugging 1165 * method which may touch any device, otherwise the kernel _will_ crash. 1166 */ 1167 static void __init devicemaps_init(struct machine_desc *mdesc) 1168 { 1169 struct map_desc map; 1170 unsigned long addr; 1171 void *vectors; 1172 1173 /* 1174 * Allocate the vector page early. 1175 */ 1176 vectors = early_alloc(PAGE_SIZE); 1177 1178 early_trap_init(vectors); 1179 1180 for (addr = VMALLOC_START; addr; addr += PMD_SIZE) 1181 pmd_clear(pmd_off_k(addr)); 1182 1183 /* 1184 * Map the kernel if it is XIP. 1185 * It is always first in the modulearea. 1186 */ 1187 #ifdef CONFIG_XIP_KERNEL 1188 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); 1189 map.virtual = MODULES_VADDR; 1190 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; 1191 map.type = MT_ROM; 1192 create_mapping(&map); 1193 #endif 1194 1195 /* 1196 * Map the cache flushing regions. 1197 */ 1198 #ifdef FLUSH_BASE 1199 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); 1200 map.virtual = FLUSH_BASE; 1201 map.length = SZ_1M; 1202 map.type = MT_CACHECLEAN; 1203 create_mapping(&map); 1204 #endif 1205 #ifdef FLUSH_BASE_MINICACHE 1206 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); 1207 map.virtual = FLUSH_BASE_MINICACHE; 1208 map.length = SZ_1M; 1209 map.type = MT_MINICLEAN; 1210 create_mapping(&map); 1211 #endif 1212 1213 /* 1214 * Create a mapping for the machine vectors at the high-vectors 1215 * location (0xffff0000). If we aren't using high-vectors, also 1216 * create a mapping at the low-vectors virtual address. 1217 */ 1218 map.pfn = __phys_to_pfn(virt_to_phys(vectors)); 1219 map.virtual = 0xffff0000; 1220 map.length = PAGE_SIZE; 1221 map.type = MT_HIGH_VECTORS; 1222 create_mapping(&map); 1223 1224 if (!vectors_high()) { 1225 map.virtual = 0; 1226 map.type = MT_LOW_VECTORS; 1227 create_mapping(&map); 1228 } 1229 1230 /* 1231 * Ask the machine support to map in the statically mapped devices. 1232 */ 1233 if (mdesc->map_io) 1234 mdesc->map_io(); 1235 fill_pmd_gaps(); 1236 1237 /* Reserve fixed i/o space in VMALLOC region */ 1238 pci_reserve_io(); 1239 1240 /* 1241 * Finally flush the caches and tlb to ensure that we're in a 1242 * consistent state wrt the writebuffer. This also ensures that 1243 * any write-allocated cache lines in the vector page are written 1244 * back. After this point, we can start to touch devices again. 1245 */ 1246 local_flush_tlb_all(); 1247 flush_cache_all(); 1248 } 1249 1250 static void __init kmap_init(void) 1251 { 1252 #ifdef CONFIG_HIGHMEM 1253 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), 1254 PKMAP_BASE, _PAGE_KERNEL_TABLE); 1255 #endif 1256 } 1257 1258 static void __init map_lowmem(void) 1259 { 1260 struct memblock_region *reg; 1261 1262 /* Map all the lowmem memory banks. */ 1263 for_each_memblock(memory, reg) { 1264 phys_addr_t start = reg->base; 1265 phys_addr_t end = start + reg->size; 1266 struct map_desc map; 1267 1268 if (end > arm_lowmem_limit) 1269 end = arm_lowmem_limit; 1270 if (start >= end) 1271 break; 1272 1273 map.pfn = __phys_to_pfn(start); 1274 map.virtual = __phys_to_virt(start); 1275 map.length = end - start; 1276 map.type = MT_MEMORY; 1277 1278 create_mapping(&map); 1279 } 1280 } 1281 1282 /* 1283 * paging_init() sets up the page tables, initialises the zone memory 1284 * maps, and sets up the zero page, bad page and bad page tables. 1285 */ 1286 void __init paging_init(struct machine_desc *mdesc) 1287 { 1288 void *zero_page; 1289 1290 memblock_set_current_limit(arm_lowmem_limit); 1291 1292 build_mem_type_table(); 1293 prepare_page_table(); 1294 map_lowmem(); 1295 dma_contiguous_remap(); 1296 devicemaps_init(mdesc); 1297 kmap_init(); 1298 tcm_init(); 1299 1300 top_pmd = pmd_off_k(0xffff0000); 1301 1302 /* allocate the zero page. */ 1303 zero_page = early_alloc(PAGE_SIZE); 1304 1305 bootmem_init(); 1306 1307 empty_zero_page = virt_to_page(zero_page); 1308 __flush_dcache_page(NULL, empty_zero_page); 1309 } 1310