1 /* 2 * Copyright 2012 Pavel Machek <pavel@denx.de> 3 * Copyright (C) 2012-2015 Altera Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #ifndef __MACH_CORE_H 21 #define __MACH_CORE_H 22 23 #define SOCFPGA_RSTMGR_CTRL 0x04 24 #define SOCFPGA_RSTMGR_MODMPURST 0x10 25 #define SOCFPGA_RSTMGR_MODPERRST 0x14 26 #define SOCFPGA_RSTMGR_BRGMODRST 0x1c 27 28 #define SOCFPGA_A10_RSTMGR_CTRL 0xC 29 #define SOCFPGA_A10_RSTMGR_MODMPURST 0x20 30 31 /* System Manager bits */ 32 #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ 33 #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ 34 35 #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ 36 37 void socfpga_init_l2_ecc(void); 38 void socfpga_init_ocram_ecc(void); 39 void socfpga_init_arria10_l2_ecc(void); 40 void socfpga_init_arria10_ocram_ecc(void); 41 42 extern void __iomem *sys_manager_base_addr; 43 extern void __iomem *rst_manager_base_addr; 44 extern void __iomem *sdr_ctl_base_addr; 45 46 u32 socfpga_sdram_self_refresh(u32 sdr_base); 47 extern unsigned int socfpga_sdram_self_refresh_sz; 48 49 extern char secondary_trampoline, secondary_trampoline_end; 50 51 extern unsigned long socfpga_cpu1start_addr; 52 53 #define SOCFPGA_SCU_VIRT_BASE 0xfee00000 54 55 #endif 56