xref: /openbmc/linux/arch/arm/mach-socfpga/core.h (revision 4d113838)
19c4566a1SDinh Nguyen /*
29c4566a1SDinh Nguyen  * Copyright 2012 Pavel Machek <pavel@denx.de>
344fd8c7dSAlan Tull  * Copyright (C) 2012-2015 Altera Corporation
49c4566a1SDinh Nguyen  *
59c4566a1SDinh Nguyen  * This program is free software; you can redistribute it and/or modify
69c4566a1SDinh Nguyen  * it under the terms of the GNU General Public License as published by
79c4566a1SDinh Nguyen  * the Free Software Foundation; either version 2 of the License, or
89c4566a1SDinh Nguyen  * (at your option) any later version.
99c4566a1SDinh Nguyen  *
109c4566a1SDinh Nguyen  * This program is distributed in the hope that it will be useful,
119c4566a1SDinh Nguyen  * but WITHOUT ANY WARRANTY; without even the implied warranty of
129c4566a1SDinh Nguyen  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
139c4566a1SDinh Nguyen  * GNU General Public License for more details.
149c4566a1SDinh Nguyen  *
159c4566a1SDinh Nguyen  * You should have received a copy of the GNU General Public License
169c4566a1SDinh Nguyen  * along with this program; if not, write to the Free Software
179c4566a1SDinh Nguyen  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
189c4566a1SDinh Nguyen  */
199c4566a1SDinh Nguyen 
209c4566a1SDinh Nguyen #ifndef __MACH_CORE_H
219c4566a1SDinh Nguyen #define __MACH_CORE_H
229c4566a1SDinh Nguyen 
235c04b57fSDinh Nguyen #define SOCFPGA_RSTMGR_CTRL	0x04
24d686ce42SAlan Tull #define SOCFPGA_RSTMGR_MODMPURST	0x10
255c04b57fSDinh Nguyen #define SOCFPGA_RSTMGR_MODPERRST	0x14
265c04b57fSDinh Nguyen #define SOCFPGA_RSTMGR_BRGMODRST	0x1c
275c04b57fSDinh Nguyen 
28cd871d51SDinh Nguyen #define SOCFPGA_A10_RSTMGR_CTRL		0xC
2945be0cdbSDinh Nguyen #define SOCFPGA_A10_RSTMGR_MODMPURST	0x20
3045be0cdbSDinh Nguyen 
315c04b57fSDinh Nguyen /* System Manager bits */
325c04b57fSDinh Nguyen #define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
335c04b57fSDinh Nguyen #define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
345c04b57fSDinh Nguyen 
35d686ce42SAlan Tull #define RSTMGR_MPUMODRST_CPU1		0x2     /* CPU1 Reset */
36d686ce42SAlan Tull 
379c4566a1SDinh Nguyen extern void socfpga_init_clocks(void);
389c4566a1SDinh Nguyen extern void socfpga_sysmgr_init(void);
394d113838SThor Thayer void socfpga_init_l2_ecc(void);
409c4566a1SDinh Nguyen 
415c04b57fSDinh Nguyen extern void __iomem *sys_manager_base_addr;
425c04b57fSDinh Nguyen extern void __iomem *rst_manager_base_addr;
4344fd8c7dSAlan Tull extern void __iomem *sdr_ctl_base_addr;
445c04b57fSDinh Nguyen 
4544fd8c7dSAlan Tull u32 socfpga_sdram_self_refresh(u32 sdr_base);
4644fd8c7dSAlan Tull extern unsigned int socfpga_sdram_self_refresh_sz;
479c4566a1SDinh Nguyen 
489c4566a1SDinh Nguyen extern char secondary_trampoline, secondary_trampoline_end;
499c4566a1SDinh Nguyen 
503a4356c0SDinh Nguyen extern unsigned long socfpga_cpu1start_addr;
519c4566a1SDinh Nguyen 
52de04261dSVince Bridgers #define SOCFPGA_SCU_VIRT_BASE   0xfee00000
539c4566a1SDinh Nguyen 
549c4566a1SDinh Nguyen #endif
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