1 /* 2 * R-Car Generation 2 support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Magnus Damm 6 * Copyright (C) 2014 Ulrich Hecht 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk/shmobile.h> 19 #include <linux/clocksource.h> 20 #include <linux/device.h> 21 #include <linux/dma-contiguous.h> 22 #include <linux/io.h> 23 #include <linux/kernel.h> 24 #include <linux/of.h> 25 #include <linux/of_fdt.h> 26 #include <asm/mach/arch.h> 27 #include "common.h" 28 #include "rcar-gen2.h" 29 30 #define MODEMR 0xe6160060 31 32 u32 rcar_gen2_read_mode_pins(void) 33 { 34 static u32 mode; 35 static bool mode_valid; 36 37 if (!mode_valid) { 38 void __iomem *modemr = ioremap_nocache(MODEMR, 4); 39 BUG_ON(!modemr); 40 mode = ioread32(modemr); 41 iounmap(modemr); 42 mode_valid = true; 43 } 44 45 return mode; 46 } 47 48 #define CNTCR 0 49 #define CNTFID0 0x20 50 51 void __init rcar_gen2_timer_init(void) 52 { 53 #if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK) 54 u32 mode = rcar_gen2_read_mode_pins(); 55 #endif 56 #ifdef CONFIG_ARM_ARCH_TIMER 57 void __iomem *base; 58 int extal_mhz = 0; 59 u32 freq; 60 61 if (of_machine_is_compatible("renesas,r8a7794")) { 62 freq = 260000000 / 8; /* ZS / 8 */ 63 /* CNTVOFF has to be initialized either from non-secure 64 * Hypervisor mode or secure Monitor mode with SCR.NS==1. 65 * If TrustZone is enabled then it should be handled by the 66 * secure code. 67 */ 68 asm volatile( 69 " cps 0x16\n" 70 " mrc p15, 0, r1, c1, c1, 0\n" 71 " orr r0, r1, #1\n" 72 " mcr p15, 0, r0, c1, c1, 0\n" 73 " isb\n" 74 " mov r0, #0\n" 75 " mcrr p15, 4, r0, r0, c14\n" 76 " isb\n" 77 " mcr p15, 0, r1, c1, c1, 0\n" 78 " isb\n" 79 " cps 0x13\n" 80 : : : "r0", "r1"); 81 } else { 82 /* At Linux boot time the r8a7790 arch timer comes up 83 * with the counter disabled. Moreover, it may also report 84 * a potentially incorrect fixed 13 MHz frequency. To be 85 * correct these registers need to be updated to use the 86 * frequency EXTAL / 2 which can be determined by the MD pins. 87 */ 88 89 switch (mode & (MD(14) | MD(13))) { 90 case 0: 91 extal_mhz = 15; 92 break; 93 case MD(13): 94 extal_mhz = 20; 95 break; 96 case MD(14): 97 extal_mhz = 26; 98 break; 99 case MD(13) | MD(14): 100 extal_mhz = 30; 101 break; 102 } 103 104 /* The arch timer frequency equals EXTAL / 2 */ 105 freq = extal_mhz * (1000000 / 2); 106 } 107 108 /* Remap "armgcnt address map" space */ 109 base = ioremap(0xe6080000, PAGE_SIZE); 110 111 /* 112 * Update the timer if it is either not running, or is not at the 113 * right frequency. The timer is only configurable in secure mode 114 * so this avoids an abort if the loader started the timer and 115 * entered the kernel in non-secure mode. 116 */ 117 118 if ((ioread32(base + CNTCR) & 1) == 0 || 119 ioread32(base + CNTFID0) != freq) { 120 /* Update registers with correct frequency */ 121 iowrite32(freq, base + CNTFID0); 122 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); 123 124 /* make sure arch timer is started by setting bit 0 of CNTCR */ 125 iowrite32(1, base + CNTCR); 126 } 127 128 iounmap(base); 129 #endif /* CONFIG_ARM_ARCH_TIMER */ 130 131 #ifdef CONFIG_COMMON_CLK 132 rcar_gen2_clocks_init(mode); 133 #endif 134 #ifdef CONFIG_ARCH_SHMOBILE_MULTI 135 clocksource_of_init(); 136 #endif 137 } 138 139 struct memory_reserve_config { 140 u64 reserved; 141 u64 base, size; 142 }; 143 144 static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname, 145 int depth, void *data) 146 { 147 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 148 const __be32 *reg, *endp; 149 int l; 150 struct memory_reserve_config *mrc = data; 151 u64 lpae_start = 1ULL << 32; 152 153 /* We are scanning "memory" nodes only */ 154 if (type == NULL || strcmp(type, "memory")) 155 return 0; 156 157 reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l); 158 if (reg == NULL) 159 reg = of_get_flat_dt_prop(node, "reg", &l); 160 if (reg == NULL) 161 return 0; 162 163 endp = reg + (l / sizeof(__be32)); 164 while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) { 165 u64 base, size; 166 167 base = dt_mem_next_cell(dt_root_addr_cells, ®); 168 size = dt_mem_next_cell(dt_root_size_cells, ®); 169 170 if (base >= lpae_start) 171 continue; 172 173 if ((base + size) >= lpae_start) 174 size = lpae_start - base; 175 176 if (size < mrc->reserved) 177 continue; 178 179 if (base < mrc->base) 180 continue; 181 182 /* keep the area at top near the 32-bit legacy limit */ 183 mrc->base = base + size - mrc->reserved; 184 mrc->size = mrc->reserved; 185 } 186 187 return 0; 188 } 189 190 struct cma *rcar_gen2_dma_contiguous; 191 192 void __init rcar_gen2_reserve(void) 193 { 194 struct memory_reserve_config mrc; 195 196 /* reserve 256 MiB at the top of the physical legacy 32-bit space */ 197 memset(&mrc, 0, sizeof(mrc)); 198 mrc.reserved = SZ_256M; 199 200 of_scan_flat_dt(rcar_gen2_scan_mem, &mrc); 201 #ifdef CONFIG_DMA_CMA 202 if (mrc.size) 203 dma_contiguous_reserve_area(mrc.size, mrc.base, 0, 204 &rcar_gen2_dma_contiguous, true); 205 #endif 206 } 207