1 /* 2 * R-Car Generation 2 support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Magnus Damm 6 * Copyright (C) 2014 Ulrich Hecht 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk/shmobile.h> 19 #include <linux/clocksource.h> 20 #include <linux/device.h> 21 #include <linux/dma-contiguous.h> 22 #include <linux/io.h> 23 #include <linux/kernel.h> 24 #include <linux/of.h> 25 #include <linux/of_fdt.h> 26 #include <asm/mach/arch.h> 27 #include "common.h" 28 #include "rcar-gen2.h" 29 30 #define MODEMR 0xe6160060 31 32 u32 rcar_gen2_read_mode_pins(void) 33 { 34 static u32 mode; 35 static bool mode_valid; 36 37 if (!mode_valid) { 38 void __iomem *modemr = ioremap_nocache(MODEMR, 4); 39 BUG_ON(!modemr); 40 mode = ioread32(modemr); 41 iounmap(modemr); 42 mode_valid = true; 43 } 44 45 return mode; 46 } 47 48 #define CNTCR 0 49 #define CNTFID0 0x20 50 51 void __init rcar_gen2_timer_init(void) 52 { 53 #if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK) 54 u32 mode = rcar_gen2_read_mode_pins(); 55 bool is_e2 = (bool)of_find_compatible_node(NULL, NULL, 56 "renesas,r8a7794"); 57 #endif 58 #ifdef CONFIG_ARM_ARCH_TIMER 59 void __iomem *base; 60 int extal_mhz = 0; 61 u32 freq; 62 63 if (is_e2) { 64 freq = 260000000 / 8; /* ZS / 8 */ 65 /* CNTVOFF has to be initialized either from non-secure 66 * Hypervisor mode or secure Monitor mode with SCR.NS==1. 67 * If TrustZone is enabled then it should be handled by the 68 * secure code. 69 */ 70 asm volatile( 71 " cps 0x16\n" 72 " mrc p15, 0, r1, c1, c1, 0\n" 73 " orr r0, r1, #1\n" 74 " mcr p15, 0, r0, c1, c1, 0\n" 75 " isb\n" 76 " mov r0, #0\n" 77 " mcrr p15, 4, r0, r0, c14\n" 78 " isb\n" 79 " mcr p15, 0, r1, c1, c1, 0\n" 80 " isb\n" 81 " cps 0x13\n" 82 : : : "r0", "r1"); 83 } else { 84 /* At Linux boot time the r8a7790 arch timer comes up 85 * with the counter disabled. Moreover, it may also report 86 * a potentially incorrect fixed 13 MHz frequency. To be 87 * correct these registers need to be updated to use the 88 * frequency EXTAL / 2 which can be determined by the MD pins. 89 */ 90 91 switch (mode & (MD(14) | MD(13))) { 92 case 0: 93 extal_mhz = 15; 94 break; 95 case MD(13): 96 extal_mhz = 20; 97 break; 98 case MD(14): 99 extal_mhz = 26; 100 break; 101 case MD(13) | MD(14): 102 extal_mhz = 30; 103 break; 104 } 105 106 /* The arch timer frequency equals EXTAL / 2 */ 107 freq = extal_mhz * (1000000 / 2); 108 } 109 110 /* Remap "armgcnt address map" space */ 111 base = ioremap(0xe6080000, PAGE_SIZE); 112 113 /* 114 * Update the timer if it is either not running, or is not at the 115 * right frequency. The timer is only configurable in secure mode 116 * so this avoids an abort if the loader started the timer and 117 * entered the kernel in non-secure mode. 118 */ 119 120 if ((ioread32(base + CNTCR) & 1) == 0 || 121 ioread32(base + CNTFID0) != freq) { 122 /* Update registers with correct frequency */ 123 iowrite32(freq, base + CNTFID0); 124 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); 125 126 /* make sure arch timer is started by setting bit 0 of CNTCR */ 127 iowrite32(1, base + CNTCR); 128 } 129 130 iounmap(base); 131 #endif /* CONFIG_ARM_ARCH_TIMER */ 132 133 #ifdef CONFIG_COMMON_CLK 134 rcar_gen2_clocks_init(mode); 135 #endif 136 #ifdef CONFIG_ARCH_SHMOBILE_MULTI 137 clocksource_of_init(); 138 #endif 139 } 140 141 struct memory_reserve_config { 142 u64 reserved; 143 u64 base, size; 144 }; 145 146 static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname, 147 int depth, void *data) 148 { 149 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 150 const __be32 *reg, *endp; 151 int l; 152 struct memory_reserve_config *mrc = data; 153 u64 lpae_start = 1ULL << 32; 154 155 /* We are scanning "memory" nodes only */ 156 if (type == NULL || strcmp(type, "memory")) 157 return 0; 158 159 reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l); 160 if (reg == NULL) 161 reg = of_get_flat_dt_prop(node, "reg", &l); 162 if (reg == NULL) 163 return 0; 164 165 endp = reg + (l / sizeof(__be32)); 166 while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) { 167 u64 base, size; 168 169 base = dt_mem_next_cell(dt_root_addr_cells, ®); 170 size = dt_mem_next_cell(dt_root_size_cells, ®); 171 172 if (base >= lpae_start) 173 continue; 174 175 if ((base + size) >= lpae_start) 176 size = lpae_start - base; 177 178 if (size < mrc->reserved) 179 continue; 180 181 if (base < mrc->base) 182 continue; 183 184 /* keep the area at top near the 32-bit legacy limit */ 185 mrc->base = base + size - mrc->reserved; 186 mrc->size = mrc->reserved; 187 } 188 189 return 0; 190 } 191 192 struct cma *rcar_gen2_dma_contiguous; 193 194 void __init rcar_gen2_reserve(void) 195 { 196 struct memory_reserve_config mrc; 197 198 /* reserve 256 MiB at the top of the physical legacy 32-bit space */ 199 memset(&mrc, 0, sizeof(mrc)); 200 mrc.reserved = SZ_256M; 201 202 of_scan_flat_dt(rcar_gen2_scan_mem, &mrc); 203 #ifdef CONFIG_DMA_CMA 204 if (mrc.size) 205 dma_contiguous_reserve_area(mrc.size, mrc.base, 0, 206 &rcar_gen2_dma_contiguous, true); 207 #endif 208 } 209