1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R-Car Generation 2 support
4  *
5  * Copyright (C) 2013  Renesas Solutions Corp.
6  * Copyright (C) 2013  Magnus Damm
7  * Copyright (C) 2014  Ulrich Hecht
8  */
9 
10 #include <linux/clk-provider.h>
11 #include <linux/clocksource.h>
12 #include <linux/device.h>
13 #include <linux/dma-contiguous.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/memblock.h>
17 #include <linux/of.h>
18 #include <linux/of_fdt.h>
19 #include <linux/of_platform.h>
20 #include <asm/mach/arch.h>
21 #include <asm/secure_cntvoff.h>
22 #include "common.h"
23 #include "rcar-gen2.h"
24 
25 static const struct of_device_id cpg_matches[] __initconst = {
26 	{ .compatible = "renesas,rcar-gen2-cpg-clocks", },
27 	{ .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
28 	{ .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
29 	{ .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
30 	{ .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
31 	{ .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
32 	{ /* sentinel */ }
33 };
34 
35 static unsigned int __init get_extal_freq(void)
36 {
37 	const struct of_device_id *match;
38 	struct device_node *cpg, *extal;
39 	u32 freq = 20000000;
40 	int idx = 0;
41 
42 	cpg = of_find_matching_node_and_match(NULL, cpg_matches, &match);
43 	if (!cpg)
44 		return freq;
45 
46 	if (match->data)
47 		idx = of_property_match_string(cpg, "clock-names", match->data);
48 	extal = of_parse_phandle(cpg, "clocks", idx);
49 	of_node_put(cpg);
50 	if (!extal)
51 		return freq;
52 
53 	of_property_read_u32(extal, "clock-frequency", &freq);
54 	of_node_put(extal);
55 	return freq;
56 }
57 
58 #define CNTCR 0
59 #define CNTFID0 0x20
60 
61 void __init rcar_gen2_timer_init(void)
62 {
63 	void __iomem *base;
64 	u32 freq;
65 
66 	secure_cntvoff_init();
67 
68 	if (of_machine_is_compatible("renesas,r8a7745") ||
69 	    of_machine_is_compatible("renesas,r8a77470") ||
70 	    of_machine_is_compatible("renesas,r8a7792") ||
71 	    of_machine_is_compatible("renesas,r8a7794")) {
72 		freq = 260000000 / 8;	/* ZS / 8 */
73 	} else {
74 		/* At Linux boot time the r8a7790 arch timer comes up
75 		 * with the counter disabled. Moreover, it may also report
76 		 * a potentially incorrect fixed 13 MHz frequency. To be
77 		 * correct these registers need to be updated to use the
78 		 * frequency EXTAL / 2.
79 		 */
80 		freq = get_extal_freq() / 2;
81 	}
82 
83 	/* Remap "armgcnt address map" space */
84 	base = ioremap(0xe6080000, PAGE_SIZE);
85 
86 	/*
87 	 * Update the timer if it is either not running, or is not at the
88 	 * right frequency. The timer is only configurable in secure mode
89 	 * so this avoids an abort if the loader started the timer and
90 	 * entered the kernel in non-secure mode.
91 	 */
92 
93 	if ((ioread32(base + CNTCR) & 1) == 0 ||
94 	    ioread32(base + CNTFID0) != freq) {
95 		/* Update registers with correct frequency */
96 		iowrite32(freq, base + CNTFID0);
97 		asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
98 
99 		/* make sure arch timer is started by setting bit 0 of CNTCR */
100 		iowrite32(1, base + CNTCR);
101 	}
102 
103 	iounmap(base);
104 
105 	of_clk_init(NULL);
106 	timer_probe();
107 }
108 
109 struct memory_reserve_config {
110 	u64 reserved;
111 	u64 base, size;
112 };
113 
114 static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
115 				     int depth, void *data)
116 {
117 	const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
118 	const __be32 *reg, *endp;
119 	int l;
120 	struct memory_reserve_config *mrc = data;
121 	u64 lpae_start = 1ULL << 32;
122 
123 	/* We are scanning "memory" nodes only */
124 	if (type == NULL || strcmp(type, "memory"))
125 		return 0;
126 
127 	reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
128 	if (reg == NULL)
129 		reg = of_get_flat_dt_prop(node, "reg", &l);
130 	if (reg == NULL)
131 		return 0;
132 
133 	endp = reg + (l / sizeof(__be32));
134 	while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
135 		u64 base, size;
136 
137 		base = dt_mem_next_cell(dt_root_addr_cells, &reg);
138 		size = dt_mem_next_cell(dt_root_size_cells, &reg);
139 
140 		if (base >= lpae_start)
141 			continue;
142 
143 		if ((base + size) >= lpae_start)
144 			size = lpae_start - base;
145 
146 		if (size < mrc->reserved)
147 			continue;
148 
149 		if (base < mrc->base)
150 			continue;
151 
152 		/* keep the area at top near the 32-bit legacy limit */
153 		mrc->base = base + size - mrc->reserved;
154 		mrc->size = mrc->reserved;
155 	}
156 
157 	return 0;
158 }
159 
160 void __init rcar_gen2_reserve(void)
161 {
162 	struct memory_reserve_config mrc;
163 
164 	/* reserve 256 MiB at the top of the physical legacy 32-bit space */
165 	memset(&mrc, 0, sizeof(mrc));
166 	mrc.reserved = SZ_256M;
167 
168 	of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
169 #ifdef CONFIG_DMA_CMA
170 	if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size)) {
171 		static struct cma *rcar_gen2_dma_contiguous;
172 
173 		dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
174 					    &rcar_gen2_dma_contiguous, true);
175 	}
176 #endif
177 }
178 
179 static const char * const rcar_gen2_boards_compat_dt[] __initconst = {
180 	"renesas,r8a7790",
181 	"renesas,r8a7791",
182 	"renesas,r8a7792",
183 	"renesas,r8a7793",
184 	"renesas,r8a7794",
185 	NULL,
186 };
187 
188 DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)")
189 	.init_late	= shmobile_init_late,
190 	.init_time	= rcar_gen2_timer_init,
191 	.reserve	= rcar_gen2_reserve,
192 	.dt_compat	= rcar_gen2_boards_compat_dt,
193 MACHINE_END
194 
195 static const char * const rz_g1_boards_compat_dt[] __initconst = {
196 	"renesas,r8a7743",
197 	"renesas,r8a7744",
198 	"renesas,r8a7745",
199 	"renesas,r8a77470",
200 	NULL,
201 };
202 
203 DT_MACHINE_START(RZ_G1_DT, "Generic RZ/G1 (Flattened Device Tree)")
204 	.init_late	= shmobile_init_late,
205 	.init_time	= rcar_gen2_timer_init,
206 	.reserve	= rcar_gen2_reserve,
207 	.dt_compat	= rz_g1_boards_compat_dt,
208 MACHINE_END
209