1 /* 2 * linux/arch/arm/mach-sa1100/neponset.c 3 */ 4 #include <linux/err.h> 5 #include <linux/init.h> 6 #include <linux/ioport.h> 7 #include <linux/irq.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm.h> 12 #include <linux/serial_core.h> 13 #include <linux/slab.h> 14 15 #include <asm/mach-types.h> 16 #include <asm/mach/map.h> 17 #include <asm/mach/serial_sa1100.h> 18 #include <asm/hardware/sa1111.h> 19 #include <asm/sizes.h> 20 21 #include <mach/hardware.h> 22 #include <mach/assabet.h> 23 #include <mach/neponset.h> 24 25 #define NEP_IRQ_SMC91X 0 26 #define NEP_IRQ_USAR 1 27 #define NEP_IRQ_SA1111 2 28 #define NEP_IRQ_NR 3 29 30 #define WHOAMI 0x00 31 #define LEDS 0x10 32 #define SWPK 0x20 33 #define IRR 0x24 34 #define KP_Y_IN 0x80 35 #define KP_X_OUT 0x90 36 #define NCR_0 0xa0 37 #define MDM_CTL_0 0xb0 38 #define MDM_CTL_1 0xb4 39 #define AUD_CTL 0xc0 40 41 #define IRR_ETHERNET (1 << 0) 42 #define IRR_USAR (1 << 1) 43 #define IRR_SA1111 (1 << 2) 44 45 #define MDM_CTL0_RTS1 (1 << 0) 46 #define MDM_CTL0_DTR1 (1 << 1) 47 #define MDM_CTL0_RTS2 (1 << 2) 48 #define MDM_CTL0_DTR2 (1 << 3) 49 50 #define MDM_CTL1_CTS1 (1 << 0) 51 #define MDM_CTL1_DSR1 (1 << 1) 52 #define MDM_CTL1_DCD1 (1 << 2) 53 #define MDM_CTL1_CTS2 (1 << 3) 54 #define MDM_CTL1_DSR2 (1 << 4) 55 #define MDM_CTL1_DCD2 (1 << 5) 56 57 #define AUD_SEL_1341 (1 << 0) 58 #define AUD_MUTE_1341 (1 << 1) 59 60 extern void sa1110_mb_disable(void); 61 62 struct neponset_drvdata { 63 void __iomem *base; 64 struct platform_device *sa1111; 65 struct platform_device *smc91x; 66 unsigned irq_base; 67 #ifdef CONFIG_PM_SLEEP 68 u32 ncr0; 69 u32 mdm_ctl_0; 70 #endif 71 }; 72 73 static void __iomem *nep_base; 74 75 void neponset_ncr_frob(unsigned int mask, unsigned int val) 76 { 77 void __iomem *base = nep_base; 78 79 if (base) { 80 unsigned long flags; 81 unsigned v; 82 83 local_irq_save(flags); 84 v = readb_relaxed(base + NCR_0); 85 writeb_relaxed((v & ~mask) | val, base + NCR_0); 86 local_irq_restore(flags); 87 } else { 88 WARN(1, "nep_base unset\n"); 89 } 90 } 91 92 static void neponset_set_mctrl(struct uart_port *port, u_int mctrl) 93 { 94 void __iomem *base = nep_base; 95 u_int mdm_ctl0; 96 97 if (!base) 98 return; 99 100 mdm_ctl0 = readb_relaxed(base + MDM_CTL_0); 101 if (port->mapbase == _Ser1UTCR0) { 102 if (mctrl & TIOCM_RTS) 103 mdm_ctl0 &= ~MDM_CTL0_RTS2; 104 else 105 mdm_ctl0 |= MDM_CTL0_RTS2; 106 107 if (mctrl & TIOCM_DTR) 108 mdm_ctl0 &= ~MDM_CTL0_DTR2; 109 else 110 mdm_ctl0 |= MDM_CTL0_DTR2; 111 } else if (port->mapbase == _Ser3UTCR0) { 112 if (mctrl & TIOCM_RTS) 113 mdm_ctl0 &= ~MDM_CTL0_RTS1; 114 else 115 mdm_ctl0 |= MDM_CTL0_RTS1; 116 117 if (mctrl & TIOCM_DTR) 118 mdm_ctl0 &= ~MDM_CTL0_DTR1; 119 else 120 mdm_ctl0 |= MDM_CTL0_DTR1; 121 } 122 123 writeb_relaxed(mdm_ctl0, base + MDM_CTL_0); 124 } 125 126 static u_int neponset_get_mctrl(struct uart_port *port) 127 { 128 void __iomem *base = nep_base; 129 u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; 130 u_int mdm_ctl1; 131 132 if (!base) 133 return ret; 134 135 mdm_ctl1 = readb_relaxed(base + MDM_CTL_1); 136 if (port->mapbase == _Ser1UTCR0) { 137 if (mdm_ctl1 & MDM_CTL1_DCD2) 138 ret &= ~TIOCM_CD; 139 if (mdm_ctl1 & MDM_CTL1_CTS2) 140 ret &= ~TIOCM_CTS; 141 if (mdm_ctl1 & MDM_CTL1_DSR2) 142 ret &= ~TIOCM_DSR; 143 } else if (port->mapbase == _Ser3UTCR0) { 144 if (mdm_ctl1 & MDM_CTL1_DCD1) 145 ret &= ~TIOCM_CD; 146 if (mdm_ctl1 & MDM_CTL1_CTS1) 147 ret &= ~TIOCM_CTS; 148 if (mdm_ctl1 & MDM_CTL1_DSR1) 149 ret &= ~TIOCM_DSR; 150 } 151 152 return ret; 153 } 154 155 static struct sa1100_port_fns neponset_port_fns __devinitdata = { 156 .set_mctrl = neponset_set_mctrl, 157 .get_mctrl = neponset_get_mctrl, 158 }; 159 160 /* 161 * Install handler for Neponset IRQ. Note that we have to loop here 162 * since the ETHERNET and USAR IRQs are level based, and we need to 163 * ensure that the IRQ signal is deasserted before returning. This 164 * is rather unfortunate. 165 */ 166 static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc) 167 { 168 struct neponset_drvdata *d = irq_desc_get_handler_data(desc); 169 unsigned int irr; 170 171 while (1) { 172 /* 173 * Acknowledge the parent IRQ. 174 */ 175 desc->irq_data.chip->irq_ack(&desc->irq_data); 176 177 /* 178 * Read the interrupt reason register. Let's have all 179 * active IRQ bits high. Note: there is a typo in the 180 * Neponset user's guide for the SA1111 IRR level. 181 */ 182 irr = readb_relaxed(d->base + IRR); 183 irr ^= IRR_ETHERNET | IRR_USAR; 184 185 if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0) 186 break; 187 188 /* 189 * Since there is no individual mask, we have to 190 * mask the parent IRQ. This is safe, since we'll 191 * recheck the register for any pending IRQs. 192 */ 193 if (irr & (IRR_ETHERNET | IRR_USAR)) { 194 desc->irq_data.chip->irq_mask(&desc->irq_data); 195 196 /* 197 * Ack the interrupt now to prevent re-entering 198 * this neponset handler. Again, this is safe 199 * since we'll check the IRR register prior to 200 * leaving. 201 */ 202 desc->irq_data.chip->irq_ack(&desc->irq_data); 203 204 if (irr & IRR_ETHERNET) 205 generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X); 206 207 if (irr & IRR_USAR) 208 generic_handle_irq(d->irq_base + NEP_IRQ_USAR); 209 210 desc->irq_data.chip->irq_unmask(&desc->irq_data); 211 } 212 213 if (irr & IRR_SA1111) 214 generic_handle_irq(d->irq_base + NEP_IRQ_SA1111); 215 } 216 } 217 218 /* Yes, we really do not have any kind of masking or unmasking */ 219 static void nochip_noop(struct irq_data *irq) 220 { 221 } 222 223 static struct irq_chip nochip = { 224 .name = "neponset", 225 .irq_ack = nochip_noop, 226 .irq_mask = nochip_noop, 227 .irq_unmask = nochip_noop, 228 }; 229 230 static struct sa1111_platform_data sa1111_info = { 231 .irq_base = IRQ_BOARD_END, 232 }; 233 234 static int __devinit neponset_probe(struct platform_device *dev) 235 { 236 struct neponset_drvdata *d; 237 struct resource *nep_res, *sa1111_res, *smc91x_res; 238 struct resource sa1111_resources[] = { 239 DEFINE_RES_MEM(0x40000000, SZ_8K), 240 { .flags = IORESOURCE_IRQ }, 241 }; 242 struct platform_device_info sa1111_devinfo = { 243 .parent = &dev->dev, 244 .name = "sa1111", 245 .id = 0, 246 .res = sa1111_resources, 247 .num_res = ARRAY_SIZE(sa1111_resources), 248 .data = &sa1111_info, 249 .size_data = sizeof(sa1111_info), 250 .dma_mask = 0xffffffffUL, 251 }; 252 struct resource smc91x_resources[] = { 253 DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS, 254 0x02000000, "smc91x-regs"), 255 DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000, 256 0x02000000, "smc91x-attrib"), 257 { .flags = IORESOURCE_IRQ }, 258 }; 259 struct platform_device_info smc91x_devinfo = { 260 .parent = &dev->dev, 261 .name = "smc91x", 262 .id = 0, 263 .res = smc91x_resources, 264 .num_res = ARRAY_SIZE(smc91x_resources), 265 }; 266 int ret, irq; 267 268 if (nep_base) 269 return -EBUSY; 270 271 irq = ret = platform_get_irq(dev, 0); 272 if (ret < 0) 273 goto err_alloc; 274 275 nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0); 276 smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1); 277 sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2); 278 if (!nep_res || !smc91x_res || !sa1111_res) { 279 ret = -ENXIO; 280 goto err_alloc; 281 } 282 283 d = kzalloc(sizeof(*d), GFP_KERNEL); 284 if (!d) { 285 ret = -ENOMEM; 286 goto err_alloc; 287 } 288 289 d->base = ioremap(nep_res->start, SZ_4K); 290 if (!d->base) { 291 ret = -ENOMEM; 292 goto err_ioremap; 293 } 294 295 if (readb_relaxed(d->base + WHOAMI) != 0x11) { 296 dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n", 297 readb_relaxed(d->base + WHOAMI)); 298 ret = -ENODEV; 299 goto err_id; 300 } 301 302 ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1); 303 if (ret <= 0) { 304 dev_err(&dev->dev, "unable to allocate %u irqs: %d\n", 305 NEP_IRQ_NR, ret); 306 if (ret == 0) 307 ret = -ENOMEM; 308 goto err_irq_alloc; 309 } 310 311 d->irq_base = ret; 312 313 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip, 314 handle_simple_irq); 315 set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE); 316 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip, 317 handle_simple_irq); 318 set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE); 319 irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip); 320 321 irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); 322 irq_set_handler_data(irq, d); 323 irq_set_chained_handler(irq, neponset_irq_handler); 324 325 /* 326 * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately 327 * something on the Neponset activates this IRQ on sleep (eth?) 328 */ 329 #if 0 330 enable_irq_wake(irq); 331 #endif 332 333 dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n", 334 d->irq_base, d->irq_base + NEP_IRQ_NR - 1); 335 nep_base = d->base; 336 337 sa1100_register_uart_fns(&neponset_port_fns); 338 339 /* Ensure that the memory bus request/grant signals are setup */ 340 sa1110_mb_disable(); 341 342 /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */ 343 writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0); 344 345 sa1111_resources[0].parent = sa1111_res; 346 sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111; 347 sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111; 348 d->sa1111 = platform_device_register_full(&sa1111_devinfo); 349 350 smc91x_resources[0].parent = smc91x_res; 351 smc91x_resources[1].parent = smc91x_res; 352 smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X; 353 smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X; 354 d->smc91x = platform_device_register_full(&smc91x_devinfo); 355 356 platform_set_drvdata(dev, d); 357 358 return 0; 359 360 err_irq_alloc: 361 err_id: 362 iounmap(d->base); 363 err_ioremap: 364 kfree(d); 365 err_alloc: 366 return ret; 367 } 368 369 static int __devexit neponset_remove(struct platform_device *dev) 370 { 371 struct neponset_drvdata *d = platform_get_drvdata(dev); 372 int irq = platform_get_irq(dev, 0); 373 374 if (!IS_ERR(d->sa1111)) 375 platform_device_unregister(d->sa1111); 376 if (!IS_ERR(d->smc91x)) 377 platform_device_unregister(d->smc91x); 378 irq_set_chained_handler(irq, NULL); 379 irq_free_descs(d->irq_base, NEP_IRQ_NR); 380 nep_base = NULL; 381 iounmap(d->base); 382 kfree(d); 383 384 return 0; 385 } 386 387 #ifdef CONFIG_PM_SLEEP 388 static int neponset_suspend(struct device *dev) 389 { 390 struct neponset_drvdata *d = dev_get_drvdata(dev); 391 392 d->ncr0 = readb_relaxed(d->base + NCR_0); 393 d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0); 394 395 return 0; 396 } 397 398 static int neponset_resume(struct device *dev) 399 { 400 struct neponset_drvdata *d = dev_get_drvdata(dev); 401 402 writeb_relaxed(d->ncr0, d->base + NCR_0); 403 writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0); 404 405 return 0; 406 } 407 408 static const struct dev_pm_ops neponset_pm_ops = { 409 .suspend_noirq = neponset_suspend, 410 .resume_noirq = neponset_resume, 411 .freeze_noirq = neponset_suspend, 412 .restore_noirq = neponset_resume, 413 }; 414 #define PM_OPS &neponset_pm_ops 415 #else 416 #define PM_OPS NULL 417 #endif 418 419 static struct platform_driver neponset_device_driver = { 420 .probe = neponset_probe, 421 .remove = __devexit_p(neponset_remove), 422 .driver = { 423 .name = "neponset", 424 .owner = THIS_MODULE, 425 .pm = PM_OPS, 426 }, 427 }; 428 429 static int __init neponset_init(void) 430 { 431 return platform_driver_register(&neponset_device_driver); 432 } 433 434 subsys_initcall(neponset_init); 435 436 static struct map_desc neponset_io_desc[] __initdata = { 437 { /* System Registers */ 438 .virtual = 0xf3000000, 439 .pfn = __phys_to_pfn(0x10000000), 440 .length = SZ_1M, 441 .type = MT_DEVICE 442 }, { /* SA-1111 */ 443 .virtual = 0xf4000000, 444 .pfn = __phys_to_pfn(0x40000000), 445 .length = SZ_1M, 446 .type = MT_DEVICE 447 } 448 }; 449 450 void __init neponset_map_io(void) 451 { 452 iotable_init(neponset_io_desc, ARRAY_SIZE(neponset_io_desc)); 453 } 454