1 /* 2 * linux/arch/arm/mach-sa1100/neponset.c 3 */ 4 #include <linux/err.h> 5 #include <linux/init.h> 6 #include <linux/ioport.h> 7 #include <linux/irq.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/platform_data/sa11x0-serial.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm.h> 13 #include <linux/serial_core.h> 14 #include <linux/slab.h> 15 16 #include <asm/mach-types.h> 17 #include <asm/mach/map.h> 18 #include <asm/hardware/sa1111.h> 19 #include <asm/sizes.h> 20 21 #include <mach/hardware.h> 22 #include <mach/assabet.h> 23 #include <mach/neponset.h> 24 #include <mach/irqs.h> 25 26 #define NEP_IRQ_SMC91X 0 27 #define NEP_IRQ_USAR 1 28 #define NEP_IRQ_SA1111 2 29 #define NEP_IRQ_NR 3 30 31 #define WHOAMI 0x00 32 #define LEDS 0x10 33 #define SWPK 0x20 34 #define IRR 0x24 35 #define KP_Y_IN 0x80 36 #define KP_X_OUT 0x90 37 #define NCR_0 0xa0 38 #define MDM_CTL_0 0xb0 39 #define MDM_CTL_1 0xb4 40 #define AUD_CTL 0xc0 41 42 #define IRR_ETHERNET (1 << 0) 43 #define IRR_USAR (1 << 1) 44 #define IRR_SA1111 (1 << 2) 45 46 #define MDM_CTL0_RTS1 (1 << 0) 47 #define MDM_CTL0_DTR1 (1 << 1) 48 #define MDM_CTL0_RTS2 (1 << 2) 49 #define MDM_CTL0_DTR2 (1 << 3) 50 51 #define MDM_CTL1_CTS1 (1 << 0) 52 #define MDM_CTL1_DSR1 (1 << 1) 53 #define MDM_CTL1_DCD1 (1 << 2) 54 #define MDM_CTL1_CTS2 (1 << 3) 55 #define MDM_CTL1_DSR2 (1 << 4) 56 #define MDM_CTL1_DCD2 (1 << 5) 57 58 #define AUD_SEL_1341 (1 << 0) 59 #define AUD_MUTE_1341 (1 << 1) 60 61 extern void sa1110_mb_disable(void); 62 63 struct neponset_drvdata { 64 void __iomem *base; 65 struct platform_device *sa1111; 66 struct platform_device *smc91x; 67 unsigned irq_base; 68 #ifdef CONFIG_PM_SLEEP 69 u32 ncr0; 70 u32 mdm_ctl_0; 71 #endif 72 }; 73 74 static void __iomem *nep_base; 75 76 void neponset_ncr_frob(unsigned int mask, unsigned int val) 77 { 78 void __iomem *base = nep_base; 79 80 if (base) { 81 unsigned long flags; 82 unsigned v; 83 84 local_irq_save(flags); 85 v = readb_relaxed(base + NCR_0); 86 writeb_relaxed((v & ~mask) | val, base + NCR_0); 87 local_irq_restore(flags); 88 } else { 89 WARN(1, "nep_base unset\n"); 90 } 91 } 92 EXPORT_SYMBOL(neponset_ncr_frob); 93 94 static void neponset_set_mctrl(struct uart_port *port, u_int mctrl) 95 { 96 void __iomem *base = nep_base; 97 u_int mdm_ctl0; 98 99 if (!base) 100 return; 101 102 mdm_ctl0 = readb_relaxed(base + MDM_CTL_0); 103 if (port->mapbase == _Ser1UTCR0) { 104 if (mctrl & TIOCM_RTS) 105 mdm_ctl0 &= ~MDM_CTL0_RTS2; 106 else 107 mdm_ctl0 |= MDM_CTL0_RTS2; 108 109 if (mctrl & TIOCM_DTR) 110 mdm_ctl0 &= ~MDM_CTL0_DTR2; 111 else 112 mdm_ctl0 |= MDM_CTL0_DTR2; 113 } else if (port->mapbase == _Ser3UTCR0) { 114 if (mctrl & TIOCM_RTS) 115 mdm_ctl0 &= ~MDM_CTL0_RTS1; 116 else 117 mdm_ctl0 |= MDM_CTL0_RTS1; 118 119 if (mctrl & TIOCM_DTR) 120 mdm_ctl0 &= ~MDM_CTL0_DTR1; 121 else 122 mdm_ctl0 |= MDM_CTL0_DTR1; 123 } 124 125 writeb_relaxed(mdm_ctl0, base + MDM_CTL_0); 126 } 127 128 static u_int neponset_get_mctrl(struct uart_port *port) 129 { 130 void __iomem *base = nep_base; 131 u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; 132 u_int mdm_ctl1; 133 134 if (!base) 135 return ret; 136 137 mdm_ctl1 = readb_relaxed(base + MDM_CTL_1); 138 if (port->mapbase == _Ser1UTCR0) { 139 if (mdm_ctl1 & MDM_CTL1_DCD2) 140 ret &= ~TIOCM_CD; 141 if (mdm_ctl1 & MDM_CTL1_CTS2) 142 ret &= ~TIOCM_CTS; 143 if (mdm_ctl1 & MDM_CTL1_DSR2) 144 ret &= ~TIOCM_DSR; 145 } else if (port->mapbase == _Ser3UTCR0) { 146 if (mdm_ctl1 & MDM_CTL1_DCD1) 147 ret &= ~TIOCM_CD; 148 if (mdm_ctl1 & MDM_CTL1_CTS1) 149 ret &= ~TIOCM_CTS; 150 if (mdm_ctl1 & MDM_CTL1_DSR1) 151 ret &= ~TIOCM_DSR; 152 } 153 154 return ret; 155 } 156 157 static struct sa1100_port_fns neponset_port_fns __devinitdata = { 158 .set_mctrl = neponset_set_mctrl, 159 .get_mctrl = neponset_get_mctrl, 160 }; 161 162 /* 163 * Install handler for Neponset IRQ. Note that we have to loop here 164 * since the ETHERNET and USAR IRQs are level based, and we need to 165 * ensure that the IRQ signal is deasserted before returning. This 166 * is rather unfortunate. 167 */ 168 static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc) 169 { 170 struct neponset_drvdata *d = irq_desc_get_handler_data(desc); 171 unsigned int irr; 172 173 while (1) { 174 /* 175 * Acknowledge the parent IRQ. 176 */ 177 desc->irq_data.chip->irq_ack(&desc->irq_data); 178 179 /* 180 * Read the interrupt reason register. Let's have all 181 * active IRQ bits high. Note: there is a typo in the 182 * Neponset user's guide for the SA1111 IRR level. 183 */ 184 irr = readb_relaxed(d->base + IRR); 185 irr ^= IRR_ETHERNET | IRR_USAR; 186 187 if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0) 188 break; 189 190 /* 191 * Since there is no individual mask, we have to 192 * mask the parent IRQ. This is safe, since we'll 193 * recheck the register for any pending IRQs. 194 */ 195 if (irr & (IRR_ETHERNET | IRR_USAR)) { 196 desc->irq_data.chip->irq_mask(&desc->irq_data); 197 198 /* 199 * Ack the interrupt now to prevent re-entering 200 * this neponset handler. Again, this is safe 201 * since we'll check the IRR register prior to 202 * leaving. 203 */ 204 desc->irq_data.chip->irq_ack(&desc->irq_data); 205 206 if (irr & IRR_ETHERNET) 207 generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X); 208 209 if (irr & IRR_USAR) 210 generic_handle_irq(d->irq_base + NEP_IRQ_USAR); 211 212 desc->irq_data.chip->irq_unmask(&desc->irq_data); 213 } 214 215 if (irr & IRR_SA1111) 216 generic_handle_irq(d->irq_base + NEP_IRQ_SA1111); 217 } 218 } 219 220 /* Yes, we really do not have any kind of masking or unmasking */ 221 static void nochip_noop(struct irq_data *irq) 222 { 223 } 224 225 static struct irq_chip nochip = { 226 .name = "neponset", 227 .irq_ack = nochip_noop, 228 .irq_mask = nochip_noop, 229 .irq_unmask = nochip_noop, 230 }; 231 232 static struct sa1111_platform_data sa1111_info = { 233 .disable_devs = SA1111_DEVID_PS2_MSE, 234 }; 235 236 static int __devinit neponset_probe(struct platform_device *dev) 237 { 238 struct neponset_drvdata *d; 239 struct resource *nep_res, *sa1111_res, *smc91x_res; 240 struct resource sa1111_resources[] = { 241 DEFINE_RES_MEM(0x40000000, SZ_8K), 242 { .flags = IORESOURCE_IRQ }, 243 }; 244 struct platform_device_info sa1111_devinfo = { 245 .parent = &dev->dev, 246 .name = "sa1111", 247 .id = 0, 248 .res = sa1111_resources, 249 .num_res = ARRAY_SIZE(sa1111_resources), 250 .data = &sa1111_info, 251 .size_data = sizeof(sa1111_info), 252 .dma_mask = 0xffffffffUL, 253 }; 254 struct resource smc91x_resources[] = { 255 DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS, 256 0x02000000, "smc91x-regs"), 257 DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000, 258 0x02000000, "smc91x-attrib"), 259 { .flags = IORESOURCE_IRQ }, 260 }; 261 struct platform_device_info smc91x_devinfo = { 262 .parent = &dev->dev, 263 .name = "smc91x", 264 .id = 0, 265 .res = smc91x_resources, 266 .num_res = ARRAY_SIZE(smc91x_resources), 267 }; 268 int ret, irq; 269 270 if (nep_base) 271 return -EBUSY; 272 273 irq = ret = platform_get_irq(dev, 0); 274 if (ret < 0) 275 goto err_alloc; 276 277 nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0); 278 smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1); 279 sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2); 280 if (!nep_res || !smc91x_res || !sa1111_res) { 281 ret = -ENXIO; 282 goto err_alloc; 283 } 284 285 d = kzalloc(sizeof(*d), GFP_KERNEL); 286 if (!d) { 287 ret = -ENOMEM; 288 goto err_alloc; 289 } 290 291 d->base = ioremap(nep_res->start, SZ_4K); 292 if (!d->base) { 293 ret = -ENOMEM; 294 goto err_ioremap; 295 } 296 297 if (readb_relaxed(d->base + WHOAMI) != 0x11) { 298 dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n", 299 readb_relaxed(d->base + WHOAMI)); 300 ret = -ENODEV; 301 goto err_id; 302 } 303 304 ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1); 305 if (ret <= 0) { 306 dev_err(&dev->dev, "unable to allocate %u irqs: %d\n", 307 NEP_IRQ_NR, ret); 308 if (ret == 0) 309 ret = -ENOMEM; 310 goto err_irq_alloc; 311 } 312 313 d->irq_base = ret; 314 315 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip, 316 handle_simple_irq); 317 set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE); 318 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip, 319 handle_simple_irq); 320 set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE); 321 irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip); 322 323 irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); 324 irq_set_handler_data(irq, d); 325 irq_set_chained_handler(irq, neponset_irq_handler); 326 327 /* 328 * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately 329 * something on the Neponset activates this IRQ on sleep (eth?) 330 */ 331 #if 0 332 enable_irq_wake(irq); 333 #endif 334 335 dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n", 336 d->irq_base, d->irq_base + NEP_IRQ_NR - 1); 337 nep_base = d->base; 338 339 sa1100_register_uart_fns(&neponset_port_fns); 340 341 /* Ensure that the memory bus request/grant signals are setup */ 342 sa1110_mb_disable(); 343 344 /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */ 345 writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0); 346 347 sa1111_resources[0].parent = sa1111_res; 348 sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111; 349 sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111; 350 d->sa1111 = platform_device_register_full(&sa1111_devinfo); 351 352 smc91x_resources[0].parent = smc91x_res; 353 smc91x_resources[1].parent = smc91x_res; 354 smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X; 355 smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X; 356 d->smc91x = platform_device_register_full(&smc91x_devinfo); 357 358 platform_set_drvdata(dev, d); 359 360 return 0; 361 362 err_irq_alloc: 363 err_id: 364 iounmap(d->base); 365 err_ioremap: 366 kfree(d); 367 err_alloc: 368 return ret; 369 } 370 371 static int __devexit neponset_remove(struct platform_device *dev) 372 { 373 struct neponset_drvdata *d = platform_get_drvdata(dev); 374 int irq = platform_get_irq(dev, 0); 375 376 if (!IS_ERR(d->sa1111)) 377 platform_device_unregister(d->sa1111); 378 if (!IS_ERR(d->smc91x)) 379 platform_device_unregister(d->smc91x); 380 irq_set_chained_handler(irq, NULL); 381 irq_free_descs(d->irq_base, NEP_IRQ_NR); 382 nep_base = NULL; 383 iounmap(d->base); 384 kfree(d); 385 386 return 0; 387 } 388 389 #ifdef CONFIG_PM_SLEEP 390 static int neponset_suspend(struct device *dev) 391 { 392 struct neponset_drvdata *d = dev_get_drvdata(dev); 393 394 d->ncr0 = readb_relaxed(d->base + NCR_0); 395 d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0); 396 397 return 0; 398 } 399 400 static int neponset_resume(struct device *dev) 401 { 402 struct neponset_drvdata *d = dev_get_drvdata(dev); 403 404 writeb_relaxed(d->ncr0, d->base + NCR_0); 405 writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0); 406 407 return 0; 408 } 409 410 static const struct dev_pm_ops neponset_pm_ops = { 411 .suspend_noirq = neponset_suspend, 412 .resume_noirq = neponset_resume, 413 .freeze_noirq = neponset_suspend, 414 .restore_noirq = neponset_resume, 415 }; 416 #define PM_OPS &neponset_pm_ops 417 #else 418 #define PM_OPS NULL 419 #endif 420 421 static struct platform_driver neponset_device_driver = { 422 .probe = neponset_probe, 423 .remove = __devexit_p(neponset_remove), 424 .driver = { 425 .name = "neponset", 426 .owner = THIS_MODULE, 427 .pm = PM_OPS, 428 }, 429 }; 430 431 static int __init neponset_init(void) 432 { 433 return platform_driver_register(&neponset_device_driver); 434 } 435 436 subsys_initcall(neponset_init); 437