1 /* 2 * linux/arch/arm/mach-sa1100/neponset.c 3 */ 4 #include <linux/err.h> 5 #include <linux/init.h> 6 #include <linux/ioport.h> 7 #include <linux/irq.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm.h> 12 #include <linux/serial_core.h> 13 #include <linux/slab.h> 14 15 #include <asm/mach-types.h> 16 #include <asm/mach/map.h> 17 #include <asm/mach/serial_sa1100.h> 18 #include <asm/hardware/sa1111.h> 19 #include <asm/sizes.h> 20 21 #include <mach/hardware.h> 22 #include <mach/assabet.h> 23 #include <mach/neponset.h> 24 #include <mach/irqs.h> 25 26 #define NEP_IRQ_SMC91X 0 27 #define NEP_IRQ_USAR 1 28 #define NEP_IRQ_SA1111 2 29 #define NEP_IRQ_NR 3 30 31 #define WHOAMI 0x00 32 #define LEDS 0x10 33 #define SWPK 0x20 34 #define IRR 0x24 35 #define KP_Y_IN 0x80 36 #define KP_X_OUT 0x90 37 #define NCR_0 0xa0 38 #define MDM_CTL_0 0xb0 39 #define MDM_CTL_1 0xb4 40 #define AUD_CTL 0xc0 41 42 #define IRR_ETHERNET (1 << 0) 43 #define IRR_USAR (1 << 1) 44 #define IRR_SA1111 (1 << 2) 45 46 #define MDM_CTL0_RTS1 (1 << 0) 47 #define MDM_CTL0_DTR1 (1 << 1) 48 #define MDM_CTL0_RTS2 (1 << 2) 49 #define MDM_CTL0_DTR2 (1 << 3) 50 51 #define MDM_CTL1_CTS1 (1 << 0) 52 #define MDM_CTL1_DSR1 (1 << 1) 53 #define MDM_CTL1_DCD1 (1 << 2) 54 #define MDM_CTL1_CTS2 (1 << 3) 55 #define MDM_CTL1_DSR2 (1 << 4) 56 #define MDM_CTL1_DCD2 (1 << 5) 57 58 #define AUD_SEL_1341 (1 << 0) 59 #define AUD_MUTE_1341 (1 << 1) 60 61 extern void sa1110_mb_disable(void); 62 63 struct neponset_drvdata { 64 void __iomem *base; 65 struct platform_device *sa1111; 66 struct platform_device *smc91x; 67 unsigned irq_base; 68 #ifdef CONFIG_PM_SLEEP 69 u32 ncr0; 70 u32 mdm_ctl_0; 71 #endif 72 }; 73 74 static void __iomem *nep_base; 75 76 void neponset_ncr_frob(unsigned int mask, unsigned int val) 77 { 78 void __iomem *base = nep_base; 79 80 if (base) { 81 unsigned long flags; 82 unsigned v; 83 84 local_irq_save(flags); 85 v = readb_relaxed(base + NCR_0); 86 writeb_relaxed((v & ~mask) | val, base + NCR_0); 87 local_irq_restore(flags); 88 } else { 89 WARN(1, "nep_base unset\n"); 90 } 91 } 92 93 static void neponset_set_mctrl(struct uart_port *port, u_int mctrl) 94 { 95 void __iomem *base = nep_base; 96 u_int mdm_ctl0; 97 98 if (!base) 99 return; 100 101 mdm_ctl0 = readb_relaxed(base + MDM_CTL_0); 102 if (port->mapbase == _Ser1UTCR0) { 103 if (mctrl & TIOCM_RTS) 104 mdm_ctl0 &= ~MDM_CTL0_RTS2; 105 else 106 mdm_ctl0 |= MDM_CTL0_RTS2; 107 108 if (mctrl & TIOCM_DTR) 109 mdm_ctl0 &= ~MDM_CTL0_DTR2; 110 else 111 mdm_ctl0 |= MDM_CTL0_DTR2; 112 } else if (port->mapbase == _Ser3UTCR0) { 113 if (mctrl & TIOCM_RTS) 114 mdm_ctl0 &= ~MDM_CTL0_RTS1; 115 else 116 mdm_ctl0 |= MDM_CTL0_RTS1; 117 118 if (mctrl & TIOCM_DTR) 119 mdm_ctl0 &= ~MDM_CTL0_DTR1; 120 else 121 mdm_ctl0 |= MDM_CTL0_DTR1; 122 } 123 124 writeb_relaxed(mdm_ctl0, base + MDM_CTL_0); 125 } 126 127 static u_int neponset_get_mctrl(struct uart_port *port) 128 { 129 void __iomem *base = nep_base; 130 u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; 131 u_int mdm_ctl1; 132 133 if (!base) 134 return ret; 135 136 mdm_ctl1 = readb_relaxed(base + MDM_CTL_1); 137 if (port->mapbase == _Ser1UTCR0) { 138 if (mdm_ctl1 & MDM_CTL1_DCD2) 139 ret &= ~TIOCM_CD; 140 if (mdm_ctl1 & MDM_CTL1_CTS2) 141 ret &= ~TIOCM_CTS; 142 if (mdm_ctl1 & MDM_CTL1_DSR2) 143 ret &= ~TIOCM_DSR; 144 } else if (port->mapbase == _Ser3UTCR0) { 145 if (mdm_ctl1 & MDM_CTL1_DCD1) 146 ret &= ~TIOCM_CD; 147 if (mdm_ctl1 & MDM_CTL1_CTS1) 148 ret &= ~TIOCM_CTS; 149 if (mdm_ctl1 & MDM_CTL1_DSR1) 150 ret &= ~TIOCM_DSR; 151 } 152 153 return ret; 154 } 155 156 static struct sa1100_port_fns neponset_port_fns __devinitdata = { 157 .set_mctrl = neponset_set_mctrl, 158 .get_mctrl = neponset_get_mctrl, 159 }; 160 161 /* 162 * Install handler for Neponset IRQ. Note that we have to loop here 163 * since the ETHERNET and USAR IRQs are level based, and we need to 164 * ensure that the IRQ signal is deasserted before returning. This 165 * is rather unfortunate. 166 */ 167 static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc) 168 { 169 struct neponset_drvdata *d = irq_desc_get_handler_data(desc); 170 unsigned int irr; 171 172 while (1) { 173 /* 174 * Acknowledge the parent IRQ. 175 */ 176 desc->irq_data.chip->irq_ack(&desc->irq_data); 177 178 /* 179 * Read the interrupt reason register. Let's have all 180 * active IRQ bits high. Note: there is a typo in the 181 * Neponset user's guide for the SA1111 IRR level. 182 */ 183 irr = readb_relaxed(d->base + IRR); 184 irr ^= IRR_ETHERNET | IRR_USAR; 185 186 if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0) 187 break; 188 189 /* 190 * Since there is no individual mask, we have to 191 * mask the parent IRQ. This is safe, since we'll 192 * recheck the register for any pending IRQs. 193 */ 194 if (irr & (IRR_ETHERNET | IRR_USAR)) { 195 desc->irq_data.chip->irq_mask(&desc->irq_data); 196 197 /* 198 * Ack the interrupt now to prevent re-entering 199 * this neponset handler. Again, this is safe 200 * since we'll check the IRR register prior to 201 * leaving. 202 */ 203 desc->irq_data.chip->irq_ack(&desc->irq_data); 204 205 if (irr & IRR_ETHERNET) 206 generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X); 207 208 if (irr & IRR_USAR) 209 generic_handle_irq(d->irq_base + NEP_IRQ_USAR); 210 211 desc->irq_data.chip->irq_unmask(&desc->irq_data); 212 } 213 214 if (irr & IRR_SA1111) 215 generic_handle_irq(d->irq_base + NEP_IRQ_SA1111); 216 } 217 } 218 219 /* Yes, we really do not have any kind of masking or unmasking */ 220 static void nochip_noop(struct irq_data *irq) 221 { 222 } 223 224 static struct irq_chip nochip = { 225 .name = "neponset", 226 .irq_ack = nochip_noop, 227 .irq_mask = nochip_noop, 228 .irq_unmask = nochip_noop, 229 }; 230 231 static struct sa1111_platform_data sa1111_info = { 232 .disable_devs = SA1111_DEVID_PS2_MSE, 233 }; 234 235 static int __devinit neponset_probe(struct platform_device *dev) 236 { 237 struct neponset_drvdata *d; 238 struct resource *nep_res, *sa1111_res, *smc91x_res; 239 struct resource sa1111_resources[] = { 240 DEFINE_RES_MEM(0x40000000, SZ_8K), 241 { .flags = IORESOURCE_IRQ }, 242 }; 243 struct platform_device_info sa1111_devinfo = { 244 .parent = &dev->dev, 245 .name = "sa1111", 246 .id = 0, 247 .res = sa1111_resources, 248 .num_res = ARRAY_SIZE(sa1111_resources), 249 .data = &sa1111_info, 250 .size_data = sizeof(sa1111_info), 251 .dma_mask = 0xffffffffUL, 252 }; 253 struct resource smc91x_resources[] = { 254 DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS, 255 0x02000000, "smc91x-regs"), 256 DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000, 257 0x02000000, "smc91x-attrib"), 258 { .flags = IORESOURCE_IRQ }, 259 }; 260 struct platform_device_info smc91x_devinfo = { 261 .parent = &dev->dev, 262 .name = "smc91x", 263 .id = 0, 264 .res = smc91x_resources, 265 .num_res = ARRAY_SIZE(smc91x_resources), 266 }; 267 int ret, irq; 268 269 if (nep_base) 270 return -EBUSY; 271 272 irq = ret = platform_get_irq(dev, 0); 273 if (ret < 0) 274 goto err_alloc; 275 276 nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0); 277 smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1); 278 sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2); 279 if (!nep_res || !smc91x_res || !sa1111_res) { 280 ret = -ENXIO; 281 goto err_alloc; 282 } 283 284 d = kzalloc(sizeof(*d), GFP_KERNEL); 285 if (!d) { 286 ret = -ENOMEM; 287 goto err_alloc; 288 } 289 290 d->base = ioremap(nep_res->start, SZ_4K); 291 if (!d->base) { 292 ret = -ENOMEM; 293 goto err_ioremap; 294 } 295 296 if (readb_relaxed(d->base + WHOAMI) != 0x11) { 297 dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n", 298 readb_relaxed(d->base + WHOAMI)); 299 ret = -ENODEV; 300 goto err_id; 301 } 302 303 ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1); 304 if (ret <= 0) { 305 dev_err(&dev->dev, "unable to allocate %u irqs: %d\n", 306 NEP_IRQ_NR, ret); 307 if (ret == 0) 308 ret = -ENOMEM; 309 goto err_irq_alloc; 310 } 311 312 d->irq_base = ret; 313 314 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip, 315 handle_simple_irq); 316 set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE); 317 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip, 318 handle_simple_irq); 319 set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE); 320 irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip); 321 322 irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); 323 irq_set_handler_data(irq, d); 324 irq_set_chained_handler(irq, neponset_irq_handler); 325 326 /* 327 * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately 328 * something on the Neponset activates this IRQ on sleep (eth?) 329 */ 330 #if 0 331 enable_irq_wake(irq); 332 #endif 333 334 dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n", 335 d->irq_base, d->irq_base + NEP_IRQ_NR - 1); 336 nep_base = d->base; 337 338 sa1100_register_uart_fns(&neponset_port_fns); 339 340 /* Ensure that the memory bus request/grant signals are setup */ 341 sa1110_mb_disable(); 342 343 /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */ 344 writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0); 345 346 sa1111_resources[0].parent = sa1111_res; 347 sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111; 348 sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111; 349 d->sa1111 = platform_device_register_full(&sa1111_devinfo); 350 351 smc91x_resources[0].parent = smc91x_res; 352 smc91x_resources[1].parent = smc91x_res; 353 smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X; 354 smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X; 355 d->smc91x = platform_device_register_full(&smc91x_devinfo); 356 357 platform_set_drvdata(dev, d); 358 359 return 0; 360 361 err_irq_alloc: 362 err_id: 363 iounmap(d->base); 364 err_ioremap: 365 kfree(d); 366 err_alloc: 367 return ret; 368 } 369 370 static int __devexit neponset_remove(struct platform_device *dev) 371 { 372 struct neponset_drvdata *d = platform_get_drvdata(dev); 373 int irq = platform_get_irq(dev, 0); 374 375 if (!IS_ERR(d->sa1111)) 376 platform_device_unregister(d->sa1111); 377 if (!IS_ERR(d->smc91x)) 378 platform_device_unregister(d->smc91x); 379 irq_set_chained_handler(irq, NULL); 380 irq_free_descs(d->irq_base, NEP_IRQ_NR); 381 nep_base = NULL; 382 iounmap(d->base); 383 kfree(d); 384 385 return 0; 386 } 387 388 #ifdef CONFIG_PM_SLEEP 389 static int neponset_suspend(struct device *dev) 390 { 391 struct neponset_drvdata *d = dev_get_drvdata(dev); 392 393 d->ncr0 = readb_relaxed(d->base + NCR_0); 394 d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0); 395 396 return 0; 397 } 398 399 static int neponset_resume(struct device *dev) 400 { 401 struct neponset_drvdata *d = dev_get_drvdata(dev); 402 403 writeb_relaxed(d->ncr0, d->base + NCR_0); 404 writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0); 405 406 return 0; 407 } 408 409 static const struct dev_pm_ops neponset_pm_ops = { 410 .suspend_noirq = neponset_suspend, 411 .resume_noirq = neponset_resume, 412 .freeze_noirq = neponset_suspend, 413 .restore_noirq = neponset_resume, 414 }; 415 #define PM_OPS &neponset_pm_ops 416 #else 417 #define PM_OPS NULL 418 #endif 419 420 static struct platform_driver neponset_device_driver = { 421 .probe = neponset_probe, 422 .remove = __devexit_p(neponset_remove), 423 .driver = { 424 .name = "neponset", 425 .owner = THIS_MODULE, 426 .pm = PM_OPS, 427 }, 428 }; 429 430 static int __init neponset_init(void) 431 { 432 return platform_driver_register(&neponset_device_driver); 433 } 434 435 subsys_initcall(neponset_init); 436