1 /* 2 * OMAP3 powerdomain definitions 3 * 4 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc. 5 * Copyright (C) 2007-2011 Nokia Corporation 6 * 7 * Paul Walmsley, Jouni Högander 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 17 #include <plat/cpu.h> 18 19 #include "powerdomain.h" 20 #include "powerdomains2xxx_3xxx_data.h" 21 22 #include "prcm-common.h" 23 #include "prm2xxx_3xxx.h" 24 #include "prm-regbits-34xx.h" 25 #include "cm2xxx_3xxx.h" 26 #include "cm-regbits-34xx.h" 27 28 /* 29 * 34XX-specific powerdomains, dependencies 30 */ 31 32 /* 33 * Powerdomains 34 */ 35 36 static struct powerdomain iva2_pwrdm = { 37 .name = "iva2_pwrdm", 38 .prcm_offs = OMAP3430_IVA2_MOD, 39 .pwrsts = PWRSTS_OFF_RET_ON, 40 .pwrsts_logic_ret = PWRSTS_OFF_RET, 41 .banks = 4, 42 .pwrsts_mem_ret = { 43 [0] = PWRSTS_OFF_RET, 44 [1] = PWRSTS_OFF_RET, 45 [2] = PWRSTS_OFF_RET, 46 [3] = PWRSTS_OFF_RET, 47 }, 48 .pwrsts_mem_on = { 49 [0] = PWRSTS_ON, 50 [1] = PWRSTS_ON, 51 [2] = PWRSTS_OFF_ON, 52 [3] = PWRSTS_ON, 53 }, 54 }; 55 56 static struct powerdomain mpu_3xxx_pwrdm = { 57 .name = "mpu_pwrdm", 58 .prcm_offs = MPU_MOD, 59 .pwrsts = PWRSTS_OFF_RET_ON, 60 .pwrsts_logic_ret = PWRSTS_OFF_RET, 61 .flags = PWRDM_HAS_MPU_QUIRK, 62 .banks = 1, 63 .pwrsts_mem_ret = { 64 [0] = PWRSTS_OFF_RET, 65 }, 66 .pwrsts_mem_on = { 67 [0] = PWRSTS_OFF_ON, 68 }, 69 }; 70 71 /* 72 * The USBTLL Save-and-Restore mechanism is broken on 73 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature 74 * needs to be disabled on these chips. 75 * Refer: 3430 errata ID i459 and 3630 errata ID i579 76 * 77 * Note: setting the SAR flag could help for errata ID i478 78 * which applies to 3430 <= ES3.1, but since the SAR feature 79 * is broken, do not use it. 80 */ 81 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { 82 .name = "core_pwrdm", 83 .prcm_offs = CORE_MOD, 84 .pwrsts = PWRSTS_OFF_RET_ON, 85 .pwrsts_logic_ret = PWRSTS_OFF_RET, 86 .banks = 2, 87 .pwrsts_mem_ret = { 88 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ 89 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ 90 }, 91 .pwrsts_mem_on = { 92 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ 93 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ 94 }, 95 }; 96 97 static struct powerdomain core_3xxx_es3_1_pwrdm = { 98 .name = "core_pwrdm", 99 .prcm_offs = CORE_MOD, 100 .pwrsts = PWRSTS_OFF_RET_ON, 101 .pwrsts_logic_ret = PWRSTS_OFF_RET, 102 /* 103 * Setting the SAR flag for errata ID i478 which applies 104 * to 3430 <= ES3.1 105 */ 106 .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ 107 .banks = 2, 108 .pwrsts_mem_ret = { 109 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ 110 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ 111 }, 112 .pwrsts_mem_on = { 113 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ 114 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ 115 }, 116 }; 117 118 static struct powerdomain dss_pwrdm = { 119 .name = "dss_pwrdm", 120 .prcm_offs = OMAP3430_DSS_MOD, 121 .pwrsts = PWRSTS_OFF_RET_ON, 122 .pwrsts_logic_ret = PWRSTS_RET, 123 .banks = 1, 124 .pwrsts_mem_ret = { 125 [0] = PWRSTS_RET, /* MEMRETSTATE */ 126 }, 127 .pwrsts_mem_on = { 128 [0] = PWRSTS_ON, /* MEMONSTATE */ 129 }, 130 }; 131 132 /* 133 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a 134 * possible SGX powerstate, the SGX device itself does not support 135 * retention. 136 */ 137 static struct powerdomain sgx_pwrdm = { 138 .name = "sgx_pwrdm", 139 .prcm_offs = OMAP3430ES2_SGX_MOD, 140 /* XXX This is accurate for 3430 SGX, but what about GFX? */ 141 .pwrsts = PWRSTS_OFF_ON, 142 .pwrsts_logic_ret = PWRSTS_RET, 143 .banks = 1, 144 .pwrsts_mem_ret = { 145 [0] = PWRSTS_RET, /* MEMRETSTATE */ 146 }, 147 .pwrsts_mem_on = { 148 [0] = PWRSTS_ON, /* MEMONSTATE */ 149 }, 150 }; 151 152 static struct powerdomain cam_pwrdm = { 153 .name = "cam_pwrdm", 154 .prcm_offs = OMAP3430_CAM_MOD, 155 .pwrsts = PWRSTS_OFF_RET_ON, 156 .pwrsts_logic_ret = PWRSTS_RET, 157 .banks = 1, 158 .pwrsts_mem_ret = { 159 [0] = PWRSTS_RET, /* MEMRETSTATE */ 160 }, 161 .pwrsts_mem_on = { 162 [0] = PWRSTS_ON, /* MEMONSTATE */ 163 }, 164 }; 165 166 static struct powerdomain per_pwrdm = { 167 .name = "per_pwrdm", 168 .prcm_offs = OMAP3430_PER_MOD, 169 .pwrsts = PWRSTS_OFF_RET_ON, 170 .pwrsts_logic_ret = PWRSTS_OFF_RET, 171 .banks = 1, 172 .pwrsts_mem_ret = { 173 [0] = PWRSTS_RET, /* MEMRETSTATE */ 174 }, 175 .pwrsts_mem_on = { 176 [0] = PWRSTS_ON, /* MEMONSTATE */ 177 }, 178 }; 179 180 static struct powerdomain emu_pwrdm = { 181 .name = "emu_pwrdm", 182 .prcm_offs = OMAP3430_EMU_MOD, 183 }; 184 185 static struct powerdomain neon_pwrdm = { 186 .name = "neon_pwrdm", 187 .prcm_offs = OMAP3430_NEON_MOD, 188 .pwrsts = PWRSTS_OFF_RET_ON, 189 .pwrsts_logic_ret = PWRSTS_RET, 190 }; 191 192 static struct powerdomain usbhost_pwrdm = { 193 .name = "usbhost_pwrdm", 194 .prcm_offs = OMAP3430ES2_USBHOST_MOD, 195 .pwrsts = PWRSTS_OFF_RET_ON, 196 .pwrsts_logic_ret = PWRSTS_RET, 197 /* 198 * REVISIT: Enabling usb host save and restore mechanism seems to 199 * leave the usb host domain permanently in ACTIVE mode after 200 * changing the usb host power domain state from OFF to active once. 201 * Disabling for now. 202 */ 203 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */ 204 .banks = 1, 205 .pwrsts_mem_ret = { 206 [0] = PWRSTS_RET, /* MEMRETSTATE */ 207 }, 208 .pwrsts_mem_on = { 209 [0] = PWRSTS_ON, /* MEMONSTATE */ 210 }, 211 }; 212 213 static struct powerdomain dpll1_pwrdm = { 214 .name = "dpll1_pwrdm", 215 .prcm_offs = MPU_MOD, 216 }; 217 218 static struct powerdomain dpll2_pwrdm = { 219 .name = "dpll2_pwrdm", 220 .prcm_offs = OMAP3430_IVA2_MOD, 221 }; 222 223 static struct powerdomain dpll3_pwrdm = { 224 .name = "dpll3_pwrdm", 225 .prcm_offs = PLL_MOD, 226 }; 227 228 static struct powerdomain dpll4_pwrdm = { 229 .name = "dpll4_pwrdm", 230 .prcm_offs = PLL_MOD, 231 }; 232 233 static struct powerdomain dpll5_pwrdm = { 234 .name = "dpll5_pwrdm", 235 .prcm_offs = PLL_MOD, 236 }; 237 238 /* As powerdomains are added or removed above, this list must also be changed */ 239 static struct powerdomain *powerdomains_omap3430_common[] __initdata = { 240 &wkup_omap2_pwrdm, 241 &iva2_pwrdm, 242 &mpu_3xxx_pwrdm, 243 &neon_pwrdm, 244 &cam_pwrdm, 245 &dss_pwrdm, 246 &per_pwrdm, 247 &emu_pwrdm, 248 &dpll1_pwrdm, 249 &dpll2_pwrdm, 250 &dpll3_pwrdm, 251 &dpll4_pwrdm, 252 NULL 253 }; 254 255 static struct powerdomain *powerdomains_omap3430es1[] __initdata = { 256 &gfx_omap2_pwrdm, 257 &core_3xxx_pre_es3_1_pwrdm, 258 NULL 259 }; 260 261 /* also includes 3630ES1.0 */ 262 static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = { 263 &core_3xxx_pre_es3_1_pwrdm, 264 &sgx_pwrdm, 265 &usbhost_pwrdm, 266 &dpll5_pwrdm, 267 NULL 268 }; 269 270 /* also includes 3630ES1.1+ */ 271 static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = { 272 &core_3xxx_es3_1_pwrdm, 273 &sgx_pwrdm, 274 &usbhost_pwrdm, 275 &dpll5_pwrdm, 276 NULL 277 }; 278 279 void __init omap3xxx_powerdomains_init(void) 280 { 281 unsigned int rev; 282 283 if (!cpu_is_omap34xx()) 284 return; 285 286 pwrdm_register_platform_funcs(&omap3_pwrdm_operations); 287 pwrdm_register_pwrdms(powerdomains_omap3430_common); 288 289 rev = omap_rev(); 290 291 if (rev == OMAP3430_REV_ES1_0) 292 pwrdm_register_pwrdms(powerdomains_omap3430es1); 293 else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 294 rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0) 295 pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0); 296 else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 || 297 rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 || 298 rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) 299 pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus); 300 else 301 WARN(1, "OMAP3 powerdomain init: unknown chip type\n"); 302 303 pwrdm_complete_init(); 304 } 305