1 /* 2 * OMAP3 powerdomain definitions 3 * 4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 5 * Copyright (C) 2007-2011 Nokia Corporation 6 * 7 * Paul Walmsley, Jouni Högander 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 17 #include "powerdomain.h" 18 #include "powerdomains2xxx_3xxx_data.h" 19 20 #include "prcm-common.h" 21 #include "prm2xxx_3xxx.h" 22 #include "prm-regbits-34xx.h" 23 #include "cm2xxx_3xxx.h" 24 #include "cm-regbits-34xx.h" 25 26 /* 27 * 34XX-specific powerdomains, dependencies 28 */ 29 30 #ifdef CONFIG_ARCH_OMAP3 31 32 /* 33 * Powerdomains 34 */ 35 36 static struct powerdomain iva2_pwrdm = { 37 .name = "iva2_pwrdm", 38 .prcm_offs = OMAP3430_IVA2_MOD, 39 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 40 .pwrsts = PWRSTS_OFF_RET_ON, 41 .pwrsts_logic_ret = PWRSTS_OFF_RET, 42 .banks = 4, 43 .pwrsts_mem_ret = { 44 [0] = PWRSTS_OFF_RET, 45 [1] = PWRSTS_OFF_RET, 46 [2] = PWRSTS_OFF_RET, 47 [3] = PWRSTS_OFF_RET, 48 }, 49 .pwrsts_mem_on = { 50 [0] = PWRSTS_ON, 51 [1] = PWRSTS_ON, 52 [2] = PWRSTS_OFF_ON, 53 [3] = PWRSTS_ON, 54 }, 55 }; 56 57 static struct powerdomain mpu_3xxx_pwrdm = { 58 .name = "mpu_pwrdm", 59 .prcm_offs = MPU_MOD, 60 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 61 .pwrsts = PWRSTS_OFF_RET_ON, 62 .pwrsts_logic_ret = PWRSTS_OFF_RET, 63 .flags = PWRDM_HAS_MPU_QUIRK, 64 .banks = 1, 65 .pwrsts_mem_ret = { 66 [0] = PWRSTS_OFF_RET, 67 }, 68 .pwrsts_mem_on = { 69 [0] = PWRSTS_OFF_ON, 70 }, 71 }; 72 73 /* 74 * The USBTLL Save-and-Restore mechanism is broken on 75 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature 76 * needs to be disabled on these chips. 77 * Refer: 3430 errata ID i459 and 3630 errata ID i579 78 * 79 * Note: setting the SAR flag could help for errata ID i478 80 * which applies to 3430 <= ES3.1, but since the SAR feature 81 * is broken, do not use it. 82 */ 83 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { 84 .name = "core_pwrdm", 85 .prcm_offs = CORE_MOD, 86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | 87 CHIP_IS_OMAP3430ES2 | 88 CHIP_IS_OMAP3430ES3_0 | 89 CHIP_IS_OMAP3630ES1), 90 .pwrsts = PWRSTS_OFF_RET_ON, 91 .pwrsts_logic_ret = PWRSTS_OFF_RET, 92 .banks = 2, 93 .pwrsts_mem_ret = { 94 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ 95 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ 96 }, 97 .pwrsts_mem_on = { 98 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ 99 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ 100 }, 101 }; 102 103 static struct powerdomain core_3xxx_es3_1_pwrdm = { 104 .name = "core_pwrdm", 105 .prcm_offs = CORE_MOD, 106 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 | 107 CHIP_GE_OMAP3630ES1_1), 108 .pwrsts = PWRSTS_OFF_RET_ON, 109 .pwrsts_logic_ret = PWRSTS_OFF_RET, 110 /* 111 * Setting the SAR flag for errata ID i478 which applies 112 * to 3430 <= ES3.1 113 */ 114 .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ 115 .banks = 2, 116 .pwrsts_mem_ret = { 117 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ 118 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ 119 }, 120 .pwrsts_mem_on = { 121 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ 122 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ 123 }, 124 }; 125 126 static struct powerdomain dss_pwrdm = { 127 .name = "dss_pwrdm", 128 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 129 .prcm_offs = OMAP3430_DSS_MOD, 130 .pwrsts = PWRSTS_OFF_RET_ON, 131 .pwrsts_logic_ret = PWRSTS_RET, 132 .banks = 1, 133 .pwrsts_mem_ret = { 134 [0] = PWRSTS_RET, /* MEMRETSTATE */ 135 }, 136 .pwrsts_mem_on = { 137 [0] = PWRSTS_ON, /* MEMONSTATE */ 138 }, 139 }; 140 141 /* 142 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a 143 * possible SGX powerstate, the SGX device itself does not support 144 * retention. 145 */ 146 static struct powerdomain sgx_pwrdm = { 147 .name = "sgx_pwrdm", 148 .prcm_offs = OMAP3430ES2_SGX_MOD, 149 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), 150 /* XXX This is accurate for 3430 SGX, but what about GFX? */ 151 .pwrsts = PWRSTS_OFF_ON, 152 .pwrsts_logic_ret = PWRSTS_RET, 153 .banks = 1, 154 .pwrsts_mem_ret = { 155 [0] = PWRSTS_RET, /* MEMRETSTATE */ 156 }, 157 .pwrsts_mem_on = { 158 [0] = PWRSTS_ON, /* MEMONSTATE */ 159 }, 160 }; 161 162 static struct powerdomain cam_pwrdm = { 163 .name = "cam_pwrdm", 164 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 165 .prcm_offs = OMAP3430_CAM_MOD, 166 .pwrsts = PWRSTS_OFF_RET_ON, 167 .pwrsts_logic_ret = PWRSTS_RET, 168 .banks = 1, 169 .pwrsts_mem_ret = { 170 [0] = PWRSTS_RET, /* MEMRETSTATE */ 171 }, 172 .pwrsts_mem_on = { 173 [0] = PWRSTS_ON, /* MEMONSTATE */ 174 }, 175 }; 176 177 static struct powerdomain per_pwrdm = { 178 .name = "per_pwrdm", 179 .prcm_offs = OMAP3430_PER_MOD, 180 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 181 .pwrsts = PWRSTS_OFF_RET_ON, 182 .pwrsts_logic_ret = PWRSTS_OFF_RET, 183 .banks = 1, 184 .pwrsts_mem_ret = { 185 [0] = PWRSTS_RET, /* MEMRETSTATE */ 186 }, 187 .pwrsts_mem_on = { 188 [0] = PWRSTS_ON, /* MEMONSTATE */ 189 }, 190 }; 191 192 static struct powerdomain emu_pwrdm = { 193 .name = "emu_pwrdm", 194 .prcm_offs = OMAP3430_EMU_MOD, 195 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 196 }; 197 198 static struct powerdomain neon_pwrdm = { 199 .name = "neon_pwrdm", 200 .prcm_offs = OMAP3430_NEON_MOD, 201 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 202 .pwrsts = PWRSTS_OFF_RET_ON, 203 .pwrsts_logic_ret = PWRSTS_RET, 204 }; 205 206 static struct powerdomain usbhost_pwrdm = { 207 .name = "usbhost_pwrdm", 208 .prcm_offs = OMAP3430ES2_USBHOST_MOD, 209 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), 210 .pwrsts = PWRSTS_OFF_RET_ON, 211 .pwrsts_logic_ret = PWRSTS_RET, 212 /* 213 * REVISIT: Enabling usb host save and restore mechanism seems to 214 * leave the usb host domain permanently in ACTIVE mode after 215 * changing the usb host power domain state from OFF to active once. 216 * Disabling for now. 217 */ 218 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */ 219 .banks = 1, 220 .pwrsts_mem_ret = { 221 [0] = PWRSTS_RET, /* MEMRETSTATE */ 222 }, 223 .pwrsts_mem_on = { 224 [0] = PWRSTS_ON, /* MEMONSTATE */ 225 }, 226 }; 227 228 static struct powerdomain dpll1_pwrdm = { 229 .name = "dpll1_pwrdm", 230 .prcm_offs = MPU_MOD, 231 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 232 }; 233 234 static struct powerdomain dpll2_pwrdm = { 235 .name = "dpll2_pwrdm", 236 .prcm_offs = OMAP3430_IVA2_MOD, 237 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 238 }; 239 240 static struct powerdomain dpll3_pwrdm = { 241 .name = "dpll3_pwrdm", 242 .prcm_offs = PLL_MOD, 243 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 244 }; 245 246 static struct powerdomain dpll4_pwrdm = { 247 .name = "dpll4_pwrdm", 248 .prcm_offs = PLL_MOD, 249 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 250 }; 251 252 static struct powerdomain dpll5_pwrdm = { 253 .name = "dpll5_pwrdm", 254 .prcm_offs = PLL_MOD, 255 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), 256 }; 257 258 /* As powerdomains are added or removed above, this list must also be changed */ 259 static struct powerdomain *powerdomains_omap3xxx[] __initdata = { 260 261 &wkup_omap2_pwrdm, 262 &gfx_omap2_pwrdm, 263 &iva2_pwrdm, 264 &mpu_3xxx_pwrdm, 265 &neon_pwrdm, 266 &core_3xxx_pre_es3_1_pwrdm, 267 &core_3xxx_es3_1_pwrdm, 268 &cam_pwrdm, 269 &dss_pwrdm, 270 &per_pwrdm, 271 &emu_pwrdm, 272 &sgx_pwrdm, 273 &usbhost_pwrdm, 274 &dpll1_pwrdm, 275 &dpll2_pwrdm, 276 &dpll3_pwrdm, 277 &dpll4_pwrdm, 278 &dpll5_pwrdm, 279 #endif 280 NULL 281 }; 282 283 284 void __init omap3xxx_powerdomains_init(void) 285 { 286 pwrdm_register_platform_funcs(&omap3_pwrdm_operations); 287 pwrdm_register_pwrdms(powerdomains_omap3xxx); 288 pwrdm_complete_init(); 289 } 290