1 /* 2 * OMAP4 CM instance functions 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2008-2011 Texas Instruments, Inc. 6 * Paul Walmsley 7 * Rajendra Nayak <rnayak@ti.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1, 14 * or CM2 hardware modules. For example, the EMU_CM CM instance is in 15 * the PRM hardware module. What a mess... 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/io.h> 23 24 #include "iomap.h" 25 #include "common.h" 26 #include "clockdomain.h" 27 #include "cm.h" 28 #include "cm1_44xx.h" 29 #include "cm2_44xx.h" 30 #include "cm44xx.h" 31 #include "cminst44xx.h" 32 #include "cm-regbits-34xx.h" 33 #include "cm-regbits-44xx.h" 34 #include "prcm44xx.h" 35 #include "prm44xx.h" 36 #include "prcm_mpu44xx.h" 37 #include "prcm-common.h" 38 39 /* 40 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: 41 * 42 * 0x0 func: Module is fully functional, including OCP 43 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep 44 * abortion 45 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if 46 * using separate functional clock 47 * 0x3 disabled: Module is disabled and cannot be accessed 48 * 49 */ 50 #define CLKCTRL_IDLEST_FUNCTIONAL 0x0 51 #define CLKCTRL_IDLEST_INTRANSITION 0x1 52 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 53 #define CLKCTRL_IDLEST_DISABLED 0x3 54 55 static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 56 57 /** 58 * omap_cm_base_init - Populates the cm partitions 59 * 60 * Populates the base addresses of the _cm_bases 61 * array used for read/write of cm module registers. 62 */ 63 void omap_cm_base_init(void) 64 { 65 _cm_bases[OMAP4430_PRM_PARTITION] = prm_base; 66 _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; 67 _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base; 68 _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; 69 } 70 71 /* Private functions */ 72 73 /** 74 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield 75 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 76 * @inst: CM instance register offset (*_INST macro) 77 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 78 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 79 * 80 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to 81 * bit 0. 82 */ 83 static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 84 { 85 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 86 v &= OMAP4430_IDLEST_MASK; 87 v >>= OMAP4430_IDLEST_SHIFT; 88 return v; 89 } 90 91 /** 92 * _is_module_ready - can module registers be accessed without causing an abort? 93 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 94 * @inst: CM instance register offset (*_INST macro) 95 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 96 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 97 * 98 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either 99 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. 100 */ 101 static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 102 { 103 u32 v; 104 105 v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs); 106 107 return (v == CLKCTRL_IDLEST_FUNCTIONAL || 108 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; 109 } 110 111 /* Public functions */ 112 113 /* Read a register in a CM instance */ 114 u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) 115 { 116 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 117 part == OMAP4430_INVALID_PRCM_PARTITION || 118 !_cm_bases[part]); 119 return readl_relaxed(_cm_bases[part] + inst + idx); 120 } 121 122 /* Write into a register in a CM instance */ 123 void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) 124 { 125 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 126 part == OMAP4430_INVALID_PRCM_PARTITION || 127 !_cm_bases[part]); 128 writel_relaxed(val, _cm_bases[part] + inst + idx); 129 } 130 131 /* Read-modify-write a register in CM1. Caller must lock */ 132 u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, 133 s16 idx) 134 { 135 u32 v; 136 137 v = omap4_cminst_read_inst_reg(part, inst, idx); 138 v &= ~mask; 139 v |= bits; 140 omap4_cminst_write_inst_reg(v, part, inst, idx); 141 142 return v; 143 } 144 145 u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 146 { 147 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); 148 } 149 150 u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 151 { 152 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); 153 } 154 155 u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) 156 { 157 u32 v; 158 159 v = omap4_cminst_read_inst_reg(part, inst, idx); 160 v &= mask; 161 v >>= __ffs(mask); 162 163 return v; 164 } 165 166 /* 167 * 168 */ 169 170 /** 171 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield 172 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) 173 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 174 * @inst: CM instance register offset (*_INST macro) 175 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 176 * 177 * @c must be the unshifted value for CLKTRCTRL - i.e., this function 178 * will handle the shift itself. 179 */ 180 static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) 181 { 182 u32 v; 183 184 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 185 v &= ~OMAP4430_CLKTRCTRL_MASK; 186 v |= c << OMAP4430_CLKTRCTRL_SHIFT; 187 omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 188 } 189 190 /** 191 * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? 192 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 193 * @inst: CM instance register offset (*_INST macro) 194 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 195 * 196 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) 197 * is in hardware-supervised idle mode, or 0 otherwise. 198 */ 199 bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) 200 { 201 u32 v; 202 203 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 204 v &= OMAP4430_CLKTRCTRL_MASK; 205 v >>= OMAP4430_CLKTRCTRL_SHIFT; 206 207 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; 208 } 209 210 /** 211 * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode 212 * @part: PRCM partition ID that the clockdomain registers exist in 213 * @inst: CM instance register offset (*_INST macro) 214 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 215 * 216 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 217 * hardware-supervised idle mode. No return value. 218 */ 219 void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) 220 { 221 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); 222 } 223 224 /** 225 * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode 226 * @part: PRCM partition ID that the clockdomain registers exist in 227 * @inst: CM instance register offset (*_INST macro) 228 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 229 * 230 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 231 * software-supervised idle mode, i.e., controlled manually by the 232 * Linux OMAP clockdomain code. No return value. 233 */ 234 void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) 235 { 236 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); 237 } 238 239 /** 240 * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle 241 * @part: PRCM partition ID that the clockdomain registers exist in 242 * @inst: CM instance register offset (*_INST macro) 243 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 244 * 245 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, 246 * waking it up. No return value. 247 */ 248 void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) 249 { 250 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); 251 } 252 253 /* 254 * 255 */ 256 257 void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs) 258 { 259 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); 260 } 261 262 /** 263 * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state 264 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 265 * @inst: CM instance register offset (*_INST macro) 266 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 267 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 268 * 269 * Wait for the module IDLEST to be functional. If the idle state is in any 270 * the non functional state (trans, idle or disabled), module and thus the 271 * sysconfig cannot be accessed and will probably lead to an "imprecise 272 * external abort" 273 */ 274 int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, 275 u16 clkctrl_offs) 276 { 277 int i = 0; 278 279 if (!clkctrl_offs) 280 return 0; 281 282 omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs), 283 MAX_MODULE_READY_TIME, i); 284 285 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 286 } 287 288 /** 289 * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled' 290 * state 291 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 292 * @inst: CM instance register offset (*_INST macro) 293 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 294 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 295 * 296 * Wait for the module IDLEST to be disabled. Some PRCM transition, 297 * like reset assertion or parent clock de-activation must wait the 298 * module to be fully disabled. 299 */ 300 int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 301 { 302 int i = 0; 303 304 if (!clkctrl_offs) 305 return 0; 306 307 omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) == 308 CLKCTRL_IDLEST_DISABLED), 309 MAX_MODULE_DISABLE_TIME, i); 310 311 return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY; 312 } 313 314 /** 315 * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL 316 * @mode: Module mode (SW or HW) 317 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 318 * @inst: CM instance register offset (*_INST macro) 319 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 320 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 321 * 322 * No return value. 323 */ 324 void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs, 325 u16 clkctrl_offs) 326 { 327 u32 v; 328 329 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 330 v &= ~OMAP4430_MODULEMODE_MASK; 331 v |= mode << OMAP4430_MODULEMODE_SHIFT; 332 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 333 } 334 335 /** 336 * omap4_cminst_module_disable - Disable the module inside CLKCTRL 337 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 338 * @inst: CM instance register offset (*_INST macro) 339 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 340 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 341 * 342 * No return value. 343 */ 344 void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, 345 u16 clkctrl_offs) 346 { 347 u32 v; 348 349 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 350 v &= ~OMAP4430_MODULEMODE_MASK; 351 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 352 } 353 354 /* 355 * Clockdomain low-level functions 356 */ 357 358 static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1, 359 struct clockdomain *clkdm2) 360 { 361 omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit), 362 clkdm1->prcm_partition, 363 clkdm1->cm_inst, clkdm1->clkdm_offs + 364 OMAP4_CM_STATICDEP); 365 return 0; 366 } 367 368 static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1, 369 struct clockdomain *clkdm2) 370 { 371 omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit), 372 clkdm1->prcm_partition, 373 clkdm1->cm_inst, clkdm1->clkdm_offs + 374 OMAP4_CM_STATICDEP); 375 return 0; 376 } 377 378 static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1, 379 struct clockdomain *clkdm2) 380 { 381 return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition, 382 clkdm1->cm_inst, 383 clkdm1->clkdm_offs + 384 OMAP4_CM_STATICDEP, 385 (1 << clkdm2->dep_bit)); 386 } 387 388 static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) 389 { 390 struct clkdm_dep *cd; 391 u32 mask = 0; 392 393 if (!clkdm->prcm_partition) 394 return 0; 395 396 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { 397 if (!cd->clkdm) 398 continue; /* only happens if data is erroneous */ 399 400 mask |= 1 << cd->clkdm->dep_bit; 401 cd->wkdep_usecount = 0; 402 } 403 404 omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, 405 clkdm->cm_inst, clkdm->clkdm_offs + 406 OMAP4_CM_STATICDEP); 407 return 0; 408 } 409 410 static int omap4_clkdm_sleep(struct clockdomain *clkdm) 411 { 412 if (clkdm->flags & CLKDM_CAN_HWSUP) 413 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 414 clkdm->cm_inst, 415 clkdm->clkdm_offs); 416 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) 417 omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, 418 clkdm->cm_inst, 419 clkdm->clkdm_offs); 420 else 421 return -EINVAL; 422 423 return 0; 424 } 425 426 static int omap4_clkdm_wakeup(struct clockdomain *clkdm) 427 { 428 omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, 429 clkdm->cm_inst, clkdm->clkdm_offs); 430 return 0; 431 } 432 433 static void omap4_clkdm_allow_idle(struct clockdomain *clkdm) 434 { 435 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 436 clkdm->cm_inst, clkdm->clkdm_offs); 437 } 438 439 static void omap4_clkdm_deny_idle(struct clockdomain *clkdm) 440 { 441 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 442 omap4_clkdm_wakeup(clkdm); 443 else 444 omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, 445 clkdm->cm_inst, 446 clkdm->clkdm_offs); 447 } 448 449 static int omap4_clkdm_clk_enable(struct clockdomain *clkdm) 450 { 451 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 452 return omap4_clkdm_wakeup(clkdm); 453 454 return 0; 455 } 456 457 static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) 458 { 459 bool hwsup = false; 460 461 if (!clkdm->prcm_partition) 462 return 0; 463 464 /* 465 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has 466 * more details on the unpleasant problem this is working 467 * around 468 */ 469 if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && 470 !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { 471 omap4_clkdm_allow_idle(clkdm); 472 return 0; 473 } 474 475 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, 476 clkdm->cm_inst, clkdm->clkdm_offs); 477 478 if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) 479 omap4_clkdm_sleep(clkdm); 480 481 return 0; 482 } 483 484 struct clkdm_ops omap4_clkdm_operations = { 485 .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, 486 .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, 487 .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep, 488 .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 489 .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep, 490 .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep, 491 .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep, 492 .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 493 .clkdm_sleep = omap4_clkdm_sleep, 494 .clkdm_wakeup = omap4_clkdm_wakeup, 495 .clkdm_allow_idle = omap4_clkdm_allow_idle, 496 .clkdm_deny_idle = omap4_clkdm_deny_idle, 497 .clkdm_clk_enable = omap4_clkdm_clk_enable, 498 .clkdm_clk_disable = omap4_clkdm_clk_disable, 499 }; 500 501 struct clkdm_ops am43xx_clkdm_operations = { 502 .clkdm_sleep = omap4_clkdm_sleep, 503 .clkdm_wakeup = omap4_clkdm_wakeup, 504 .clkdm_allow_idle = omap4_clkdm_allow_idle, 505 .clkdm_deny_idle = omap4_clkdm_deny_idle, 506 .clkdm_clk_enable = omap4_clkdm_clk_enable, 507 .clkdm_clk_disable = omap4_clkdm_clk_disable, 508 }; 509