1 /* 2 * OMAP4 CM instance functions 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2008-2011 Texas Instruments, Inc. 6 * Paul Walmsley 7 * Rajendra Nayak <rnayak@ti.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1, 14 * or CM2 hardware modules. For example, the EMU_CM CM instance is in 15 * the PRM hardware module. What a mess... 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/io.h> 23 24 #include "clockdomain.h" 25 #include "cm.h" 26 #include "cm1_44xx.h" 27 #include "cm2_44xx.h" 28 #include "cm44xx.h" 29 #include "cminst44xx.h" 30 #include "cm-regbits-34xx.h" 31 #include "prcm44xx.h" 32 #include "prm44xx.h" 33 #include "prcm_mpu44xx.h" 34 #include "prcm-common.h" 35 36 #define OMAP4430_IDLEST_SHIFT 16 37 #define OMAP4430_IDLEST_MASK (0x3 << 16) 38 #define OMAP4430_CLKTRCTRL_SHIFT 0 39 #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 40 #define OMAP4430_MODULEMODE_SHIFT 0 41 #define OMAP4430_MODULEMODE_MASK (0x3 << 0) 42 43 /* 44 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: 45 * 46 * 0x0 func: Module is fully functional, including OCP 47 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep 48 * abortion 49 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if 50 * using separate functional clock 51 * 0x3 disabled: Module is disabled and cannot be accessed 52 * 53 */ 54 #define CLKCTRL_IDLEST_FUNCTIONAL 0x0 55 #define CLKCTRL_IDLEST_INTRANSITION 0x1 56 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 57 #define CLKCTRL_IDLEST_DISABLED 0x3 58 59 static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 60 61 /** 62 * omap_cm_base_init - Populates the cm partitions 63 * 64 * Populates the base addresses of the _cm_bases 65 * array used for read/write of cm module registers. 66 */ 67 void omap_cm_base_init(void) 68 { 69 _cm_bases[OMAP4430_PRM_PARTITION] = prm_base; 70 _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; 71 _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base; 72 _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; 73 } 74 75 /* Private functions */ 76 77 /** 78 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield 79 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 80 * @inst: CM instance register offset (*_INST macro) 81 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 82 * 83 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to 84 * bit 0. 85 */ 86 static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs) 87 { 88 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 89 v &= OMAP4430_IDLEST_MASK; 90 v >>= OMAP4430_IDLEST_SHIFT; 91 return v; 92 } 93 94 /** 95 * _is_module_ready - can module registers be accessed without causing an abort? 96 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 97 * @inst: CM instance register offset (*_INST macro) 98 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 99 * 100 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either 101 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. 102 */ 103 static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs) 104 { 105 u32 v; 106 107 v = _clkctrl_idlest(part, inst, clkctrl_offs); 108 109 return (v == CLKCTRL_IDLEST_FUNCTIONAL || 110 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; 111 } 112 113 /* Public functions */ 114 115 /* Read a register in a CM instance */ 116 u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) 117 { 118 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 119 part == OMAP4430_INVALID_PRCM_PARTITION || 120 !_cm_bases[part]); 121 return readl_relaxed(_cm_bases[part] + inst + idx); 122 } 123 124 /* Write into a register in a CM instance */ 125 void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) 126 { 127 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 128 part == OMAP4430_INVALID_PRCM_PARTITION || 129 !_cm_bases[part]); 130 writel_relaxed(val, _cm_bases[part] + inst + idx); 131 } 132 133 /* Read-modify-write a register in CM1. Caller must lock */ 134 u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, 135 s16 idx) 136 { 137 u32 v; 138 139 v = omap4_cminst_read_inst_reg(part, inst, idx); 140 v &= ~mask; 141 v |= bits; 142 omap4_cminst_write_inst_reg(v, part, inst, idx); 143 144 return v; 145 } 146 147 u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 148 { 149 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); 150 } 151 152 u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 153 { 154 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); 155 } 156 157 u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) 158 { 159 u32 v; 160 161 v = omap4_cminst_read_inst_reg(part, inst, idx); 162 v &= mask; 163 v >>= __ffs(mask); 164 165 return v; 166 } 167 168 /* 169 * 170 */ 171 172 /** 173 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield 174 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) 175 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 176 * @inst: CM instance register offset (*_INST macro) 177 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 178 * 179 * @c must be the unshifted value for CLKTRCTRL - i.e., this function 180 * will handle the shift itself. 181 */ 182 static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) 183 { 184 u32 v; 185 186 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 187 v &= ~OMAP4430_CLKTRCTRL_MASK; 188 v |= c << OMAP4430_CLKTRCTRL_SHIFT; 189 omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 190 } 191 192 /** 193 * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? 194 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 195 * @inst: CM instance register offset (*_INST macro) 196 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 197 * 198 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) 199 * is in hardware-supervised idle mode, or 0 otherwise. 200 */ 201 bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) 202 { 203 u32 v; 204 205 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 206 v &= OMAP4430_CLKTRCTRL_MASK; 207 v >>= OMAP4430_CLKTRCTRL_SHIFT; 208 209 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; 210 } 211 212 /** 213 * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode 214 * @part: PRCM partition ID that the clockdomain registers exist in 215 * @inst: CM instance register offset (*_INST macro) 216 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 217 * 218 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 219 * hardware-supervised idle mode. No return value. 220 */ 221 void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) 222 { 223 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); 224 } 225 226 /** 227 * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode 228 * @part: PRCM partition ID that the clockdomain registers exist in 229 * @inst: CM instance register offset (*_INST macro) 230 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 231 * 232 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 233 * software-supervised idle mode, i.e., controlled manually by the 234 * Linux OMAP clockdomain code. No return value. 235 */ 236 void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) 237 { 238 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); 239 } 240 241 /** 242 * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle 243 * @part: PRCM partition ID that the clockdomain registers exist in 244 * @inst: CM instance register offset (*_INST macro) 245 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 246 * 247 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, 248 * waking it up. No return value. 249 */ 250 void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) 251 { 252 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); 253 } 254 255 /* 256 * 257 */ 258 259 void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs) 260 { 261 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); 262 } 263 264 /** 265 * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state 266 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 267 * @inst: CM instance register offset (*_INST macro) 268 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 269 * 270 * Wait for the module IDLEST to be functional. If the idle state is in any 271 * the non functional state (trans, idle or disabled), module and thus the 272 * sysconfig cannot be accessed and will probably lead to an "imprecise 273 * external abort" 274 */ 275 int omap4_cminst_wait_module_ready(u8 part, u16 inst, u16 clkctrl_offs) 276 { 277 int i = 0; 278 279 if (!clkctrl_offs) 280 return 0; 281 282 omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs), 283 MAX_MODULE_READY_TIME, i); 284 285 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 286 } 287 288 /** 289 * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled' 290 * state 291 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 292 * @inst: CM instance register offset (*_INST macro) 293 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 294 * 295 * Wait for the module IDLEST to be disabled. Some PRCM transition, 296 * like reset assertion or parent clock de-activation must wait the 297 * module to be fully disabled. 298 */ 299 int omap4_cminst_wait_module_idle(u8 part, u16 inst, u16 clkctrl_offs) 300 { 301 int i = 0; 302 303 if (!clkctrl_offs) 304 return 0; 305 306 omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) == 307 CLKCTRL_IDLEST_DISABLED), 308 MAX_MODULE_DISABLE_TIME, i); 309 310 return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY; 311 } 312 313 /** 314 * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL 315 * @mode: Module mode (SW or HW) 316 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 317 * @inst: CM instance register offset (*_INST macro) 318 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 319 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 320 * 321 * No return value. 322 */ 323 void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs, 324 u16 clkctrl_offs) 325 { 326 u32 v; 327 328 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 329 v &= ~OMAP4430_MODULEMODE_MASK; 330 v |= mode << OMAP4430_MODULEMODE_SHIFT; 331 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 332 } 333 334 /** 335 * omap4_cminst_module_disable - Disable the module inside CLKCTRL 336 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 337 * @inst: CM instance register offset (*_INST macro) 338 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 339 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 340 * 341 * No return value. 342 */ 343 void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, 344 u16 clkctrl_offs) 345 { 346 u32 v; 347 348 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 349 v &= ~OMAP4430_MODULEMODE_MASK; 350 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 351 } 352 353 /* 354 * Clockdomain low-level functions 355 */ 356 357 static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1, 358 struct clockdomain *clkdm2) 359 { 360 omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit), 361 clkdm1->prcm_partition, 362 clkdm1->cm_inst, clkdm1->clkdm_offs + 363 OMAP4_CM_STATICDEP); 364 return 0; 365 } 366 367 static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1, 368 struct clockdomain *clkdm2) 369 { 370 omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit), 371 clkdm1->prcm_partition, 372 clkdm1->cm_inst, clkdm1->clkdm_offs + 373 OMAP4_CM_STATICDEP); 374 return 0; 375 } 376 377 static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1, 378 struct clockdomain *clkdm2) 379 { 380 return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition, 381 clkdm1->cm_inst, 382 clkdm1->clkdm_offs + 383 OMAP4_CM_STATICDEP, 384 (1 << clkdm2->dep_bit)); 385 } 386 387 static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) 388 { 389 struct clkdm_dep *cd; 390 u32 mask = 0; 391 392 if (!clkdm->prcm_partition) 393 return 0; 394 395 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { 396 if (!cd->clkdm) 397 continue; /* only happens if data is erroneous */ 398 399 mask |= 1 << cd->clkdm->dep_bit; 400 cd->wkdep_usecount = 0; 401 } 402 403 omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, 404 clkdm->cm_inst, clkdm->clkdm_offs + 405 OMAP4_CM_STATICDEP); 406 return 0; 407 } 408 409 static int omap4_clkdm_sleep(struct clockdomain *clkdm) 410 { 411 if (clkdm->flags & CLKDM_CAN_HWSUP) 412 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 413 clkdm->cm_inst, 414 clkdm->clkdm_offs); 415 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) 416 omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, 417 clkdm->cm_inst, 418 clkdm->clkdm_offs); 419 else 420 return -EINVAL; 421 422 return 0; 423 } 424 425 static int omap4_clkdm_wakeup(struct clockdomain *clkdm) 426 { 427 omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, 428 clkdm->cm_inst, clkdm->clkdm_offs); 429 return 0; 430 } 431 432 static void omap4_clkdm_allow_idle(struct clockdomain *clkdm) 433 { 434 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 435 clkdm->cm_inst, clkdm->clkdm_offs); 436 } 437 438 static void omap4_clkdm_deny_idle(struct clockdomain *clkdm) 439 { 440 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 441 omap4_clkdm_wakeup(clkdm); 442 else 443 omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, 444 clkdm->cm_inst, 445 clkdm->clkdm_offs); 446 } 447 448 static int omap4_clkdm_clk_enable(struct clockdomain *clkdm) 449 { 450 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 451 return omap4_clkdm_wakeup(clkdm); 452 453 return 0; 454 } 455 456 static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) 457 { 458 bool hwsup = false; 459 460 if (!clkdm->prcm_partition) 461 return 0; 462 463 /* 464 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has 465 * more details on the unpleasant problem this is working 466 * around 467 */ 468 if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && 469 !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { 470 omap4_clkdm_allow_idle(clkdm); 471 return 0; 472 } 473 474 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, 475 clkdm->cm_inst, clkdm->clkdm_offs); 476 477 if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) 478 omap4_clkdm_sleep(clkdm); 479 480 return 0; 481 } 482 483 struct clkdm_ops omap4_clkdm_operations = { 484 .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, 485 .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, 486 .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep, 487 .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 488 .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep, 489 .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep, 490 .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep, 491 .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 492 .clkdm_sleep = omap4_clkdm_sleep, 493 .clkdm_wakeup = omap4_clkdm_wakeup, 494 .clkdm_allow_idle = omap4_clkdm_allow_idle, 495 .clkdm_deny_idle = omap4_clkdm_deny_idle, 496 .clkdm_clk_enable = omap4_clkdm_clk_enable, 497 .clkdm_clk_disable = omap4_clkdm_clk_disable, 498 }; 499 500 struct clkdm_ops am43xx_clkdm_operations = { 501 .clkdm_sleep = omap4_clkdm_sleep, 502 .clkdm_wakeup = omap4_clkdm_wakeup, 503 .clkdm_allow_idle = omap4_clkdm_allow_idle, 504 .clkdm_deny_idle = omap4_clkdm_deny_idle, 505 .clkdm_clk_enable = omap4_clkdm_clk_enable, 506 .clkdm_clk_disable = omap4_clkdm_clk_disable, 507 }; 508