1 /* 2 * OMAP4 CM instance functions 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2008-2011 Texas Instruments, Inc. 6 * Paul Walmsley 7 * Rajendra Nayak <rnayak@ti.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1, 14 * or CM2 hardware modules. For example, the EMU_CM CM instance is in 15 * the PRM hardware module. What a mess... 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/io.h> 23 24 #include "clockdomain.h" 25 #include "cm.h" 26 #include "cm1_44xx.h" 27 #include "cm2_44xx.h" 28 #include "cm44xx.h" 29 #include "cminst44xx.h" 30 #include "cm-regbits-34xx.h" 31 #include "prcm44xx.h" 32 #include "prm44xx.h" 33 #include "prcm_mpu44xx.h" 34 #include "prcm-common.h" 35 36 #define OMAP4430_IDLEST_SHIFT 16 37 #define OMAP4430_IDLEST_MASK (0x3 << 16) 38 #define OMAP4430_CLKTRCTRL_SHIFT 0 39 #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 40 #define OMAP4430_MODULEMODE_SHIFT 0 41 #define OMAP4430_MODULEMODE_MASK (0x3 << 0) 42 43 /* 44 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: 45 * 46 * 0x0 func: Module is fully functional, including OCP 47 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep 48 * abortion 49 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if 50 * using separate functional clock 51 * 0x3 disabled: Module is disabled and cannot be accessed 52 * 53 */ 54 #define CLKCTRL_IDLEST_FUNCTIONAL 0x0 55 #define CLKCTRL_IDLEST_INTRANSITION 0x1 56 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 57 #define CLKCTRL_IDLEST_DISABLED 0x3 58 59 static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 60 61 /** 62 * omap_cm_base_init - Populates the cm partitions 63 * 64 * Populates the base addresses of the _cm_bases 65 * array used for read/write of cm module registers. 66 */ 67 void omap_cm_base_init(void) 68 { 69 _cm_bases[OMAP4430_PRM_PARTITION] = prm_base; 70 _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; 71 _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base; 72 _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; 73 } 74 75 /* Private functions */ 76 77 /** 78 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield 79 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 80 * @inst: CM instance register offset (*_INST macro) 81 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 82 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 83 * 84 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to 85 * bit 0. 86 */ 87 static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 88 { 89 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 90 v &= OMAP4430_IDLEST_MASK; 91 v >>= OMAP4430_IDLEST_SHIFT; 92 return v; 93 } 94 95 /** 96 * _is_module_ready - can module registers be accessed without causing an abort? 97 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 98 * @inst: CM instance register offset (*_INST macro) 99 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 100 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 101 * 102 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either 103 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. 104 */ 105 static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 106 { 107 u32 v; 108 109 v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs); 110 111 return (v == CLKCTRL_IDLEST_FUNCTIONAL || 112 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; 113 } 114 115 /* Public functions */ 116 117 /* Read a register in a CM instance */ 118 u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) 119 { 120 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 121 part == OMAP4430_INVALID_PRCM_PARTITION || 122 !_cm_bases[part]); 123 return readl_relaxed(_cm_bases[part] + inst + idx); 124 } 125 126 /* Write into a register in a CM instance */ 127 void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) 128 { 129 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 130 part == OMAP4430_INVALID_PRCM_PARTITION || 131 !_cm_bases[part]); 132 writel_relaxed(val, _cm_bases[part] + inst + idx); 133 } 134 135 /* Read-modify-write a register in CM1. Caller must lock */ 136 u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, 137 s16 idx) 138 { 139 u32 v; 140 141 v = omap4_cminst_read_inst_reg(part, inst, idx); 142 v &= ~mask; 143 v |= bits; 144 omap4_cminst_write_inst_reg(v, part, inst, idx); 145 146 return v; 147 } 148 149 u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 150 { 151 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); 152 } 153 154 u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 155 { 156 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); 157 } 158 159 u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) 160 { 161 u32 v; 162 163 v = omap4_cminst_read_inst_reg(part, inst, idx); 164 v &= mask; 165 v >>= __ffs(mask); 166 167 return v; 168 } 169 170 /* 171 * 172 */ 173 174 /** 175 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield 176 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) 177 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 178 * @inst: CM instance register offset (*_INST macro) 179 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 180 * 181 * @c must be the unshifted value for CLKTRCTRL - i.e., this function 182 * will handle the shift itself. 183 */ 184 static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) 185 { 186 u32 v; 187 188 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 189 v &= ~OMAP4430_CLKTRCTRL_MASK; 190 v |= c << OMAP4430_CLKTRCTRL_SHIFT; 191 omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 192 } 193 194 /** 195 * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? 196 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 197 * @inst: CM instance register offset (*_INST macro) 198 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 199 * 200 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) 201 * is in hardware-supervised idle mode, or 0 otherwise. 202 */ 203 bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) 204 { 205 u32 v; 206 207 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 208 v &= OMAP4430_CLKTRCTRL_MASK; 209 v >>= OMAP4430_CLKTRCTRL_SHIFT; 210 211 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; 212 } 213 214 /** 215 * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode 216 * @part: PRCM partition ID that the clockdomain registers exist in 217 * @inst: CM instance register offset (*_INST macro) 218 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 219 * 220 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 221 * hardware-supervised idle mode. No return value. 222 */ 223 void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) 224 { 225 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); 226 } 227 228 /** 229 * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode 230 * @part: PRCM partition ID that the clockdomain registers exist in 231 * @inst: CM instance register offset (*_INST macro) 232 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 233 * 234 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 235 * software-supervised idle mode, i.e., controlled manually by the 236 * Linux OMAP clockdomain code. No return value. 237 */ 238 void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) 239 { 240 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); 241 } 242 243 /** 244 * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle 245 * @part: PRCM partition ID that the clockdomain registers exist in 246 * @inst: CM instance register offset (*_INST macro) 247 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 248 * 249 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, 250 * waking it up. No return value. 251 */ 252 void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) 253 { 254 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); 255 } 256 257 /* 258 * 259 */ 260 261 void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs) 262 { 263 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); 264 } 265 266 /** 267 * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state 268 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 269 * @inst: CM instance register offset (*_INST macro) 270 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 271 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 272 * 273 * Wait for the module IDLEST to be functional. If the idle state is in any 274 * the non functional state (trans, idle or disabled), module and thus the 275 * sysconfig cannot be accessed and will probably lead to an "imprecise 276 * external abort" 277 */ 278 int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, 279 u16 clkctrl_offs) 280 { 281 int i = 0; 282 283 if (!clkctrl_offs) 284 return 0; 285 286 omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs), 287 MAX_MODULE_READY_TIME, i); 288 289 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 290 } 291 292 /** 293 * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled' 294 * state 295 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 296 * @inst: CM instance register offset (*_INST macro) 297 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 298 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 299 * 300 * Wait for the module IDLEST to be disabled. Some PRCM transition, 301 * like reset assertion or parent clock de-activation must wait the 302 * module to be fully disabled. 303 */ 304 int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 305 { 306 int i = 0; 307 308 if (!clkctrl_offs) 309 return 0; 310 311 omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) == 312 CLKCTRL_IDLEST_DISABLED), 313 MAX_MODULE_DISABLE_TIME, i); 314 315 return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY; 316 } 317 318 /** 319 * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL 320 * @mode: Module mode (SW or HW) 321 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 322 * @inst: CM instance register offset (*_INST macro) 323 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 324 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 325 * 326 * No return value. 327 */ 328 void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs, 329 u16 clkctrl_offs) 330 { 331 u32 v; 332 333 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 334 v &= ~OMAP4430_MODULEMODE_MASK; 335 v |= mode << OMAP4430_MODULEMODE_SHIFT; 336 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 337 } 338 339 /** 340 * omap4_cminst_module_disable - Disable the module inside CLKCTRL 341 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 342 * @inst: CM instance register offset (*_INST macro) 343 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 344 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 345 * 346 * No return value. 347 */ 348 void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, 349 u16 clkctrl_offs) 350 { 351 u32 v; 352 353 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 354 v &= ~OMAP4430_MODULEMODE_MASK; 355 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 356 } 357 358 /* 359 * Clockdomain low-level functions 360 */ 361 362 static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1, 363 struct clockdomain *clkdm2) 364 { 365 omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit), 366 clkdm1->prcm_partition, 367 clkdm1->cm_inst, clkdm1->clkdm_offs + 368 OMAP4_CM_STATICDEP); 369 return 0; 370 } 371 372 static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1, 373 struct clockdomain *clkdm2) 374 { 375 omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit), 376 clkdm1->prcm_partition, 377 clkdm1->cm_inst, clkdm1->clkdm_offs + 378 OMAP4_CM_STATICDEP); 379 return 0; 380 } 381 382 static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1, 383 struct clockdomain *clkdm2) 384 { 385 return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition, 386 clkdm1->cm_inst, 387 clkdm1->clkdm_offs + 388 OMAP4_CM_STATICDEP, 389 (1 << clkdm2->dep_bit)); 390 } 391 392 static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) 393 { 394 struct clkdm_dep *cd; 395 u32 mask = 0; 396 397 if (!clkdm->prcm_partition) 398 return 0; 399 400 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { 401 if (!cd->clkdm) 402 continue; /* only happens if data is erroneous */ 403 404 mask |= 1 << cd->clkdm->dep_bit; 405 cd->wkdep_usecount = 0; 406 } 407 408 omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, 409 clkdm->cm_inst, clkdm->clkdm_offs + 410 OMAP4_CM_STATICDEP); 411 return 0; 412 } 413 414 static int omap4_clkdm_sleep(struct clockdomain *clkdm) 415 { 416 if (clkdm->flags & CLKDM_CAN_HWSUP) 417 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 418 clkdm->cm_inst, 419 clkdm->clkdm_offs); 420 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) 421 omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, 422 clkdm->cm_inst, 423 clkdm->clkdm_offs); 424 else 425 return -EINVAL; 426 427 return 0; 428 } 429 430 static int omap4_clkdm_wakeup(struct clockdomain *clkdm) 431 { 432 omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, 433 clkdm->cm_inst, clkdm->clkdm_offs); 434 return 0; 435 } 436 437 static void omap4_clkdm_allow_idle(struct clockdomain *clkdm) 438 { 439 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 440 clkdm->cm_inst, clkdm->clkdm_offs); 441 } 442 443 static void omap4_clkdm_deny_idle(struct clockdomain *clkdm) 444 { 445 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 446 omap4_clkdm_wakeup(clkdm); 447 else 448 omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, 449 clkdm->cm_inst, 450 clkdm->clkdm_offs); 451 } 452 453 static int omap4_clkdm_clk_enable(struct clockdomain *clkdm) 454 { 455 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 456 return omap4_clkdm_wakeup(clkdm); 457 458 return 0; 459 } 460 461 static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) 462 { 463 bool hwsup = false; 464 465 if (!clkdm->prcm_partition) 466 return 0; 467 468 /* 469 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has 470 * more details on the unpleasant problem this is working 471 * around 472 */ 473 if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && 474 !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { 475 omap4_clkdm_allow_idle(clkdm); 476 return 0; 477 } 478 479 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, 480 clkdm->cm_inst, clkdm->clkdm_offs); 481 482 if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) 483 omap4_clkdm_sleep(clkdm); 484 485 return 0; 486 } 487 488 struct clkdm_ops omap4_clkdm_operations = { 489 .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, 490 .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, 491 .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep, 492 .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 493 .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep, 494 .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep, 495 .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep, 496 .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 497 .clkdm_sleep = omap4_clkdm_sleep, 498 .clkdm_wakeup = omap4_clkdm_wakeup, 499 .clkdm_allow_idle = omap4_clkdm_allow_idle, 500 .clkdm_deny_idle = omap4_clkdm_deny_idle, 501 .clkdm_clk_enable = omap4_clkdm_clk_enable, 502 .clkdm_clk_disable = omap4_clkdm_clk_disable, 503 }; 504 505 struct clkdm_ops am43xx_clkdm_operations = { 506 .clkdm_sleep = omap4_clkdm_sleep, 507 .clkdm_wakeup = omap4_clkdm_wakeup, 508 .clkdm_allow_idle = omap4_clkdm_allow_idle, 509 .clkdm_deny_idle = omap4_clkdm_deny_idle, 510 .clkdm_clk_enable = omap4_clkdm_clk_enable, 511 .clkdm_clk_disable = omap4_clkdm_clk_disable, 512 }; 513