1 /* 2 * OMAP4 CM instance functions 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2008-2011 Texas Instruments, Inc. 6 * Paul Walmsley 7 * Rajendra Nayak <rnayak@ti.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1, 14 * or CM2 hardware modules. For example, the EMU_CM CM instance is in 15 * the PRM hardware module. What a mess... 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/io.h> 23 24 #include "clockdomain.h" 25 #include "cm.h" 26 #include "cm1_44xx.h" 27 #include "cm2_44xx.h" 28 #include "cm44xx.h" 29 #include "cm-regbits-34xx.h" 30 #include "prcm44xx.h" 31 #include "prm44xx.h" 32 #include "prcm_mpu44xx.h" 33 #include "prcm-common.h" 34 35 #define OMAP4430_IDLEST_SHIFT 16 36 #define OMAP4430_IDLEST_MASK (0x3 << 16) 37 #define OMAP4430_CLKTRCTRL_SHIFT 0 38 #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 39 #define OMAP4430_MODULEMODE_SHIFT 0 40 #define OMAP4430_MODULEMODE_MASK (0x3 << 0) 41 42 /* 43 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: 44 * 45 * 0x0 func: Module is fully functional, including OCP 46 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep 47 * abortion 48 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if 49 * using separate functional clock 50 * 0x3 disabled: Module is disabled and cannot be accessed 51 * 52 */ 53 #define CLKCTRL_IDLEST_FUNCTIONAL 0x0 54 #define CLKCTRL_IDLEST_INTRANSITION 0x1 55 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 56 #define CLKCTRL_IDLEST_DISABLED 0x3 57 58 static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 59 60 /** 61 * omap_cm_base_init - Populates the cm partitions 62 * 63 * Populates the base addresses of the _cm_bases 64 * array used for read/write of cm module registers. 65 */ 66 static void omap_cm_base_init(void) 67 { 68 _cm_bases[OMAP4430_PRM_PARTITION] = prm_base; 69 _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; 70 _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base; 71 _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; 72 } 73 74 /* Private functions */ 75 76 static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx); 77 78 /** 79 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield 80 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 81 * @inst: CM instance register offset (*_INST macro) 82 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 83 * 84 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to 85 * bit 0. 86 */ 87 static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs) 88 { 89 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 90 v &= OMAP4430_IDLEST_MASK; 91 v >>= OMAP4430_IDLEST_SHIFT; 92 return v; 93 } 94 95 /** 96 * _is_module_ready - can module registers be accessed without causing an abort? 97 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 98 * @inst: CM instance register offset (*_INST macro) 99 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 100 * 101 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either 102 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. 103 */ 104 static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs) 105 { 106 u32 v; 107 108 v = _clkctrl_idlest(part, inst, clkctrl_offs); 109 110 return (v == CLKCTRL_IDLEST_FUNCTIONAL || 111 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; 112 } 113 114 /* Read a register in a CM instance */ 115 static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) 116 { 117 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 118 part == OMAP4430_INVALID_PRCM_PARTITION || 119 !_cm_bases[part]); 120 return readl_relaxed(_cm_bases[part] + inst + idx); 121 } 122 123 /* Write into a register in a CM instance */ 124 static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) 125 { 126 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 127 part == OMAP4430_INVALID_PRCM_PARTITION || 128 !_cm_bases[part]); 129 writel_relaxed(val, _cm_bases[part] + inst + idx); 130 } 131 132 /* Read-modify-write a register in CM1. Caller must lock */ 133 static u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, 134 s16 idx) 135 { 136 u32 v; 137 138 v = omap4_cminst_read_inst_reg(part, inst, idx); 139 v &= ~mask; 140 v |= bits; 141 omap4_cminst_write_inst_reg(v, part, inst, idx); 142 143 return v; 144 } 145 146 static u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 147 { 148 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); 149 } 150 151 static u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, 152 s16 idx) 153 { 154 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); 155 } 156 157 static u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) 158 { 159 u32 v; 160 161 v = omap4_cminst_read_inst_reg(part, inst, idx); 162 v &= mask; 163 v >>= __ffs(mask); 164 165 return v; 166 } 167 168 /* 169 * 170 */ 171 172 /** 173 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield 174 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) 175 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 176 * @inst: CM instance register offset (*_INST macro) 177 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 178 * 179 * @c must be the unshifted value for CLKTRCTRL - i.e., this function 180 * will handle the shift itself. 181 */ 182 static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) 183 { 184 u32 v; 185 186 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 187 v &= ~OMAP4430_CLKTRCTRL_MASK; 188 v |= c << OMAP4430_CLKTRCTRL_SHIFT; 189 omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 190 } 191 192 /** 193 * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? 194 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 195 * @inst: CM instance register offset (*_INST macro) 196 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 197 * 198 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) 199 * is in hardware-supervised idle mode, or 0 otherwise. 200 */ 201 static bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) 202 { 203 u32 v; 204 205 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 206 v &= OMAP4430_CLKTRCTRL_MASK; 207 v >>= OMAP4430_CLKTRCTRL_SHIFT; 208 209 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; 210 } 211 212 /** 213 * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode 214 * @part: PRCM partition ID that the clockdomain registers exist in 215 * @inst: CM instance register offset (*_INST macro) 216 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 217 * 218 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 219 * hardware-supervised idle mode. No return value. 220 */ 221 static void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) 222 { 223 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); 224 } 225 226 /** 227 * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode 228 * @part: PRCM partition ID that the clockdomain registers exist in 229 * @inst: CM instance register offset (*_INST macro) 230 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 231 * 232 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 233 * software-supervised idle mode, i.e., controlled manually by the 234 * Linux OMAP clockdomain code. No return value. 235 */ 236 static void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) 237 { 238 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); 239 } 240 241 /** 242 * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle 243 * @part: PRCM partition ID that the clockdomain registers exist in 244 * @inst: CM instance register offset (*_INST macro) 245 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 246 * 247 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, 248 * waking it up. No return value. 249 */ 250 static void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) 251 { 252 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); 253 } 254 255 /* 256 * 257 */ 258 259 static void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs) 260 { 261 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); 262 } 263 264 /** 265 * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state 266 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 267 * @inst: CM instance register offset (*_INST macro) 268 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 269 * @bit_shift: bit shift for the register, ignored for OMAP4+ 270 * 271 * Wait for the module IDLEST to be functional. If the idle state is in any 272 * the non functional state (trans, idle or disabled), module and thus the 273 * sysconfig cannot be accessed and will probably lead to an "imprecise 274 * external abort" 275 */ 276 static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, 277 u8 bit_shift) 278 { 279 int i = 0; 280 281 if (!clkctrl_offs) 282 return 0; 283 284 omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs), 285 MAX_MODULE_READY_TIME, i); 286 287 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 288 } 289 290 /** 291 * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled' 292 * state 293 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 294 * @inst: CM instance register offset (*_INST macro) 295 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 296 * @bit_shift: Bit shift for the register, ignored for OMAP4+ 297 * 298 * Wait for the module IDLEST to be disabled. Some PRCM transition, 299 * like reset assertion or parent clock de-activation must wait the 300 * module to be fully disabled. 301 */ 302 static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, 303 u8 bit_shift) 304 { 305 int i = 0; 306 307 if (!clkctrl_offs) 308 return 0; 309 310 omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) == 311 CLKCTRL_IDLEST_DISABLED), 312 MAX_MODULE_DISABLE_TIME, i); 313 314 return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY; 315 } 316 317 /** 318 * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL 319 * @mode: Module mode (SW or HW) 320 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 321 * @inst: CM instance register offset (*_INST macro) 322 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 323 * 324 * No return value. 325 */ 326 static void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, 327 u16 clkctrl_offs) 328 { 329 u32 v; 330 331 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 332 v &= ~OMAP4430_MODULEMODE_MASK; 333 v |= mode << OMAP4430_MODULEMODE_SHIFT; 334 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 335 } 336 337 /** 338 * omap4_cminst_module_disable - Disable the module inside CLKCTRL 339 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 340 * @inst: CM instance register offset (*_INST macro) 341 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 342 * 343 * No return value. 344 */ 345 static void omap4_cminst_module_disable(u8 part, u16 inst, u16 clkctrl_offs) 346 { 347 u32 v; 348 349 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 350 v &= ~OMAP4430_MODULEMODE_MASK; 351 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 352 } 353 354 /* 355 * Clockdomain low-level functions 356 */ 357 358 static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1, 359 struct clockdomain *clkdm2) 360 { 361 omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit), 362 clkdm1->prcm_partition, 363 clkdm1->cm_inst, clkdm1->clkdm_offs + 364 OMAP4_CM_STATICDEP); 365 return 0; 366 } 367 368 static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1, 369 struct clockdomain *clkdm2) 370 { 371 omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit), 372 clkdm1->prcm_partition, 373 clkdm1->cm_inst, clkdm1->clkdm_offs + 374 OMAP4_CM_STATICDEP); 375 return 0; 376 } 377 378 static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1, 379 struct clockdomain *clkdm2) 380 { 381 return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition, 382 clkdm1->cm_inst, 383 clkdm1->clkdm_offs + 384 OMAP4_CM_STATICDEP, 385 (1 << clkdm2->dep_bit)); 386 } 387 388 static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) 389 { 390 struct clkdm_dep *cd; 391 u32 mask = 0; 392 393 if (!clkdm->prcm_partition) 394 return 0; 395 396 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { 397 if (!cd->clkdm) 398 continue; /* only happens if data is erroneous */ 399 400 mask |= 1 << cd->clkdm->dep_bit; 401 cd->wkdep_usecount = 0; 402 } 403 404 omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, 405 clkdm->cm_inst, clkdm->clkdm_offs + 406 OMAP4_CM_STATICDEP); 407 return 0; 408 } 409 410 static int omap4_clkdm_sleep(struct clockdomain *clkdm) 411 { 412 if (clkdm->flags & CLKDM_CAN_HWSUP) 413 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 414 clkdm->cm_inst, 415 clkdm->clkdm_offs); 416 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) 417 omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, 418 clkdm->cm_inst, 419 clkdm->clkdm_offs); 420 else 421 return -EINVAL; 422 423 return 0; 424 } 425 426 static int omap4_clkdm_wakeup(struct clockdomain *clkdm) 427 { 428 omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, 429 clkdm->cm_inst, clkdm->clkdm_offs); 430 return 0; 431 } 432 433 static void omap4_clkdm_allow_idle(struct clockdomain *clkdm) 434 { 435 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 436 clkdm->cm_inst, clkdm->clkdm_offs); 437 } 438 439 static void omap4_clkdm_deny_idle(struct clockdomain *clkdm) 440 { 441 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 442 omap4_clkdm_wakeup(clkdm); 443 else 444 omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, 445 clkdm->cm_inst, 446 clkdm->clkdm_offs); 447 } 448 449 static int omap4_clkdm_clk_enable(struct clockdomain *clkdm) 450 { 451 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 452 return omap4_clkdm_wakeup(clkdm); 453 454 return 0; 455 } 456 457 static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) 458 { 459 bool hwsup = false; 460 461 if (!clkdm->prcm_partition) 462 return 0; 463 464 /* 465 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has 466 * more details on the unpleasant problem this is working 467 * around 468 */ 469 if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && 470 !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { 471 omap4_clkdm_allow_idle(clkdm); 472 return 0; 473 } 474 475 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, 476 clkdm->cm_inst, clkdm->clkdm_offs); 477 478 if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) 479 omap4_clkdm_sleep(clkdm); 480 481 return 0; 482 } 483 484 struct clkdm_ops omap4_clkdm_operations = { 485 .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, 486 .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, 487 .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep, 488 .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 489 .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep, 490 .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep, 491 .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep, 492 .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 493 .clkdm_sleep = omap4_clkdm_sleep, 494 .clkdm_wakeup = omap4_clkdm_wakeup, 495 .clkdm_allow_idle = omap4_clkdm_allow_idle, 496 .clkdm_deny_idle = omap4_clkdm_deny_idle, 497 .clkdm_clk_enable = omap4_clkdm_clk_enable, 498 .clkdm_clk_disable = omap4_clkdm_clk_disable, 499 }; 500 501 struct clkdm_ops am43xx_clkdm_operations = { 502 .clkdm_sleep = omap4_clkdm_sleep, 503 .clkdm_wakeup = omap4_clkdm_wakeup, 504 .clkdm_allow_idle = omap4_clkdm_allow_idle, 505 .clkdm_deny_idle = omap4_clkdm_deny_idle, 506 .clkdm_clk_enable = omap4_clkdm_clk_enable, 507 .clkdm_clk_disable = omap4_clkdm_clk_disable, 508 }; 509 510 static struct cm_ll_data omap4xxx_cm_ll_data = { 511 .wait_module_ready = &omap4_cminst_wait_module_ready, 512 .wait_module_idle = &omap4_cminst_wait_module_idle, 513 .module_enable = &omap4_cminst_module_enable, 514 .module_disable = &omap4_cminst_module_disable, 515 }; 516 517 int __init omap4_cm_init(const struct omap_prcm_init_data *data) 518 { 519 omap_cm_base_init(); 520 521 return cm_register(&omap4xxx_cm_ll_data); 522 } 523 524 static void __exit omap4_cm_exit(void) 525 { 526 cm_unregister(&omap4xxx_cm_ll_data); 527 } 528 __exitcall(omap4_cm_exit); 529