1 /* 2 * OMAP4 CM instance functions 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2008-2011 Texas Instruments, Inc. 6 * Paul Walmsley 7 * Rajendra Nayak <rnayak@ti.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1, 14 * or CM2 hardware modules. For example, the EMU_CM CM instance is in 15 * the PRM hardware module. What a mess... 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/io.h> 23 24 #include "clockdomain.h" 25 #include "cm.h" 26 #include "cm1_44xx.h" 27 #include "cm2_44xx.h" 28 #include "cm44xx.h" 29 #include "cm-regbits-34xx.h" 30 #include "prcm44xx.h" 31 #include "prm44xx.h" 32 #include "prcm_mpu44xx.h" 33 #include "prcm-common.h" 34 35 #define OMAP4430_IDLEST_SHIFT 16 36 #define OMAP4430_IDLEST_MASK (0x3 << 16) 37 #define OMAP4430_CLKTRCTRL_SHIFT 0 38 #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 39 #define OMAP4430_MODULEMODE_SHIFT 0 40 #define OMAP4430_MODULEMODE_MASK (0x3 << 0) 41 42 /* 43 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: 44 * 45 * 0x0 func: Module is fully functional, including OCP 46 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep 47 * abortion 48 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if 49 * using separate functional clock 50 * 0x3 disabled: Module is disabled and cannot be accessed 51 * 52 */ 53 #define CLKCTRL_IDLEST_FUNCTIONAL 0x0 54 #define CLKCTRL_IDLEST_INTRANSITION 0x1 55 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 56 #define CLKCTRL_IDLEST_DISABLED 0x3 57 58 static struct omap_domain_base _cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 59 60 /** 61 * omap_cm_base_init - Populates the cm partitions 62 * 63 * Populates the base addresses of the _cm_bases 64 * array used for read/write of cm module registers. 65 */ 66 static void omap_cm_base_init(void) 67 { 68 memcpy(&_cm_bases[OMAP4430_PRM_PARTITION], &prm_base, sizeof(prm_base)); 69 memcpy(&_cm_bases[OMAP4430_CM1_PARTITION], &cm_base, sizeof(cm_base)); 70 memcpy(&_cm_bases[OMAP4430_CM2_PARTITION], &cm2_base, sizeof(cm2_base)); 71 memcpy(&_cm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base, 72 sizeof(prcm_mpu_base)); 73 } 74 75 /* Private functions */ 76 77 static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx); 78 79 /** 80 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield 81 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 82 * @inst: CM instance register offset (*_INST macro) 83 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 84 * 85 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to 86 * bit 0. 87 */ 88 static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs) 89 { 90 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 91 v &= OMAP4430_IDLEST_MASK; 92 v >>= OMAP4430_IDLEST_SHIFT; 93 return v; 94 } 95 96 /** 97 * _is_module_ready - can module registers be accessed without causing an abort? 98 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 99 * @inst: CM instance register offset (*_INST macro) 100 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 101 * 102 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either 103 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. 104 */ 105 static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs) 106 { 107 u32 v; 108 109 v = _clkctrl_idlest(part, inst, clkctrl_offs); 110 111 return (v == CLKCTRL_IDLEST_FUNCTIONAL || 112 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; 113 } 114 115 /* Read a register in a CM instance */ 116 static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) 117 { 118 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 119 part == OMAP4430_INVALID_PRCM_PARTITION || 120 !_cm_bases[part].va); 121 return readl_relaxed(_cm_bases[part].va + inst + idx); 122 } 123 124 /* Write into a register in a CM instance */ 125 static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) 126 { 127 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 128 part == OMAP4430_INVALID_PRCM_PARTITION || 129 !_cm_bases[part].va); 130 writel_relaxed(val, _cm_bases[part].va + inst + idx); 131 } 132 133 /* Read-modify-write a register in CM1. Caller must lock */ 134 static u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, 135 s16 idx) 136 { 137 u32 v; 138 139 v = omap4_cminst_read_inst_reg(part, inst, idx); 140 v &= ~mask; 141 v |= bits; 142 omap4_cminst_write_inst_reg(v, part, inst, idx); 143 144 return v; 145 } 146 147 static u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 148 { 149 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); 150 } 151 152 static u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, 153 s16 idx) 154 { 155 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); 156 } 157 158 static u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) 159 { 160 u32 v; 161 162 v = omap4_cminst_read_inst_reg(part, inst, idx); 163 v &= mask; 164 v >>= __ffs(mask); 165 166 return v; 167 } 168 169 /* 170 * 171 */ 172 173 /** 174 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield 175 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) 176 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 177 * @inst: CM instance register offset (*_INST macro) 178 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 179 * 180 * @c must be the unshifted value for CLKTRCTRL - i.e., this function 181 * will handle the shift itself. 182 */ 183 static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) 184 { 185 u32 v; 186 187 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 188 v &= ~OMAP4430_CLKTRCTRL_MASK; 189 v |= c << OMAP4430_CLKTRCTRL_SHIFT; 190 omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 191 } 192 193 /** 194 * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? 195 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 196 * @inst: CM instance register offset (*_INST macro) 197 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 198 * 199 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) 200 * is in hardware-supervised idle mode, or 0 otherwise. 201 */ 202 static bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) 203 { 204 u32 v; 205 206 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 207 v &= OMAP4430_CLKTRCTRL_MASK; 208 v >>= OMAP4430_CLKTRCTRL_SHIFT; 209 210 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; 211 } 212 213 /** 214 * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode 215 * @part: PRCM partition ID that the clockdomain registers exist in 216 * @inst: CM instance register offset (*_INST macro) 217 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 218 * 219 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 220 * hardware-supervised idle mode. No return value. 221 */ 222 static void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) 223 { 224 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); 225 } 226 227 /** 228 * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode 229 * @part: PRCM partition ID that the clockdomain registers exist in 230 * @inst: CM instance register offset (*_INST macro) 231 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 232 * 233 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 234 * software-supervised idle mode, i.e., controlled manually by the 235 * Linux OMAP clockdomain code. No return value. 236 */ 237 static void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) 238 { 239 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); 240 } 241 242 /** 243 * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle 244 * @part: PRCM partition ID that the clockdomain registers exist in 245 * @inst: CM instance register offset (*_INST macro) 246 * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 247 * 248 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, 249 * waking it up. No return value. 250 */ 251 static void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) 252 { 253 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); 254 } 255 256 /* 257 * 258 */ 259 260 static void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs) 261 { 262 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); 263 } 264 265 /** 266 * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state 267 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 268 * @inst: CM instance register offset (*_INST macro) 269 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 270 * @bit_shift: bit shift for the register, ignored for OMAP4+ 271 * 272 * Wait for the module IDLEST to be functional. If the idle state is in any 273 * the non functional state (trans, idle or disabled), module and thus the 274 * sysconfig cannot be accessed and will probably lead to an "imprecise 275 * external abort" 276 */ 277 static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, 278 u8 bit_shift) 279 { 280 int i = 0; 281 282 omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs), 283 MAX_MODULE_READY_TIME, i); 284 285 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 286 } 287 288 /** 289 * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled' 290 * state 291 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 292 * @inst: CM instance register offset (*_INST macro) 293 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 294 * @bit_shift: Bit shift for the register, ignored for OMAP4+ 295 * 296 * Wait for the module IDLEST to be disabled. Some PRCM transition, 297 * like reset assertion or parent clock de-activation must wait the 298 * module to be fully disabled. 299 */ 300 static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, 301 u8 bit_shift) 302 { 303 int i = 0; 304 305 omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) == 306 CLKCTRL_IDLEST_DISABLED), 307 MAX_MODULE_DISABLE_TIME, i); 308 309 return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY; 310 } 311 312 /** 313 * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL 314 * @mode: Module mode (SW or HW) 315 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 316 * @inst: CM instance register offset (*_INST macro) 317 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 318 * 319 * No return value. 320 */ 321 static void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, 322 u16 clkctrl_offs) 323 { 324 u32 v; 325 326 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 327 v &= ~OMAP4430_MODULEMODE_MASK; 328 v |= mode << OMAP4430_MODULEMODE_SHIFT; 329 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 330 } 331 332 /** 333 * omap4_cminst_module_disable - Disable the module inside CLKCTRL 334 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 335 * @inst: CM instance register offset (*_INST macro) 336 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 337 * 338 * No return value. 339 */ 340 static void omap4_cminst_module_disable(u8 part, u16 inst, u16 clkctrl_offs) 341 { 342 u32 v; 343 344 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 345 v &= ~OMAP4430_MODULEMODE_MASK; 346 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 347 } 348 349 /* 350 * Clockdomain low-level functions 351 */ 352 353 static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1, 354 struct clockdomain *clkdm2) 355 { 356 omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit), 357 clkdm1->prcm_partition, 358 clkdm1->cm_inst, clkdm1->clkdm_offs + 359 OMAP4_CM_STATICDEP); 360 return 0; 361 } 362 363 static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1, 364 struct clockdomain *clkdm2) 365 { 366 omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit), 367 clkdm1->prcm_partition, 368 clkdm1->cm_inst, clkdm1->clkdm_offs + 369 OMAP4_CM_STATICDEP); 370 return 0; 371 } 372 373 static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1, 374 struct clockdomain *clkdm2) 375 { 376 return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition, 377 clkdm1->cm_inst, 378 clkdm1->clkdm_offs + 379 OMAP4_CM_STATICDEP, 380 (1 << clkdm2->dep_bit)); 381 } 382 383 static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) 384 { 385 struct clkdm_dep *cd; 386 u32 mask = 0; 387 388 if (!clkdm->prcm_partition) 389 return 0; 390 391 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { 392 if (!cd->clkdm) 393 continue; /* only happens if data is erroneous */ 394 395 mask |= 1 << cd->clkdm->dep_bit; 396 cd->wkdep_usecount = 0; 397 } 398 399 omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, 400 clkdm->cm_inst, clkdm->clkdm_offs + 401 OMAP4_CM_STATICDEP); 402 return 0; 403 } 404 405 static int omap4_clkdm_sleep(struct clockdomain *clkdm) 406 { 407 if (clkdm->flags & CLKDM_CAN_HWSUP) 408 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 409 clkdm->cm_inst, 410 clkdm->clkdm_offs); 411 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) 412 omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, 413 clkdm->cm_inst, 414 clkdm->clkdm_offs); 415 else 416 return -EINVAL; 417 418 return 0; 419 } 420 421 static int omap4_clkdm_wakeup(struct clockdomain *clkdm) 422 { 423 omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, 424 clkdm->cm_inst, clkdm->clkdm_offs); 425 return 0; 426 } 427 428 static void omap4_clkdm_allow_idle(struct clockdomain *clkdm) 429 { 430 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 431 clkdm->cm_inst, clkdm->clkdm_offs); 432 } 433 434 static void omap4_clkdm_deny_idle(struct clockdomain *clkdm) 435 { 436 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 437 omap4_clkdm_wakeup(clkdm); 438 else 439 omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, 440 clkdm->cm_inst, 441 clkdm->clkdm_offs); 442 } 443 444 static int omap4_clkdm_clk_enable(struct clockdomain *clkdm) 445 { 446 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 447 return omap4_clkdm_wakeup(clkdm); 448 449 return 0; 450 } 451 452 static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) 453 { 454 bool hwsup = false; 455 456 if (!clkdm->prcm_partition) 457 return 0; 458 459 /* 460 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has 461 * more details on the unpleasant problem this is working 462 * around 463 */ 464 if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && 465 !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { 466 omap4_clkdm_allow_idle(clkdm); 467 return 0; 468 } 469 470 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, 471 clkdm->cm_inst, clkdm->clkdm_offs); 472 473 if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) 474 omap4_clkdm_sleep(clkdm); 475 476 return 0; 477 } 478 479 static u32 omap4_cminst_xlate_clkctrl(u8 part, u16 inst, u16 offset) 480 { 481 return _cm_bases[part].pa + inst + offset; 482 } 483 484 struct clkdm_ops omap4_clkdm_operations = { 485 .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, 486 .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, 487 .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep, 488 .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 489 .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep, 490 .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep, 491 .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep, 492 .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 493 .clkdm_sleep = omap4_clkdm_sleep, 494 .clkdm_wakeup = omap4_clkdm_wakeup, 495 .clkdm_allow_idle = omap4_clkdm_allow_idle, 496 .clkdm_deny_idle = omap4_clkdm_deny_idle, 497 .clkdm_clk_enable = omap4_clkdm_clk_enable, 498 .clkdm_clk_disable = omap4_clkdm_clk_disable, 499 }; 500 501 struct clkdm_ops am43xx_clkdm_operations = { 502 .clkdm_sleep = omap4_clkdm_sleep, 503 .clkdm_wakeup = omap4_clkdm_wakeup, 504 .clkdm_allow_idle = omap4_clkdm_allow_idle, 505 .clkdm_deny_idle = omap4_clkdm_deny_idle, 506 .clkdm_clk_enable = omap4_clkdm_clk_enable, 507 .clkdm_clk_disable = omap4_clkdm_clk_disable, 508 }; 509 510 static struct cm_ll_data omap4xxx_cm_ll_data = { 511 .wait_module_ready = &omap4_cminst_wait_module_ready, 512 .wait_module_idle = &omap4_cminst_wait_module_idle, 513 .module_enable = &omap4_cminst_module_enable, 514 .module_disable = &omap4_cminst_module_disable, 515 .xlate_clkctrl = &omap4_cminst_xlate_clkctrl, 516 }; 517 518 int __init omap4_cm_init(const struct omap_prcm_init_data *data) 519 { 520 omap_cm_base_init(); 521 522 return cm_register(&omap4xxx_cm_ll_data); 523 } 524 525 static void __exit omap4_cm_exit(void) 526 { 527 cm_unregister(&omap4xxx_cm_ll_data); 528 } 529 __exitcall(omap4_cm_exit); 530