12ace831fSPaul Walmsley /* 22ace831fSPaul Walmsley * OMAP4 CM instance functions 32ace831fSPaul Walmsley * 42ace831fSPaul Walmsley * Copyright (C) 2009 Nokia Corporation 5d0f0631dSBenoit Cousson * Copyright (C) 2011 Texas Instruments, Inc. 62ace831fSPaul Walmsley * Paul Walmsley 72ace831fSPaul Walmsley * 82ace831fSPaul Walmsley * This program is free software; you can redistribute it and/or modify 92ace831fSPaul Walmsley * it under the terms of the GNU General Public License version 2 as 102ace831fSPaul Walmsley * published by the Free Software Foundation. 112ace831fSPaul Walmsley * 122ace831fSPaul Walmsley * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1, 132ace831fSPaul Walmsley * or CM2 hardware modules. For example, the EMU_CM CM instance is in 142ace831fSPaul Walmsley * the PRM hardware module. What a mess... 152ace831fSPaul Walmsley */ 162ace831fSPaul Walmsley 172ace831fSPaul Walmsley #include <linux/kernel.h> 182ace831fSPaul Walmsley #include <linux/types.h> 192ace831fSPaul Walmsley #include <linux/errno.h> 202ace831fSPaul Walmsley #include <linux/err.h> 212ace831fSPaul Walmsley #include <linux/io.h> 222ace831fSPaul Walmsley 23ee0839c2STony Lindgren #include "iomap.h" 244e65331cSTony Lindgren #include "common.h" 252ace831fSPaul Walmsley #include "cm.h" 262ace831fSPaul Walmsley #include "cm1_44xx.h" 272ace831fSPaul Walmsley #include "cm2_44xx.h" 282ace831fSPaul Walmsley #include "cm44xx.h" 292ace831fSPaul Walmsley #include "cminst44xx.h" 30bd2122caSPaul Walmsley #include "cm-regbits-34xx.h" 312ace831fSPaul Walmsley #include "cm-regbits-44xx.h" 322ace831fSPaul Walmsley #include "prcm44xx.h" 332ace831fSPaul Walmsley #include "prm44xx.h" 342ace831fSPaul Walmsley #include "prcm_mpu44xx.h" 35610eb8c2SR Sricharan #include "prcm-common.h" 362ace831fSPaul Walmsley 37d0f0631dSBenoit Cousson /* 38d0f0631dSBenoit Cousson * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: 39d0f0631dSBenoit Cousson * 40d0f0631dSBenoit Cousson * 0x0 func: Module is fully functional, including OCP 41d0f0631dSBenoit Cousson * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep 42d0f0631dSBenoit Cousson * abortion 43d0f0631dSBenoit Cousson * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if 44d0f0631dSBenoit Cousson * using separate functional clock 45d0f0631dSBenoit Cousson * 0x3 disabled: Module is disabled and cannot be accessed 46d0f0631dSBenoit Cousson * 47d0f0631dSBenoit Cousson */ 48d0f0631dSBenoit Cousson #define CLKCTRL_IDLEST_FUNCTIONAL 0x0 49d0f0631dSBenoit Cousson #define CLKCTRL_IDLEST_INTRANSITION 0x1 50d0f0631dSBenoit Cousson #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 51d0f0631dSBenoit Cousson #define CLKCTRL_IDLEST_DISABLED 0x3 52d0f0631dSBenoit Cousson 53610eb8c2SR Sricharan static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 54610eb8c2SR Sricharan 55610eb8c2SR Sricharan /** 56610eb8c2SR Sricharan * omap_cm_base_init - Populates the cm partitions 57610eb8c2SR Sricharan * 58610eb8c2SR Sricharan * Populates the base addresses of the _cm_bases 59610eb8c2SR Sricharan * array used for read/write of cm module registers. 60610eb8c2SR Sricharan */ 61610eb8c2SR Sricharan void omap_cm_base_init(void) 62610eb8c2SR Sricharan { 63610eb8c2SR Sricharan _cm_bases[OMAP4430_PRM_PARTITION] = prm_base; 64610eb8c2SR Sricharan _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; 65610eb8c2SR Sricharan _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base; 66610eb8c2SR Sricharan _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; 67610eb8c2SR Sricharan } 682ace831fSPaul Walmsley 69d0f0631dSBenoit Cousson /* Private functions */ 70d0f0631dSBenoit Cousson 71d0f0631dSBenoit Cousson /** 72d0f0631dSBenoit Cousson * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield 73d0f0631dSBenoit Cousson * @part: PRCM partition ID that the CM_CLKCTRL register exists in 74d0f0631dSBenoit Cousson * @inst: CM instance register offset (*_INST macro) 75d0f0631dSBenoit Cousson * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 76d0f0631dSBenoit Cousson * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 77d0f0631dSBenoit Cousson * 78d0f0631dSBenoit Cousson * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to 79d0f0631dSBenoit Cousson * bit 0. 80d0f0631dSBenoit Cousson */ 81d0f0631dSBenoit Cousson static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 82d0f0631dSBenoit Cousson { 83d0f0631dSBenoit Cousson u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 84d0f0631dSBenoit Cousson v &= OMAP4430_IDLEST_MASK; 85d0f0631dSBenoit Cousson v >>= OMAP4430_IDLEST_SHIFT; 86d0f0631dSBenoit Cousson return v; 87d0f0631dSBenoit Cousson } 88d0f0631dSBenoit Cousson 89d0f0631dSBenoit Cousson /** 90d0f0631dSBenoit Cousson * _is_module_ready - can module registers be accessed without causing an abort? 91d0f0631dSBenoit Cousson * @part: PRCM partition ID that the CM_CLKCTRL register exists in 92d0f0631dSBenoit Cousson * @inst: CM instance register offset (*_INST macro) 93d0f0631dSBenoit Cousson * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 94d0f0631dSBenoit Cousson * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 95d0f0631dSBenoit Cousson * 96d0f0631dSBenoit Cousson * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either 97d0f0631dSBenoit Cousson * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. 98d0f0631dSBenoit Cousson */ 99d0f0631dSBenoit Cousson static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 100d0f0631dSBenoit Cousson { 101d0f0631dSBenoit Cousson u32 v; 102d0f0631dSBenoit Cousson 103d0f0631dSBenoit Cousson v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs); 104d0f0631dSBenoit Cousson 105d0f0631dSBenoit Cousson return (v == CLKCTRL_IDLEST_FUNCTIONAL || 106d0f0631dSBenoit Cousson v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; 107d0f0631dSBenoit Cousson } 108d0f0631dSBenoit Cousson 109d0f0631dSBenoit Cousson /* Public functions */ 110d0f0631dSBenoit Cousson 1112ace831fSPaul Walmsley /* Read a register in a CM instance */ 1122ace831fSPaul Walmsley u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx) 1132ace831fSPaul Walmsley { 1142ace831fSPaul Walmsley BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 1152ace831fSPaul Walmsley part == OMAP4430_INVALID_PRCM_PARTITION || 1162ace831fSPaul Walmsley !_cm_bases[part]); 117610eb8c2SR Sricharan return __raw_readl(_cm_bases[part] + inst + idx); 1182ace831fSPaul Walmsley } 1192ace831fSPaul Walmsley 1202ace831fSPaul Walmsley /* Write into a register in a CM instance */ 1212ace831fSPaul Walmsley void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) 1222ace831fSPaul Walmsley { 1232ace831fSPaul Walmsley BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 1242ace831fSPaul Walmsley part == OMAP4430_INVALID_PRCM_PARTITION || 1252ace831fSPaul Walmsley !_cm_bases[part]); 126610eb8c2SR Sricharan __raw_writel(val, _cm_bases[part] + inst + idx); 1272ace831fSPaul Walmsley } 1282ace831fSPaul Walmsley 1292ace831fSPaul Walmsley /* Read-modify-write a register in CM1. Caller must lock */ 1302ace831fSPaul Walmsley u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, 1312ace831fSPaul Walmsley s16 idx) 1322ace831fSPaul Walmsley { 1332ace831fSPaul Walmsley u32 v; 1342ace831fSPaul Walmsley 1352ace831fSPaul Walmsley v = omap4_cminst_read_inst_reg(part, inst, idx); 1362ace831fSPaul Walmsley v &= ~mask; 1372ace831fSPaul Walmsley v |= bits; 1382ace831fSPaul Walmsley omap4_cminst_write_inst_reg(v, part, inst, idx); 1392ace831fSPaul Walmsley 1402ace831fSPaul Walmsley return v; 1412ace831fSPaul Walmsley } 1422ace831fSPaul Walmsley 14304eb7773SRajendra Nayak u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx) 14404eb7773SRajendra Nayak { 14504eb7773SRajendra Nayak return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); 14604eb7773SRajendra Nayak } 14704eb7773SRajendra Nayak 14804eb7773SRajendra Nayak u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx) 14904eb7773SRajendra Nayak { 15004eb7773SRajendra Nayak return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); 15104eb7773SRajendra Nayak } 15204eb7773SRajendra Nayak 15304eb7773SRajendra Nayak u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) 15404eb7773SRajendra Nayak { 15504eb7773SRajendra Nayak u32 v; 15604eb7773SRajendra Nayak 15704eb7773SRajendra Nayak v = omap4_cminst_read_inst_reg(part, inst, idx); 15804eb7773SRajendra Nayak v &= mask; 15904eb7773SRajendra Nayak v >>= __ffs(mask); 16004eb7773SRajendra Nayak 16104eb7773SRajendra Nayak return v; 16204eb7773SRajendra Nayak } 16304eb7773SRajendra Nayak 164bd2122caSPaul Walmsley /* 165bd2122caSPaul Walmsley * 166bd2122caSPaul Walmsley */ 167bd2122caSPaul Walmsley 168bd2122caSPaul Walmsley /** 169bd2122caSPaul Walmsley * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield 170bd2122caSPaul Walmsley * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) 171bd2122caSPaul Walmsley * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 172bd2122caSPaul Walmsley * @inst: CM instance register offset (*_INST macro) 173bd2122caSPaul Walmsley * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 174bd2122caSPaul Walmsley * 175bd2122caSPaul Walmsley * @c must be the unshifted value for CLKTRCTRL - i.e., this function 176bd2122caSPaul Walmsley * will handle the shift itself. 177bd2122caSPaul Walmsley */ 178bd2122caSPaul Walmsley static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs) 179bd2122caSPaul Walmsley { 180bd2122caSPaul Walmsley u32 v; 181bd2122caSPaul Walmsley 182bd2122caSPaul Walmsley v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 183bd2122caSPaul Walmsley v &= ~OMAP4430_CLKTRCTRL_MASK; 184bd2122caSPaul Walmsley v |= c << OMAP4430_CLKTRCTRL_SHIFT; 185bd2122caSPaul Walmsley omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 186bd2122caSPaul Walmsley } 187bd2122caSPaul Walmsley 188bd2122caSPaul Walmsley /** 189bd2122caSPaul Walmsley * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? 190bd2122caSPaul Walmsley * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 191bd2122caSPaul Walmsley * @inst: CM instance register offset (*_INST macro) 192bd2122caSPaul Walmsley * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 193bd2122caSPaul Walmsley * 194bd2122caSPaul Walmsley * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) 195bd2122caSPaul Walmsley * is in hardware-supervised idle mode, or 0 otherwise. 196bd2122caSPaul Walmsley */ 197bd2122caSPaul Walmsley bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs) 198bd2122caSPaul Walmsley { 199bd2122caSPaul Walmsley u32 v; 200bd2122caSPaul Walmsley 201bd2122caSPaul Walmsley v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 202bd2122caSPaul Walmsley v &= OMAP4430_CLKTRCTRL_MASK; 203bd2122caSPaul Walmsley v >>= OMAP4430_CLKTRCTRL_SHIFT; 204bd2122caSPaul Walmsley 205bd2122caSPaul Walmsley return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; 206bd2122caSPaul Walmsley } 207bd2122caSPaul Walmsley 208bd2122caSPaul Walmsley /** 209bd2122caSPaul Walmsley * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode 210bd2122caSPaul Walmsley * @part: PRCM partition ID that the clockdomain registers exist in 211bd2122caSPaul Walmsley * @inst: CM instance register offset (*_INST macro) 212bd2122caSPaul Walmsley * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 213bd2122caSPaul Walmsley * 214bd2122caSPaul Walmsley * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 215bd2122caSPaul Walmsley * hardware-supervised idle mode. No return value. 216bd2122caSPaul Walmsley */ 217bd2122caSPaul Walmsley void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs) 218bd2122caSPaul Walmsley { 219bd2122caSPaul Walmsley _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); 220bd2122caSPaul Walmsley } 221bd2122caSPaul Walmsley 222bd2122caSPaul Walmsley /** 223bd2122caSPaul Walmsley * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode 224bd2122caSPaul Walmsley * @part: PRCM partition ID that the clockdomain registers exist in 225bd2122caSPaul Walmsley * @inst: CM instance register offset (*_INST macro) 226bd2122caSPaul Walmsley * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 227bd2122caSPaul Walmsley * 228bd2122caSPaul Walmsley * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 229bd2122caSPaul Walmsley * software-supervised idle mode, i.e., controlled manually by the 230bd2122caSPaul Walmsley * Linux OMAP clockdomain code. No return value. 231bd2122caSPaul Walmsley */ 232bd2122caSPaul Walmsley void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs) 233bd2122caSPaul Walmsley { 234bd2122caSPaul Walmsley _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); 235bd2122caSPaul Walmsley } 236bd2122caSPaul Walmsley 237bd2122caSPaul Walmsley /** 238bd2122caSPaul Walmsley * omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle 239bd2122caSPaul Walmsley * @part: PRCM partition ID that the clockdomain registers exist in 240bd2122caSPaul Walmsley * @inst: CM instance register offset (*_INST macro) 241bd2122caSPaul Walmsley * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 242bd2122caSPaul Walmsley * 243bd2122caSPaul Walmsley * Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle 244bd2122caSPaul Walmsley * No return value. 245bd2122caSPaul Walmsley */ 246bd2122caSPaul Walmsley void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs) 247bd2122caSPaul Walmsley { 248bd2122caSPaul Walmsley _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); 249bd2122caSPaul Walmsley } 250bd2122caSPaul Walmsley 251bd2122caSPaul Walmsley /** 252bd2122caSPaul Walmsley * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle 253bd2122caSPaul Walmsley * @part: PRCM partition ID that the clockdomain registers exist in 254bd2122caSPaul Walmsley * @inst: CM instance register offset (*_INST macro) 255bd2122caSPaul Walmsley * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 256bd2122caSPaul Walmsley * 257bd2122caSPaul Walmsley * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, 258bd2122caSPaul Walmsley * waking it up. No return value. 259bd2122caSPaul Walmsley */ 260bd2122caSPaul Walmsley void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs) 261bd2122caSPaul Walmsley { 262bd2122caSPaul Walmsley _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); 263bd2122caSPaul Walmsley } 264bd2122caSPaul Walmsley 265bd2122caSPaul Walmsley /* 266bd2122caSPaul Walmsley * 267bd2122caSPaul Walmsley */ 2682ace831fSPaul Walmsley 2692ace831fSPaul Walmsley /** 270d0f0631dSBenoit Cousson * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state 271d0f0631dSBenoit Cousson * @part: PRCM partition ID that the CM_CLKCTRL register exists in 272d0f0631dSBenoit Cousson * @inst: CM instance register offset (*_INST macro) 273d0f0631dSBenoit Cousson * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 274d0f0631dSBenoit Cousson * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 2752ace831fSPaul Walmsley * 2762ace831fSPaul Walmsley * Wait for the module IDLEST to be functional. If the idle state is in any 2772ace831fSPaul Walmsley * the non functional state (trans, idle or disabled), module and thus the 2782ace831fSPaul Walmsley * sysconfig cannot be accessed and will probably lead to an "imprecise 2792ace831fSPaul Walmsley * external abort" 2802ace831fSPaul Walmsley */ 281d0f0631dSBenoit Cousson int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, 282d0f0631dSBenoit Cousson u16 clkctrl_offs) 2832ace831fSPaul Walmsley { 2842ace831fSPaul Walmsley int i = 0; 2852ace831fSPaul Walmsley 286d0f0631dSBenoit Cousson if (!clkctrl_offs) 2872ace831fSPaul Walmsley return 0; 2882ace831fSPaul Walmsley 289d0f0631dSBenoit Cousson omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs), 2902ace831fSPaul Walmsley MAX_MODULE_READY_TIME, i); 2912ace831fSPaul Walmsley 2922ace831fSPaul Walmsley return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 2932ace831fSPaul Walmsley } 2942ace831fSPaul Walmsley 29511b10341SBenoit Cousson /** 29611b10341SBenoit Cousson * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled' 29711b10341SBenoit Cousson * state 29811b10341SBenoit Cousson * @part: PRCM partition ID that the CM_CLKCTRL register exists in 29911b10341SBenoit Cousson * @inst: CM instance register offset (*_INST macro) 30011b10341SBenoit Cousson * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 30111b10341SBenoit Cousson * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 30211b10341SBenoit Cousson * 30311b10341SBenoit Cousson * Wait for the module IDLEST to be disabled. Some PRCM transition, 30411b10341SBenoit Cousson * like reset assertion or parent clock de-activation must wait the 30511b10341SBenoit Cousson * module to be fully disabled. 30611b10341SBenoit Cousson */ 30711b10341SBenoit Cousson int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 30811b10341SBenoit Cousson { 30911b10341SBenoit Cousson int i = 0; 31011b10341SBenoit Cousson 31111b10341SBenoit Cousson if (!clkctrl_offs) 31211b10341SBenoit Cousson return 0; 31311b10341SBenoit Cousson 31411b10341SBenoit Cousson omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) == 31511b10341SBenoit Cousson CLKCTRL_IDLEST_DISABLED), 316b8f15b7eSPaul Walmsley MAX_MODULE_DISABLE_TIME, i); 31711b10341SBenoit Cousson 318b8f15b7eSPaul Walmsley return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY; 31911b10341SBenoit Cousson } 320288d6a16SBenoit Cousson 321288d6a16SBenoit Cousson /** 322288d6a16SBenoit Cousson * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL 323288d6a16SBenoit Cousson * @mode: Module mode (SW or HW) 324288d6a16SBenoit Cousson * @part: PRCM partition ID that the CM_CLKCTRL register exists in 325288d6a16SBenoit Cousson * @inst: CM instance register offset (*_INST macro) 326288d6a16SBenoit Cousson * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 327288d6a16SBenoit Cousson * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 328288d6a16SBenoit Cousson * 329288d6a16SBenoit Cousson * No return value. 330288d6a16SBenoit Cousson */ 331288d6a16SBenoit Cousson void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs, 332288d6a16SBenoit Cousson u16 clkctrl_offs) 333288d6a16SBenoit Cousson { 334288d6a16SBenoit Cousson u32 v; 335288d6a16SBenoit Cousson 336288d6a16SBenoit Cousson v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 337288d6a16SBenoit Cousson v &= ~OMAP4430_MODULEMODE_MASK; 338288d6a16SBenoit Cousson v |= mode << OMAP4430_MODULEMODE_SHIFT; 339288d6a16SBenoit Cousson omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 340288d6a16SBenoit Cousson } 341288d6a16SBenoit Cousson 342288d6a16SBenoit Cousson /** 343288d6a16SBenoit Cousson * omap4_cminst_module_disable - Disable the module inside CLKCTRL 344288d6a16SBenoit Cousson * @part: PRCM partition ID that the CM_CLKCTRL register exists in 345288d6a16SBenoit Cousson * @inst: CM instance register offset (*_INST macro) 346288d6a16SBenoit Cousson * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 347288d6a16SBenoit Cousson * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 348288d6a16SBenoit Cousson * 349288d6a16SBenoit Cousson * No return value. 350288d6a16SBenoit Cousson */ 351288d6a16SBenoit Cousson void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, 352288d6a16SBenoit Cousson u16 clkctrl_offs) 353288d6a16SBenoit Cousson { 354288d6a16SBenoit Cousson u32 v; 355288d6a16SBenoit Cousson 356288d6a16SBenoit Cousson v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 357288d6a16SBenoit Cousson v &= ~OMAP4430_MODULEMODE_MASK; 358288d6a16SBenoit Cousson omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 359288d6a16SBenoit Cousson } 360