12ace831fSPaul Walmsley /* 22ace831fSPaul Walmsley * OMAP4 CM instance functions 32ace831fSPaul Walmsley * 42ace831fSPaul Walmsley * Copyright (C) 2009 Nokia Corporation 54bd5259eSPaul Walmsley * Copyright (C) 2008-2011 Texas Instruments, Inc. 62ace831fSPaul Walmsley * Paul Walmsley 74bd5259eSPaul Walmsley * Rajendra Nayak <rnayak@ti.com> 82ace831fSPaul Walmsley * 92ace831fSPaul Walmsley * This program is free software; you can redistribute it and/or modify 102ace831fSPaul Walmsley * it under the terms of the GNU General Public License version 2 as 112ace831fSPaul Walmsley * published by the Free Software Foundation. 122ace831fSPaul Walmsley * 132ace831fSPaul Walmsley * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1, 142ace831fSPaul Walmsley * or CM2 hardware modules. For example, the EMU_CM CM instance is in 152ace831fSPaul Walmsley * the PRM hardware module. What a mess... 162ace831fSPaul Walmsley */ 172ace831fSPaul Walmsley 182ace831fSPaul Walmsley #include <linux/kernel.h> 192ace831fSPaul Walmsley #include <linux/types.h> 202ace831fSPaul Walmsley #include <linux/errno.h> 212ace831fSPaul Walmsley #include <linux/err.h> 222ace831fSPaul Walmsley #include <linux/io.h> 232ace831fSPaul Walmsley 244bd5259eSPaul Walmsley #include "clockdomain.h" 252ace831fSPaul Walmsley #include "cm.h" 262ace831fSPaul Walmsley #include "cm1_44xx.h" 272ace831fSPaul Walmsley #include "cm2_44xx.h" 282ace831fSPaul Walmsley #include "cm44xx.h" 292ace831fSPaul Walmsley #include "cminst44xx.h" 30bd2122caSPaul Walmsley #include "cm-regbits-34xx.h" 312ace831fSPaul Walmsley #include "prcm44xx.h" 322ace831fSPaul Walmsley #include "prm44xx.h" 332ace831fSPaul Walmsley #include "prcm_mpu44xx.h" 34610eb8c2SR Sricharan #include "prcm-common.h" 352ace831fSPaul Walmsley 3670fcebf1STero Kristo #define OMAP4430_IDLEST_SHIFT 16 3770fcebf1STero Kristo #define OMAP4430_IDLEST_MASK (0x3 << 16) 3870fcebf1STero Kristo #define OMAP4430_CLKTRCTRL_SHIFT 0 3970fcebf1STero Kristo #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 4070fcebf1STero Kristo #define OMAP4430_MODULEMODE_SHIFT 0 4170fcebf1STero Kristo #define OMAP4430_MODULEMODE_MASK (0x3 << 0) 4270fcebf1STero Kristo 43d0f0631dSBenoit Cousson /* 44d0f0631dSBenoit Cousson * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: 45d0f0631dSBenoit Cousson * 46d0f0631dSBenoit Cousson * 0x0 func: Module is fully functional, including OCP 47d0f0631dSBenoit Cousson * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep 48d0f0631dSBenoit Cousson * abortion 49d0f0631dSBenoit Cousson * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if 50d0f0631dSBenoit Cousson * using separate functional clock 51d0f0631dSBenoit Cousson * 0x3 disabled: Module is disabled and cannot be accessed 52d0f0631dSBenoit Cousson * 53d0f0631dSBenoit Cousson */ 54d0f0631dSBenoit Cousson #define CLKCTRL_IDLEST_FUNCTIONAL 0x0 55d0f0631dSBenoit Cousson #define CLKCTRL_IDLEST_INTRANSITION 0x1 56d0f0631dSBenoit Cousson #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 57d0f0631dSBenoit Cousson #define CLKCTRL_IDLEST_DISABLED 0x3 58d0f0631dSBenoit Cousson 59610eb8c2SR Sricharan static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 60610eb8c2SR Sricharan 61610eb8c2SR Sricharan /** 62610eb8c2SR Sricharan * omap_cm_base_init - Populates the cm partitions 63610eb8c2SR Sricharan * 64610eb8c2SR Sricharan * Populates the base addresses of the _cm_bases 65610eb8c2SR Sricharan * array used for read/write of cm module registers. 66610eb8c2SR Sricharan */ 67610eb8c2SR Sricharan void omap_cm_base_init(void) 68610eb8c2SR Sricharan { 69610eb8c2SR Sricharan _cm_bases[OMAP4430_PRM_PARTITION] = prm_base; 70610eb8c2SR Sricharan _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; 71610eb8c2SR Sricharan _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base; 72610eb8c2SR Sricharan _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; 73610eb8c2SR Sricharan } 742ace831fSPaul Walmsley 75d0f0631dSBenoit Cousson /* Private functions */ 76d0f0631dSBenoit Cousson 77d0f0631dSBenoit Cousson /** 78d0f0631dSBenoit Cousson * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield 79d0f0631dSBenoit Cousson * @part: PRCM partition ID that the CM_CLKCTRL register exists in 80d0f0631dSBenoit Cousson * @inst: CM instance register offset (*_INST macro) 81d0f0631dSBenoit Cousson * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 82d0f0631dSBenoit Cousson * 83d0f0631dSBenoit Cousson * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to 84d0f0631dSBenoit Cousson * bit 0. 85d0f0631dSBenoit Cousson */ 869907f85eSTero Kristo static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs) 87d0f0631dSBenoit Cousson { 88d0f0631dSBenoit Cousson u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 89d0f0631dSBenoit Cousson v &= OMAP4430_IDLEST_MASK; 90d0f0631dSBenoit Cousson v >>= OMAP4430_IDLEST_SHIFT; 91d0f0631dSBenoit Cousson return v; 92d0f0631dSBenoit Cousson } 93d0f0631dSBenoit Cousson 94d0f0631dSBenoit Cousson /** 95d0f0631dSBenoit Cousson * _is_module_ready - can module registers be accessed without causing an abort? 96d0f0631dSBenoit Cousson * @part: PRCM partition ID that the CM_CLKCTRL register exists in 97d0f0631dSBenoit Cousson * @inst: CM instance register offset (*_INST macro) 98d0f0631dSBenoit Cousson * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 99d0f0631dSBenoit Cousson * 100d0f0631dSBenoit Cousson * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either 101d0f0631dSBenoit Cousson * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. 102d0f0631dSBenoit Cousson */ 1039907f85eSTero Kristo static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs) 104d0f0631dSBenoit Cousson { 105d0f0631dSBenoit Cousson u32 v; 106d0f0631dSBenoit Cousson 1079907f85eSTero Kristo v = _clkctrl_idlest(part, inst, clkctrl_offs); 108d0f0631dSBenoit Cousson 109d0f0631dSBenoit Cousson return (v == CLKCTRL_IDLEST_FUNCTIONAL || 110d0f0631dSBenoit Cousson v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; 111d0f0631dSBenoit Cousson } 112d0f0631dSBenoit Cousson 113d0f0631dSBenoit Cousson /* Public functions */ 114d0f0631dSBenoit Cousson 1152ace831fSPaul Walmsley /* Read a register in a CM instance */ 116d3f5d551SAnkur Kishore u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) 1172ace831fSPaul Walmsley { 1182ace831fSPaul Walmsley BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 1192ace831fSPaul Walmsley part == OMAP4430_INVALID_PRCM_PARTITION || 1202ace831fSPaul Walmsley !_cm_bases[part]); 121edfaf05cSVictor Kamensky return readl_relaxed(_cm_bases[part] + inst + idx); 1222ace831fSPaul Walmsley } 1232ace831fSPaul Walmsley 1242ace831fSPaul Walmsley /* Write into a register in a CM instance */ 125d3f5d551SAnkur Kishore void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) 1262ace831fSPaul Walmsley { 1272ace831fSPaul Walmsley BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 1282ace831fSPaul Walmsley part == OMAP4430_INVALID_PRCM_PARTITION || 1292ace831fSPaul Walmsley !_cm_bases[part]); 130edfaf05cSVictor Kamensky writel_relaxed(val, _cm_bases[part] + inst + idx); 1312ace831fSPaul Walmsley } 1322ace831fSPaul Walmsley 1332ace831fSPaul Walmsley /* Read-modify-write a register in CM1. Caller must lock */ 134d3f5d551SAnkur Kishore u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, 1352ace831fSPaul Walmsley s16 idx) 1362ace831fSPaul Walmsley { 1372ace831fSPaul Walmsley u32 v; 1382ace831fSPaul Walmsley 1392ace831fSPaul Walmsley v = omap4_cminst_read_inst_reg(part, inst, idx); 1402ace831fSPaul Walmsley v &= ~mask; 1412ace831fSPaul Walmsley v |= bits; 1422ace831fSPaul Walmsley omap4_cminst_write_inst_reg(v, part, inst, idx); 1432ace831fSPaul Walmsley 1442ace831fSPaul Walmsley return v; 1452ace831fSPaul Walmsley } 1462ace831fSPaul Walmsley 147d3f5d551SAnkur Kishore u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 14804eb7773SRajendra Nayak { 14904eb7773SRajendra Nayak return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); 15004eb7773SRajendra Nayak } 15104eb7773SRajendra Nayak 152d3f5d551SAnkur Kishore u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 15304eb7773SRajendra Nayak { 15404eb7773SRajendra Nayak return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); 15504eb7773SRajendra Nayak } 15604eb7773SRajendra Nayak 15704eb7773SRajendra Nayak u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) 15804eb7773SRajendra Nayak { 15904eb7773SRajendra Nayak u32 v; 16004eb7773SRajendra Nayak 16104eb7773SRajendra Nayak v = omap4_cminst_read_inst_reg(part, inst, idx); 16204eb7773SRajendra Nayak v &= mask; 16304eb7773SRajendra Nayak v >>= __ffs(mask); 16404eb7773SRajendra Nayak 16504eb7773SRajendra Nayak return v; 16604eb7773SRajendra Nayak } 16704eb7773SRajendra Nayak 168bd2122caSPaul Walmsley /* 169bd2122caSPaul Walmsley * 170bd2122caSPaul Walmsley */ 171bd2122caSPaul Walmsley 172bd2122caSPaul Walmsley /** 173bd2122caSPaul Walmsley * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield 174bd2122caSPaul Walmsley * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) 175bd2122caSPaul Walmsley * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 176bd2122caSPaul Walmsley * @inst: CM instance register offset (*_INST macro) 177bd2122caSPaul Walmsley * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 178bd2122caSPaul Walmsley * 179bd2122caSPaul Walmsley * @c must be the unshifted value for CLKTRCTRL - i.e., this function 180bd2122caSPaul Walmsley * will handle the shift itself. 181bd2122caSPaul Walmsley */ 182d3f5d551SAnkur Kishore static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) 183bd2122caSPaul Walmsley { 184bd2122caSPaul Walmsley u32 v; 185bd2122caSPaul Walmsley 186bd2122caSPaul Walmsley v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 187bd2122caSPaul Walmsley v &= ~OMAP4430_CLKTRCTRL_MASK; 188bd2122caSPaul Walmsley v |= c << OMAP4430_CLKTRCTRL_SHIFT; 189bd2122caSPaul Walmsley omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 190bd2122caSPaul Walmsley } 191bd2122caSPaul Walmsley 192bd2122caSPaul Walmsley /** 193bd2122caSPaul Walmsley * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? 194bd2122caSPaul Walmsley * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 195bd2122caSPaul Walmsley * @inst: CM instance register offset (*_INST macro) 196bd2122caSPaul Walmsley * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 197bd2122caSPaul Walmsley * 198bd2122caSPaul Walmsley * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) 199bd2122caSPaul Walmsley * is in hardware-supervised idle mode, or 0 otherwise. 200bd2122caSPaul Walmsley */ 201d3f5d551SAnkur Kishore bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) 202bd2122caSPaul Walmsley { 203bd2122caSPaul Walmsley u32 v; 204bd2122caSPaul Walmsley 205bd2122caSPaul Walmsley v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 206bd2122caSPaul Walmsley v &= OMAP4430_CLKTRCTRL_MASK; 207bd2122caSPaul Walmsley v >>= OMAP4430_CLKTRCTRL_SHIFT; 208bd2122caSPaul Walmsley 209bd2122caSPaul Walmsley return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; 210bd2122caSPaul Walmsley } 211bd2122caSPaul Walmsley 212bd2122caSPaul Walmsley /** 213bd2122caSPaul Walmsley * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode 214bd2122caSPaul Walmsley * @part: PRCM partition ID that the clockdomain registers exist in 215bd2122caSPaul Walmsley * @inst: CM instance register offset (*_INST macro) 216bd2122caSPaul Walmsley * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 217bd2122caSPaul Walmsley * 218bd2122caSPaul Walmsley * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 219bd2122caSPaul Walmsley * hardware-supervised idle mode. No return value. 220bd2122caSPaul Walmsley */ 221d3f5d551SAnkur Kishore void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) 222bd2122caSPaul Walmsley { 223bd2122caSPaul Walmsley _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); 224bd2122caSPaul Walmsley } 225bd2122caSPaul Walmsley 226bd2122caSPaul Walmsley /** 227bd2122caSPaul Walmsley * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode 228bd2122caSPaul Walmsley * @part: PRCM partition ID that the clockdomain registers exist in 229bd2122caSPaul Walmsley * @inst: CM instance register offset (*_INST macro) 230bd2122caSPaul Walmsley * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 231bd2122caSPaul Walmsley * 232bd2122caSPaul Walmsley * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 233bd2122caSPaul Walmsley * software-supervised idle mode, i.e., controlled manually by the 234bd2122caSPaul Walmsley * Linux OMAP clockdomain code. No return value. 235bd2122caSPaul Walmsley */ 236d3f5d551SAnkur Kishore void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) 237bd2122caSPaul Walmsley { 238bd2122caSPaul Walmsley _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); 239bd2122caSPaul Walmsley } 240bd2122caSPaul Walmsley 241bd2122caSPaul Walmsley /** 242bd2122caSPaul Walmsley * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle 243bd2122caSPaul Walmsley * @part: PRCM partition ID that the clockdomain registers exist in 244bd2122caSPaul Walmsley * @inst: CM instance register offset (*_INST macro) 245bd2122caSPaul Walmsley * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 246bd2122caSPaul Walmsley * 247bd2122caSPaul Walmsley * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, 248bd2122caSPaul Walmsley * waking it up. No return value. 249bd2122caSPaul Walmsley */ 250d3f5d551SAnkur Kishore void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) 251bd2122caSPaul Walmsley { 252bd2122caSPaul Walmsley _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); 253bd2122caSPaul Walmsley } 254bd2122caSPaul Walmsley 255bd2122caSPaul Walmsley /* 256bd2122caSPaul Walmsley * 257bd2122caSPaul Walmsley */ 2582ace831fSPaul Walmsley 259f67f04baSDave Gerlach void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs) 260f67f04baSDave Gerlach { 261f67f04baSDave Gerlach _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); 262f67f04baSDave Gerlach } 263f67f04baSDave Gerlach 2642ace831fSPaul Walmsley /** 265d0f0631dSBenoit Cousson * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state 266d0f0631dSBenoit Cousson * @part: PRCM partition ID that the CM_CLKCTRL register exists in 267d0f0631dSBenoit Cousson * @inst: CM instance register offset (*_INST macro) 268d0f0631dSBenoit Cousson * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 269021b6ff0STero Kristo * @bit_shift: bit shift for the register, ignored for OMAP4+ 2702ace831fSPaul Walmsley * 2712ace831fSPaul Walmsley * Wait for the module IDLEST to be functional. If the idle state is in any 2722ace831fSPaul Walmsley * the non functional state (trans, idle or disabled), module and thus the 2732ace831fSPaul Walmsley * sysconfig cannot be accessed and will probably lead to an "imprecise 2742ace831fSPaul Walmsley * external abort" 2752ace831fSPaul Walmsley */ 276021b6ff0STero Kristo static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, 277021b6ff0STero Kristo u8 bit_shift) 2782ace831fSPaul Walmsley { 2792ace831fSPaul Walmsley int i = 0; 2802ace831fSPaul Walmsley 281d0f0631dSBenoit Cousson if (!clkctrl_offs) 2822ace831fSPaul Walmsley return 0; 2832ace831fSPaul Walmsley 2849907f85eSTero Kristo omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs), 2852ace831fSPaul Walmsley MAX_MODULE_READY_TIME, i); 2862ace831fSPaul Walmsley 2872ace831fSPaul Walmsley return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 2882ace831fSPaul Walmsley } 2892ace831fSPaul Walmsley 29011b10341SBenoit Cousson /** 29111b10341SBenoit Cousson * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled' 29211b10341SBenoit Cousson * state 29311b10341SBenoit Cousson * @part: PRCM partition ID that the CM_CLKCTRL register exists in 29411b10341SBenoit Cousson * @inst: CM instance register offset (*_INST macro) 29511b10341SBenoit Cousson * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 296a8ae5afaSTero Kristo * @bit_shift: Bit shift for the register, ignored for OMAP4+ 29711b10341SBenoit Cousson * 29811b10341SBenoit Cousson * Wait for the module IDLEST to be disabled. Some PRCM transition, 29911b10341SBenoit Cousson * like reset assertion or parent clock de-activation must wait the 30011b10341SBenoit Cousson * module to be fully disabled. 30111b10341SBenoit Cousson */ 302a8ae5afaSTero Kristo static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, 303a8ae5afaSTero Kristo u8 bit_shift) 30411b10341SBenoit Cousson { 30511b10341SBenoit Cousson int i = 0; 30611b10341SBenoit Cousson 30711b10341SBenoit Cousson if (!clkctrl_offs) 30811b10341SBenoit Cousson return 0; 30911b10341SBenoit Cousson 3109907f85eSTero Kristo omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) == 31111b10341SBenoit Cousson CLKCTRL_IDLEST_DISABLED), 312b8f15b7eSPaul Walmsley MAX_MODULE_DISABLE_TIME, i); 31311b10341SBenoit Cousson 314b8f15b7eSPaul Walmsley return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY; 31511b10341SBenoit Cousson } 316288d6a16SBenoit Cousson 317288d6a16SBenoit Cousson /** 318288d6a16SBenoit Cousson * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL 319288d6a16SBenoit Cousson * @mode: Module mode (SW or HW) 320288d6a16SBenoit Cousson * @part: PRCM partition ID that the CM_CLKCTRL register exists in 321288d6a16SBenoit Cousson * @inst: CM instance register offset (*_INST macro) 322288d6a16SBenoit Cousson * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 323288d6a16SBenoit Cousson * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 324288d6a16SBenoit Cousson * 325288d6a16SBenoit Cousson * No return value. 326288d6a16SBenoit Cousson */ 327288d6a16SBenoit Cousson void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs, 328288d6a16SBenoit Cousson u16 clkctrl_offs) 329288d6a16SBenoit Cousson { 330288d6a16SBenoit Cousson u32 v; 331288d6a16SBenoit Cousson 332288d6a16SBenoit Cousson v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 333288d6a16SBenoit Cousson v &= ~OMAP4430_MODULEMODE_MASK; 334288d6a16SBenoit Cousson v |= mode << OMAP4430_MODULEMODE_SHIFT; 335288d6a16SBenoit Cousson omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 336288d6a16SBenoit Cousson } 337288d6a16SBenoit Cousson 338288d6a16SBenoit Cousson /** 339288d6a16SBenoit Cousson * omap4_cminst_module_disable - Disable the module inside CLKCTRL 340288d6a16SBenoit Cousson * @part: PRCM partition ID that the CM_CLKCTRL register exists in 341288d6a16SBenoit Cousson * @inst: CM instance register offset (*_INST macro) 342288d6a16SBenoit Cousson * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 343288d6a16SBenoit Cousson * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 344288d6a16SBenoit Cousson * 345288d6a16SBenoit Cousson * No return value. 346288d6a16SBenoit Cousson */ 347288d6a16SBenoit Cousson void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, 348288d6a16SBenoit Cousson u16 clkctrl_offs) 349288d6a16SBenoit Cousson { 350288d6a16SBenoit Cousson u32 v; 351288d6a16SBenoit Cousson 352288d6a16SBenoit Cousson v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 353288d6a16SBenoit Cousson v &= ~OMAP4430_MODULEMODE_MASK; 354288d6a16SBenoit Cousson omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 355288d6a16SBenoit Cousson } 3564bd5259eSPaul Walmsley 3574bd5259eSPaul Walmsley /* 3584bd5259eSPaul Walmsley * Clockdomain low-level functions 3594bd5259eSPaul Walmsley */ 3604bd5259eSPaul Walmsley 3614bd5259eSPaul Walmsley static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1, 3624bd5259eSPaul Walmsley struct clockdomain *clkdm2) 3634bd5259eSPaul Walmsley { 3644bd5259eSPaul Walmsley omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit), 3654bd5259eSPaul Walmsley clkdm1->prcm_partition, 3664bd5259eSPaul Walmsley clkdm1->cm_inst, clkdm1->clkdm_offs + 3674bd5259eSPaul Walmsley OMAP4_CM_STATICDEP); 3684bd5259eSPaul Walmsley return 0; 3694bd5259eSPaul Walmsley } 3704bd5259eSPaul Walmsley 3714bd5259eSPaul Walmsley static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1, 3724bd5259eSPaul Walmsley struct clockdomain *clkdm2) 3734bd5259eSPaul Walmsley { 3744bd5259eSPaul Walmsley omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit), 3754bd5259eSPaul Walmsley clkdm1->prcm_partition, 3764bd5259eSPaul Walmsley clkdm1->cm_inst, clkdm1->clkdm_offs + 3774bd5259eSPaul Walmsley OMAP4_CM_STATICDEP); 3784bd5259eSPaul Walmsley return 0; 3794bd5259eSPaul Walmsley } 3804bd5259eSPaul Walmsley 3814bd5259eSPaul Walmsley static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1, 3824bd5259eSPaul Walmsley struct clockdomain *clkdm2) 3834bd5259eSPaul Walmsley { 3844bd5259eSPaul Walmsley return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition, 3854bd5259eSPaul Walmsley clkdm1->cm_inst, 3864bd5259eSPaul Walmsley clkdm1->clkdm_offs + 3874bd5259eSPaul Walmsley OMAP4_CM_STATICDEP, 3884bd5259eSPaul Walmsley (1 << clkdm2->dep_bit)); 3894bd5259eSPaul Walmsley } 3904bd5259eSPaul Walmsley 3914bd5259eSPaul Walmsley static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) 3924bd5259eSPaul Walmsley { 3934bd5259eSPaul Walmsley struct clkdm_dep *cd; 3944bd5259eSPaul Walmsley u32 mask = 0; 3954bd5259eSPaul Walmsley 3964bd5259eSPaul Walmsley if (!clkdm->prcm_partition) 3974bd5259eSPaul Walmsley return 0; 3984bd5259eSPaul Walmsley 3994bd5259eSPaul Walmsley for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { 4004bd5259eSPaul Walmsley if (!cd->clkdm) 4014bd5259eSPaul Walmsley continue; /* only happens if data is erroneous */ 4024bd5259eSPaul Walmsley 4034bd5259eSPaul Walmsley mask |= 1 << cd->clkdm->dep_bit; 40492493870SPaul Walmsley cd->wkdep_usecount = 0; 4054bd5259eSPaul Walmsley } 4064bd5259eSPaul Walmsley 4074bd5259eSPaul Walmsley omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, 4084bd5259eSPaul Walmsley clkdm->cm_inst, clkdm->clkdm_offs + 4094bd5259eSPaul Walmsley OMAP4_CM_STATICDEP); 4104bd5259eSPaul Walmsley return 0; 4114bd5259eSPaul Walmsley } 4124bd5259eSPaul Walmsley 4134bd5259eSPaul Walmsley static int omap4_clkdm_sleep(struct clockdomain *clkdm) 4144bd5259eSPaul Walmsley { 415f67f04baSDave Gerlach if (clkdm->flags & CLKDM_CAN_HWSUP) 4164bd5259eSPaul Walmsley omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 417f67f04baSDave Gerlach clkdm->cm_inst, 418f67f04baSDave Gerlach clkdm->clkdm_offs); 419f67f04baSDave Gerlach else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) 420f67f04baSDave Gerlach omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, 421f67f04baSDave Gerlach clkdm->cm_inst, 422f67f04baSDave Gerlach clkdm->clkdm_offs); 423f67f04baSDave Gerlach else 424f67f04baSDave Gerlach return -EINVAL; 425f67f04baSDave Gerlach 4264bd5259eSPaul Walmsley return 0; 4274bd5259eSPaul Walmsley } 4284bd5259eSPaul Walmsley 4294bd5259eSPaul Walmsley static int omap4_clkdm_wakeup(struct clockdomain *clkdm) 4304bd5259eSPaul Walmsley { 4314bd5259eSPaul Walmsley omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, 4324bd5259eSPaul Walmsley clkdm->cm_inst, clkdm->clkdm_offs); 4334bd5259eSPaul Walmsley return 0; 4344bd5259eSPaul Walmsley } 4354bd5259eSPaul Walmsley 4364bd5259eSPaul Walmsley static void omap4_clkdm_allow_idle(struct clockdomain *clkdm) 4374bd5259eSPaul Walmsley { 4384bd5259eSPaul Walmsley omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 4394bd5259eSPaul Walmsley clkdm->cm_inst, clkdm->clkdm_offs); 4404bd5259eSPaul Walmsley } 4414bd5259eSPaul Walmsley 4424bd5259eSPaul Walmsley static void omap4_clkdm_deny_idle(struct clockdomain *clkdm) 4434bd5259eSPaul Walmsley { 4444bd5259eSPaul Walmsley if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 4454bd5259eSPaul Walmsley omap4_clkdm_wakeup(clkdm); 4464bd5259eSPaul Walmsley else 4474bd5259eSPaul Walmsley omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, 4484bd5259eSPaul Walmsley clkdm->cm_inst, 4494bd5259eSPaul Walmsley clkdm->clkdm_offs); 4504bd5259eSPaul Walmsley } 4514bd5259eSPaul Walmsley 4524bd5259eSPaul Walmsley static int omap4_clkdm_clk_enable(struct clockdomain *clkdm) 4534bd5259eSPaul Walmsley { 4544bd5259eSPaul Walmsley if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 4554bd5259eSPaul Walmsley return omap4_clkdm_wakeup(clkdm); 4564bd5259eSPaul Walmsley 4574bd5259eSPaul Walmsley return 0; 4584bd5259eSPaul Walmsley } 4594bd5259eSPaul Walmsley 4604bd5259eSPaul Walmsley static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) 4614bd5259eSPaul Walmsley { 4624bd5259eSPaul Walmsley bool hwsup = false; 4634bd5259eSPaul Walmsley 4644bd5259eSPaul Walmsley if (!clkdm->prcm_partition) 4654bd5259eSPaul Walmsley return 0; 4664bd5259eSPaul Walmsley 4674bd5259eSPaul Walmsley /* 4684bd5259eSPaul Walmsley * The CLKDM_MISSING_IDLE_REPORTING flag documentation has 4694bd5259eSPaul Walmsley * more details on the unpleasant problem this is working 4704bd5259eSPaul Walmsley * around 4714bd5259eSPaul Walmsley */ 4724bd5259eSPaul Walmsley if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && 4734bd5259eSPaul Walmsley !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { 4744bd5259eSPaul Walmsley omap4_clkdm_allow_idle(clkdm); 4754bd5259eSPaul Walmsley return 0; 4764bd5259eSPaul Walmsley } 4774bd5259eSPaul Walmsley 4784bd5259eSPaul Walmsley hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, 4794bd5259eSPaul Walmsley clkdm->cm_inst, clkdm->clkdm_offs); 4804bd5259eSPaul Walmsley 4814bd5259eSPaul Walmsley if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) 4824bd5259eSPaul Walmsley omap4_clkdm_sleep(clkdm); 4834bd5259eSPaul Walmsley 4844bd5259eSPaul Walmsley return 0; 4854bd5259eSPaul Walmsley } 4864bd5259eSPaul Walmsley 4874bd5259eSPaul Walmsley struct clkdm_ops omap4_clkdm_operations = { 4884bd5259eSPaul Walmsley .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, 4894bd5259eSPaul Walmsley .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, 4904bd5259eSPaul Walmsley .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep, 4914bd5259eSPaul Walmsley .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 4924bd5259eSPaul Walmsley .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep, 4934bd5259eSPaul Walmsley .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep, 4944bd5259eSPaul Walmsley .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep, 4954bd5259eSPaul Walmsley .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 4964bd5259eSPaul Walmsley .clkdm_sleep = omap4_clkdm_sleep, 4974bd5259eSPaul Walmsley .clkdm_wakeup = omap4_clkdm_wakeup, 4984bd5259eSPaul Walmsley .clkdm_allow_idle = omap4_clkdm_allow_idle, 4994bd5259eSPaul Walmsley .clkdm_deny_idle = omap4_clkdm_deny_idle, 5004bd5259eSPaul Walmsley .clkdm_clk_enable = omap4_clkdm_clk_enable, 5014bd5259eSPaul Walmsley .clkdm_clk_disable = omap4_clkdm_clk_disable, 5024bd5259eSPaul Walmsley }; 503c9218fe6SAmbresh K 504c9218fe6SAmbresh K struct clkdm_ops am43xx_clkdm_operations = { 505c9218fe6SAmbresh K .clkdm_sleep = omap4_clkdm_sleep, 506c9218fe6SAmbresh K .clkdm_wakeup = omap4_clkdm_wakeup, 507c9218fe6SAmbresh K .clkdm_allow_idle = omap4_clkdm_allow_idle, 508c9218fe6SAmbresh K .clkdm_deny_idle = omap4_clkdm_deny_idle, 509c9218fe6SAmbresh K .clkdm_clk_enable = omap4_clkdm_clk_enable, 510c9218fe6SAmbresh K .clkdm_clk_disable = omap4_clkdm_clk_disable, 511c9218fe6SAmbresh K }; 5127632a02fSTero Kristo 513021b6ff0STero Kristo static struct cm_ll_data omap4xxx_cm_ll_data = { 514021b6ff0STero Kristo .wait_module_ready = &omap4_cminst_wait_module_ready, 515a8ae5afaSTero Kristo .wait_module_idle = &omap4_cminst_wait_module_idle, 516021b6ff0STero Kristo }; 5177632a02fSTero Kristo 5187632a02fSTero Kristo int __init omap4_cm_init(void) 5197632a02fSTero Kristo { 5207632a02fSTero Kristo return cm_register(&omap4xxx_cm_ll_data); 5217632a02fSTero Kristo } 5227632a02fSTero Kristo 5237632a02fSTero Kristo static void __exit omap4_cm_exit(void) 5247632a02fSTero Kristo { 5257632a02fSTero Kristo cm_unregister(&omap4xxx_cm_ll_data); 5267632a02fSTero Kristo } 5277632a02fSTero Kristo __exitcall(omap4_cm_exit); 528