1dd708413SRajendra Nayak /* 2dd708413SRajendra Nayak * OMAP44xx Clock Management register bits 3dd708413SRajendra Nayak * 4dd708413SRajendra Nayak * Copyright (C) 2009 Texas Instruments, Inc. 5dd708413SRajendra Nayak * Copyright (C) 2009 Nokia Corporation 6dd708413SRajendra Nayak * 7dd708413SRajendra Nayak * Paul Walmsley (paul@pwsan.com) 8dd708413SRajendra Nayak * Rajendra Nayak (rnayak@ti.com) 9dd708413SRajendra Nayak * Benoit Cousson (b-cousson@ti.com) 10dd708413SRajendra Nayak * 11dd708413SRajendra Nayak * This file is automatically generated from the OMAP hardware databases. 12dd708413SRajendra Nayak * We respectfully ask that any modifications to this file be coordinated 13dd708413SRajendra Nayak * with the public linux-omap@vger.kernel.org mailing list and the 14dd708413SRajendra Nayak * authors above to ensure that the autogeneration scripts are kept 15dd708413SRajendra Nayak * up-to-date with the file contents. 16dd708413SRajendra Nayak * 17dd708413SRajendra Nayak * This program is free software; you can redistribute it and/or modify 18dd708413SRajendra Nayak * it under the terms of the GNU General Public License version 2 as 19dd708413SRajendra Nayak * published by the Free Software Foundation. 20dd708413SRajendra Nayak */ 21dd708413SRajendra Nayak 22dd708413SRajendra Nayak #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 23dd708413SRajendra Nayak #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 24dd708413SRajendra Nayak 25dd708413SRajendra Nayak #include "cm.h" 26dd708413SRajendra Nayak 27dd708413SRajendra Nayak 28dd708413SRajendra Nayak /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ 2956ef28acSRajendra Nayak #define OMAP4430_ABE_DYNDEP_SHIFT 3 30dd708413SRajendra Nayak #define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3) 31dd708413SRajendra Nayak 32dd708413SRajendra Nayak /* 33dd708413SRajendra Nayak * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 34dd708413SRajendra Nayak * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, 35dd708413SRajendra Nayak * CM_TESLA_STATICDEP 36dd708413SRajendra Nayak */ 3756ef28acSRajendra Nayak #define OMAP4430_ABE_STATDEP_SHIFT 3 38dd708413SRajendra Nayak #define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3) 39dd708413SRajendra Nayak 40dd708413SRajendra Nayak /* Used by CM_L4CFG_DYNAMICDEP */ 4156ef28acSRajendra Nayak #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 42dd708413SRajendra Nayak #define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16) 43dd708413SRajendra Nayak 44dd708413SRajendra Nayak /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ 4556ef28acSRajendra Nayak #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 46dd708413SRajendra Nayak #define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16) 47dd708413SRajendra Nayak 48dd708413SRajendra Nayak /* 49dd708413SRajendra Nayak * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB, 50dd708413SRajendra Nayak * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, 51dd708413SRajendra Nayak * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU 52dd708413SRajendra Nayak */ 5356ef28acSRajendra Nayak #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 54dd708413SRajendra Nayak #define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2) 55dd708413SRajendra Nayak 56dd708413SRajendra Nayak /* Used by CM_L4CFG_DYNAMICDEP */ 5756ef28acSRajendra Nayak #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 58dd708413SRajendra Nayak #define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17) 59dd708413SRajendra Nayak 60dd708413SRajendra Nayak /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ 6156ef28acSRajendra Nayak #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 62dd708413SRajendra Nayak #define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17) 63dd708413SRajendra Nayak 64dd708413SRajendra Nayak /* Used by CM1_ABE_CLKSTCTRL */ 6556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 66dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13) 67dd708413SRajendra Nayak 68dd708413SRajendra Nayak /* Used by CM1_ABE_CLKSTCTRL */ 6956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 70dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12) 71dd708413SRajendra Nayak 72dd708413SRajendra Nayak /* Used by CM_WKUP_CLKSTCTRL */ 7356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 74dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9) 75dd708413SRajendra Nayak 76dd708413SRajendra Nayak /* Used by CM1_ABE_CLKSTCTRL */ 7756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 78dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11) 79dd708413SRajendra Nayak 80dd708413SRajendra Nayak /* Used by CM1_ABE_CLKSTCTRL */ 8156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 82dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8) 83dd708413SRajendra Nayak 84dd708413SRajendra Nayak /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 8556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 86dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11) 87dd708413SRajendra Nayak 88dd708413SRajendra Nayak /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 8956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 90dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12) 91dd708413SRajendra Nayak 92dd708413SRajendra Nayak /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 9356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 94dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13) 95dd708413SRajendra Nayak 96dd708413SRajendra Nayak /* Used by CM_CAM_CLKSTCTRL */ 9756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 98dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9) 99dd708413SRajendra Nayak 100dd708413SRajendra Nayak /* Used by CM_EMU_CLKSTCTRL */ 10156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 102dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9) 103dd708413SRajendra Nayak 104dd708413SRajendra Nayak /* Used by CM_CEFUSE_CLKSTCTRL */ 10556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 106dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9) 107dd708413SRajendra Nayak 108dd708413SRajendra Nayak /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 10956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 110dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9) 111dd708413SRajendra Nayak 112dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 11356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 114dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9) 115dd708413SRajendra Nayak 116dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 11756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 118dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10) 119dd708413SRajendra Nayak 120dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 12156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 122dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11) 123dd708413SRajendra Nayak 124dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 12556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 126dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12) 127dd708413SRajendra Nayak 128dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 12956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 130dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13) 131dd708413SRajendra Nayak 132dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 13356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 134dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14) 135dd708413SRajendra Nayak 136dd708413SRajendra Nayak /* Used by CM_DSS_CLKSTCTRL */ 13756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 138dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10) 139dd708413SRajendra Nayak 140dd708413SRajendra Nayak /* Used by CM_DSS_CLKSTCTRL */ 14156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 142dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9) 143dd708413SRajendra Nayak 144dd708413SRajendra Nayak /* Used by CM_DUCATI_CLKSTCTRL */ 14556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 146dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8) 147dd708413SRajendra Nayak 148dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 14956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT 10 150dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10) 151dd708413SRajendra Nayak 152dd708413SRajendra Nayak /* Used by CM_EMU_CLKSTCTRL */ 15356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 154dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8) 155dd708413SRajendra Nayak 156dd708413SRajendra Nayak /* Used by CM_CAM_CLKSTCTRL */ 15756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 158dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10) 159dd708413SRajendra Nayak 160dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 16156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 162dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15) 163dd708413SRajendra Nayak 164dd708413SRajendra Nayak /* Used by CM1_ABE_CLKSTCTRL */ 16556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 166dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10) 167dd708413SRajendra Nayak 168dd708413SRajendra Nayak /* Used by CM_DSS_CLKSTCTRL */ 16956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 170dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11) 171dd708413SRajendra Nayak 172dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 17356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 174dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20) 175dd708413SRajendra Nayak 176dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 17756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 178dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26) 179dd708413SRajendra Nayak 180dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 18156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 182dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21) 183dd708413SRajendra Nayak 184dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 18556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 186dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27) 187dd708413SRajendra Nayak 188dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL */ 18956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT 31 190dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31) 191dd708413SRajendra Nayak 192dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 19356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 194dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13) 195dd708413SRajendra Nayak 196dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 19756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 198dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12) 199dd708413SRajendra Nayak 200dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 20156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 202dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28) 203dd708413SRajendra Nayak 204dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 20556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 206dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29) 207dd708413SRajendra Nayak 208dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 20956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 210dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11) 211dd708413SRajendra Nayak 212dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 21356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 214dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16) 215dd708413SRajendra Nayak 216dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 21756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 218dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17) 219dd708413SRajendra Nayak 220dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 22156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 222dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18) 223dd708413SRajendra Nayak 224dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 22556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 226dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19) 227dd708413SRajendra Nayak 228dd708413SRajendra Nayak /* Used by CM_CAM_CLKSTCTRL */ 22956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 230dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8) 231dd708413SRajendra Nayak 232dd708413SRajendra Nayak /* Used by CM_IVAHD_CLKSTCTRL */ 23356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 234dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8) 235dd708413SRajendra Nayak 236dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 23756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT 14 238dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14) 239dd708413SRajendra Nayak 240dd708413SRajendra Nayak /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ 24156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 242dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8) 243dd708413SRajendra Nayak 244dd708413SRajendra Nayak /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ 24556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 246dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8) 247dd708413SRajendra Nayak 248dd708413SRajendra Nayak /* Used by CM_D2D_CLKSTCTRL */ 24956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 250dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8) 251dd708413SRajendra Nayak 252dd708413SRajendra Nayak /* Used by CM_SDMA_CLKSTCTRL */ 25356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 254dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8) 255dd708413SRajendra Nayak 256dd708413SRajendra Nayak /* Used by CM_DSS_CLKSTCTRL */ 25756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 258dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8) 259dd708413SRajendra Nayak 260dd708413SRajendra Nayak /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 26156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 262dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8) 263dd708413SRajendra Nayak 264dd708413SRajendra Nayak /* Used by CM_GFX_CLKSTCTRL */ 26556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 266dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8) 267dd708413SRajendra Nayak 268dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 26956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 270dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8) 271dd708413SRajendra Nayak 272dd708413SRajendra Nayak /* Used by CM_L3INSTR_CLKSTCTRL */ 27356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 274dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8) 275dd708413SRajendra Nayak 276dd708413SRajendra Nayak /* Used by CM_L4SEC_CLKSTCTRL */ 27756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 278dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8) 279dd708413SRajendra Nayak 280dd708413SRajendra Nayak /* Used by CM_ALWON_CLKSTCTRL */ 28156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 282dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8) 283dd708413SRajendra Nayak 284dd708413SRajendra Nayak /* Used by CM_CEFUSE_CLKSTCTRL */ 28556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 286dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8) 287dd708413SRajendra Nayak 288dd708413SRajendra Nayak /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ 28956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 290dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8) 291dd708413SRajendra Nayak 292dd708413SRajendra Nayak /* Used by CM_D2D_CLKSTCTRL */ 29356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 294dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9) 295dd708413SRajendra Nayak 296dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 29756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 298dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9) 299dd708413SRajendra Nayak 300dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 30156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 302dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8) 303dd708413SRajendra Nayak 304dd708413SRajendra Nayak /* Used by CM_L4SEC_CLKSTCTRL */ 30556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 306dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9) 307dd708413SRajendra Nayak 308dd708413SRajendra Nayak /* Used by CM_WKUP_CLKSTCTRL */ 30956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 310dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12) 311dd708413SRajendra Nayak 312dd708413SRajendra Nayak /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ 31356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 314dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8) 315dd708413SRajendra Nayak 316dd708413SRajendra Nayak /* Used by CM1_ABE_CLKSTCTRL */ 31756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 318dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9) 319dd708413SRajendra Nayak 320dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 32156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 322dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16) 323dd708413SRajendra Nayak 324dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 32556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 326dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17) 327dd708413SRajendra Nayak 328dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 32956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 330dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18) 331dd708413SRajendra Nayak 332dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 33356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 334dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19) 335dd708413SRajendra Nayak 336dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 33756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 338dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25) 339dd708413SRajendra Nayak 340dd708413SRajendra Nayak /* Used by CM_EMU_CLKSTCTRL */ 34156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT 10 342dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10) 343dd708413SRajendra Nayak 344dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 34556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 346dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20) 347dd708413SRajendra Nayak 348dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 34956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 350dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21) 351dd708413SRajendra Nayak 352dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 35356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 354dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22) 355dd708413SRajendra Nayak 356dd708413SRajendra Nayak /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 35756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 358dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24) 359dd708413SRajendra Nayak 360dd708413SRajendra Nayak /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 36156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 362dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10) 363dd708413SRajendra Nayak 364dd708413SRajendra Nayak /* Used by CM_GFX_CLKSTCTRL */ 36556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 366dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9) 367dd708413SRajendra Nayak 368dd708413SRajendra Nayak /* Used by CM_ALWON_CLKSTCTRL */ 36956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 370dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11) 371dd708413SRajendra Nayak 372dd708413SRajendra Nayak /* Used by CM_ALWON_CLKSTCTRL */ 37356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 374dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10) 375dd708413SRajendra Nayak 376dd708413SRajendra Nayak /* Used by CM_ALWON_CLKSTCTRL */ 37756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 378dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9) 379dd708413SRajendra Nayak 380dd708413SRajendra Nayak /* Used by CM_WKUP_CLKSTCTRL */ 38156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 382dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8) 383dd708413SRajendra Nayak 384dd708413SRajendra Nayak /* Used by CM_TESLA_CLKSTCTRL */ 38556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 386dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8) 387dd708413SRajendra Nayak 388dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 38956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 390dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22) 391dd708413SRajendra Nayak 392dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 39356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 394dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23) 395dd708413SRajendra Nayak 396dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 39756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 398dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24) 399dd708413SRajendra Nayak 400dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 40156ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 402dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15) 403dd708413SRajendra Nayak 404dd708413SRajendra Nayak /* Used by CM_WKUP_CLKSTCTRL */ 40556ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 406dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10) 407dd708413SRajendra Nayak 408dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 40956ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 410dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30) 411dd708413SRajendra Nayak 412dd708413SRajendra Nayak /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 41356ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 414dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25) 415dd708413SRajendra Nayak 416dd708413SRajendra Nayak /* Used by CM_WKUP_CLKSTCTRL */ 41756ef28acSRajendra Nayak #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 418dd708413SRajendra Nayak #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11) 419dd708413SRajendra Nayak 420dd708413SRajendra Nayak /* 421dd708413SRajendra Nayak * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, 422dd708413SRajendra Nayak * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, 423dd708413SRajendra Nayak * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, 424dd708413SRajendra Nayak * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, 425dd708413SRajendra Nayak * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, 426dd708413SRajendra Nayak * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, 427dd708413SRajendra Nayak * CM1_ABE_TIMER8_CLKCTRL 428dd708413SRajendra Nayak */ 42956ef28acSRajendra Nayak #define OMAP4430_CLKSEL_SHIFT 24 430dd708413SRajendra Nayak #define OMAP4430_CLKSEL_MASK BITFIELD(24, 24) 431dd708413SRajendra Nayak 432dd708413SRajendra Nayak /* 433dd708413SRajendra Nayak * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, 434dd708413SRajendra Nayak * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, 435dd708413SRajendra Nayak * CM_CLKSEL_USB_60MHZ 436dd708413SRajendra Nayak */ 43756ef28acSRajendra Nayak #define OMAP4430_CLKSEL_0_0_SHIFT 0 438dd708413SRajendra Nayak #define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0) 439dd708413SRajendra Nayak 440dd708413SRajendra Nayak /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ 44156ef28acSRajendra Nayak #define OMAP4430_CLKSEL_0_1_SHIFT 0 442dd708413SRajendra Nayak #define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1) 443dd708413SRajendra Nayak 444dd708413SRajendra Nayak /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ 44556ef28acSRajendra Nayak #define OMAP4430_CLKSEL_24_25_SHIFT 24 446dd708413SRajendra Nayak #define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25) 447dd708413SRajendra Nayak 448dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ 44956ef28acSRajendra Nayak #define OMAP4430_CLKSEL_60M_SHIFT 24 450dd708413SRajendra Nayak #define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24) 451dd708413SRajendra Nayak 452dd708413SRajendra Nayak /* Used by CM1_ABE_AESS_CLKCTRL */ 45356ef28acSRajendra Nayak #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 454dd708413SRajendra Nayak #define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24) 455dd708413SRajendra Nayak 456dd708413SRajendra Nayak /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ 45756ef28acSRajendra Nayak #define OMAP4430_CLKSEL_CORE_SHIFT 0 458dd708413SRajendra Nayak #define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0) 459dd708413SRajendra Nayak 460dd708413SRajendra Nayak /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ 46156ef28acSRajendra Nayak #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 462dd708413SRajendra Nayak #define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1) 463dd708413SRajendra Nayak 464dd708413SRajendra Nayak /* Used by CM_WKUP_USIM_CLKCTRL */ 46556ef28acSRajendra Nayak #define OMAP4430_CLKSEL_DIV_SHIFT 24 466dd708413SRajendra Nayak #define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24) 467dd708413SRajendra Nayak 468dd708413SRajendra Nayak /* Used by CM_CAM_FDIF_CLKCTRL */ 46956ef28acSRajendra Nayak #define OMAP4430_CLKSEL_FCLK_SHIFT 24 470dd708413SRajendra Nayak #define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25) 471dd708413SRajendra Nayak 472dd708413SRajendra Nayak /* Used by CM_L4PER_MCBSP4_CLKCTRL */ 47356ef28acSRajendra Nayak #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 474dd708413SRajendra Nayak #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25) 475dd708413SRajendra Nayak 476dd708413SRajendra Nayak /* 477dd708413SRajendra Nayak * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, 478dd708413SRajendra Nayak * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, 479dd708413SRajendra Nayak * CM1_ABE_MCBSP3_CLKCTRL 480dd708413SRajendra Nayak */ 48156ef28acSRajendra Nayak #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 482dd708413SRajendra Nayak #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27) 483dd708413SRajendra Nayak 484dd708413SRajendra Nayak /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ 48556ef28acSRajendra Nayak #define OMAP4430_CLKSEL_L3_SHIFT 4 486dd708413SRajendra Nayak #define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4) 487dd708413SRajendra Nayak 488dd708413SRajendra Nayak /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ 48956ef28acSRajendra Nayak #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 490dd708413SRajendra Nayak #define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2) 491dd708413SRajendra Nayak 492dd708413SRajendra Nayak /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ 49356ef28acSRajendra Nayak #define OMAP4430_CLKSEL_L4_SHIFT 8 494dd708413SRajendra Nayak #define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8) 495dd708413SRajendra Nayak 496dd708413SRajendra Nayak /* Used by CM_CLKSEL_ABE */ 49756ef28acSRajendra Nayak #define OMAP4430_CLKSEL_OPP_SHIFT 0 498dd708413SRajendra Nayak #define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1) 499dd708413SRajendra Nayak 500dd708413SRajendra Nayak /* Used by CM_GFX_GFX_CLKCTRL */ 50156ef28acSRajendra Nayak #define OMAP4430_CLKSEL_PER_192M_SHIFT 25 502dd708413SRajendra Nayak #define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26) 503dd708413SRajendra Nayak 504dd708413SRajendra Nayak /* Used by CM_EMU_DEBUGSS_CLKCTRL */ 50556ef28acSRajendra Nayak #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 506dd708413SRajendra Nayak #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29) 507dd708413SRajendra Nayak 508dd708413SRajendra Nayak /* Used by CM_EMU_DEBUGSS_CLKCTRL */ 50956ef28acSRajendra Nayak #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 510dd708413SRajendra Nayak #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26) 511dd708413SRajendra Nayak 512dd708413SRajendra Nayak /* Used by CM_GFX_GFX_CLKCTRL */ 51356ef28acSRajendra Nayak #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 514dd708413SRajendra Nayak #define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24) 515dd708413SRajendra Nayak 516dd708413SRajendra Nayak /* 517dd708413SRajendra Nayak * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, 518dd708413SRajendra Nayak * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL 519dd708413SRajendra Nayak */ 52056ef28acSRajendra Nayak #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 521dd708413SRajendra Nayak #define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25) 522dd708413SRajendra Nayak 523dd708413SRajendra Nayak /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ 52456ef28acSRajendra Nayak #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 525dd708413SRajendra Nayak #define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24) 526dd708413SRajendra Nayak 527dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 52856ef28acSRajendra Nayak #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 529dd708413SRajendra Nayak #define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24) 530dd708413SRajendra Nayak 531dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 53256ef28acSRajendra Nayak #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 533dd708413SRajendra Nayak #define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25) 534dd708413SRajendra Nayak 535dd708413SRajendra Nayak /* 536dd708413SRajendra Nayak * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL, 537dd708413SRajendra Nayak * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, 538dd708413SRajendra Nayak * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, 539dd708413SRajendra Nayak * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, 540dd708413SRajendra Nayak * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL, 541dd708413SRajendra Nayak * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE, 542dd708413SRajendra Nayak * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE, 543dd708413SRajendra Nayak * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL, 544dd708413SRajendra Nayak * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL, 545dd708413SRajendra Nayak * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE 546dd708413SRajendra Nayak */ 54756ef28acSRajendra Nayak #define OMAP4430_CLKTRCTRL_SHIFT 0 548dd708413SRajendra Nayak #define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1) 549dd708413SRajendra Nayak 550dd708413SRajendra Nayak /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ 55156ef28acSRajendra Nayak #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 552dd708413SRajendra Nayak #define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6) 553dd708413SRajendra Nayak 554dd708413SRajendra Nayak /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ 55556ef28acSRajendra Nayak #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 556dd708413SRajendra Nayak #define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18) 557dd708413SRajendra Nayak 558dd708413SRajendra Nayak /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ 55956ef28acSRajendra Nayak #define OMAP4430_D2D_DYNDEP_SHIFT 18 560dd708413SRajendra Nayak #define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18) 561dd708413SRajendra Nayak 562dd708413SRajendra Nayak /* Used by CM_MPU_STATICDEP */ 56356ef28acSRajendra Nayak #define OMAP4430_D2D_STATDEP_SHIFT 18 564dd708413SRajendra Nayak #define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18) 565dd708413SRajendra Nayak 566dd708413SRajendra Nayak /* 567dd708413SRajendra Nayak * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, 568dd708413SRajendra Nayak * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, 569dd708413SRajendra Nayak * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, 570dd708413SRajendra Nayak * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, 571dd708413SRajendra Nayak * CM_SSC_DELTAMSTEP_DPLL_MPU 572dd708413SRajendra Nayak */ 57356ef28acSRajendra Nayak #define OMAP4430_DELTAMSTEP_SHIFT 0 574dd708413SRajendra Nayak #define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19) 575dd708413SRajendra Nayak 576dd708413SRajendra Nayak /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ 57756ef28acSRajendra Nayak #define OMAP4430_DLL_OVERRIDE_SHIFT 2 578dd708413SRajendra Nayak #define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2) 579dd708413SRajendra Nayak 580dd708413SRajendra Nayak /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ 58156ef28acSRajendra Nayak #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 582dd708413SRajendra Nayak #define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0) 583dd708413SRajendra Nayak 584dd708413SRajendra Nayak /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ 58556ef28acSRajendra Nayak #define OMAP4430_DLL_RESET_SHIFT 3 586dd708413SRajendra Nayak #define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3) 587dd708413SRajendra Nayak 588dd708413SRajendra Nayak /* 589dd708413SRajendra Nayak * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB, 590dd708413SRajendra Nayak * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 591dd708413SRajendra Nayak * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU 592dd708413SRajendra Nayak */ 59356ef28acSRajendra Nayak #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 594dd708413SRajendra Nayak #define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23) 595dd708413SRajendra Nayak 596dd708413SRajendra Nayak /* Used by CM_CLKDCOLDO_DPLL_USB */ 59756ef28acSRajendra Nayak #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 598dd708413SRajendra Nayak #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8) 599dd708413SRajendra Nayak 600dd708413SRajendra Nayak /* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */ 60156ef28acSRajendra Nayak #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 602dd708413SRajendra Nayak #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20) 603dd708413SRajendra Nayak 604dd708413SRajendra Nayak /* 605dd708413SRajendra Nayak * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, 606dd708413SRajendra Nayak * CM_DIV_M3_DPLL_CORE 607dd708413SRajendra Nayak */ 60856ef28acSRajendra Nayak #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 609dd708413SRajendra Nayak #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4) 610dd708413SRajendra Nayak 611dd708413SRajendra Nayak /* 612dd708413SRajendra Nayak * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, 613dd708413SRajendra Nayak * CM_DIV_M3_DPLL_CORE 614dd708413SRajendra Nayak */ 61556ef28acSRajendra Nayak #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 616dd708413SRajendra Nayak #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5) 617dd708413SRajendra Nayak 618dd708413SRajendra Nayak /* 619dd708413SRajendra Nayak * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, 620dd708413SRajendra Nayak * CM_DIV_M3_DPLL_CORE 621dd708413SRajendra Nayak */ 62256ef28acSRajendra Nayak #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 623dd708413SRajendra Nayak #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8) 624dd708413SRajendra Nayak 625dd708413SRajendra Nayak /* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ 62656ef28acSRajendra Nayak #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 627dd708413SRajendra Nayak #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10) 628dd708413SRajendra Nayak 629dd708413SRajendra Nayak /* 630dd708413SRajendra Nayak * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, 631dd708413SRajendra Nayak * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 632dd708413SRajendra Nayak * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU 633dd708413SRajendra Nayak */ 63456ef28acSRajendra Nayak #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 635dd708413SRajendra Nayak #define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4) 636dd708413SRajendra Nayak 637dd708413SRajendra Nayak /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ 63856ef28acSRajendra Nayak #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 639dd708413SRajendra Nayak #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6) 640dd708413SRajendra Nayak 641dd708413SRajendra Nayak /* 642dd708413SRajendra Nayak * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, 643dd708413SRajendra Nayak * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 644dd708413SRajendra Nayak * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU 645dd708413SRajendra Nayak */ 64656ef28acSRajendra Nayak #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 647dd708413SRajendra Nayak #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5) 648dd708413SRajendra Nayak 649dd708413SRajendra Nayak /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ 65056ef28acSRajendra Nayak #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 651dd708413SRajendra Nayak #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7) 652dd708413SRajendra Nayak 653dd708413SRajendra Nayak /* 654dd708413SRajendra Nayak * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, 655dd708413SRajendra Nayak * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, 656dd708413SRajendra Nayak * CM_DIV_M2_DPLL_MPU 657dd708413SRajendra Nayak */ 65856ef28acSRajendra Nayak #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 659dd708413SRajendra Nayak #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8) 660dd708413SRajendra Nayak 661dd708413SRajendra Nayak /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ 66256ef28acSRajendra Nayak #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 663dd708413SRajendra Nayak #define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10) 664dd708413SRajendra Nayak 665dd708413SRajendra Nayak /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ 66656ef28acSRajendra Nayak #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 667dd708413SRajendra Nayak #define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15) 668dd708413SRajendra Nayak 669dd708413SRajendra Nayak /* Used by CM_SHADOW_FREQ_CONFIG2 */ 67056ef28acSRajendra Nayak #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 671dd708413SRajendra Nayak #define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7) 672dd708413SRajendra Nayak 673dd708413SRajendra Nayak /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ 67456ef28acSRajendra Nayak #define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT 1 675dd708413SRajendra Nayak #define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1) 676dd708413SRajendra Nayak 677dd708413SRajendra Nayak /* 678dd708413SRajendra Nayak * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, 679dd708413SRajendra Nayak * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 680dd708413SRajendra Nayak * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU 681dd708413SRajendra Nayak */ 68256ef28acSRajendra Nayak #define OMAP4430_DPLL_DIV_SHIFT 0 683dd708413SRajendra Nayak #define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6) 684dd708413SRajendra Nayak 685dd708413SRajendra Nayak /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ 68656ef28acSRajendra Nayak #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 687dd708413SRajendra Nayak #define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7) 688dd708413SRajendra Nayak 689dd708413SRajendra Nayak /* 690dd708413SRajendra Nayak * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB, 691dd708413SRajendra Nayak * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 692dd708413SRajendra Nayak * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 693dd708413SRajendra Nayak */ 69456ef28acSRajendra Nayak #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 695dd708413SRajendra Nayak #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8) 696dd708413SRajendra Nayak 697dd708413SRajendra Nayak /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ 69856ef28acSRajendra Nayak #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 699dd708413SRajendra Nayak #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3) 700dd708413SRajendra Nayak 701dd708413SRajendra Nayak /* 702dd708413SRajendra Nayak * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, 703dd708413SRajendra Nayak * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 704dd708413SRajendra Nayak * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 705dd708413SRajendra Nayak */ 70656ef28acSRajendra Nayak #define OMAP4430_DPLL_EN_SHIFT 0 707dd708413SRajendra Nayak #define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2) 708dd708413SRajendra Nayak 709dd708413SRajendra Nayak /* 710dd708413SRajendra Nayak * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 711dd708413SRajendra Nayak * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 712dd708413SRajendra Nayak * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 713dd708413SRajendra Nayak */ 71456ef28acSRajendra Nayak #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 715dd708413SRajendra Nayak #define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10) 716dd708413SRajendra Nayak 717dd708413SRajendra Nayak /* 718dd708413SRajendra Nayak * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, 719dd708413SRajendra Nayak * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 720dd708413SRajendra Nayak * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU 721dd708413SRajendra Nayak */ 72256ef28acSRajendra Nayak #define OMAP4430_DPLL_MULT_SHIFT 8 723dd708413SRajendra Nayak #define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18) 724dd708413SRajendra Nayak 725dd708413SRajendra Nayak /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ 72656ef28acSRajendra Nayak #define OMAP4430_DPLL_MULT_USB_SHIFT 8 727dd708413SRajendra Nayak #define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19) 728dd708413SRajendra Nayak 729dd708413SRajendra Nayak /* 730dd708413SRajendra Nayak * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 731dd708413SRajendra Nayak * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 732dd708413SRajendra Nayak * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 733dd708413SRajendra Nayak */ 73456ef28acSRajendra Nayak #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 735dd708413SRajendra Nayak #define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11) 736dd708413SRajendra Nayak 737dd708413SRajendra Nayak /* Used by CM_CLKSEL_DPLL_USB */ 73856ef28acSRajendra Nayak #define OMAP4430_DPLL_SD_DIV_SHIFT 24 739dd708413SRajendra Nayak #define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31) 740dd708413SRajendra Nayak 741dd708413SRajendra Nayak /* 742dd708413SRajendra Nayak * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, 743dd708413SRajendra Nayak * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 744dd708413SRajendra Nayak * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 745dd708413SRajendra Nayak */ 74656ef28acSRajendra Nayak #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 747dd708413SRajendra Nayak #define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13) 748dd708413SRajendra Nayak 749dd708413SRajendra Nayak /* 750dd708413SRajendra Nayak * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, 751dd708413SRajendra Nayak * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 752dd708413SRajendra Nayak * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 753dd708413SRajendra Nayak */ 75456ef28acSRajendra Nayak #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 755dd708413SRajendra Nayak #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14) 756dd708413SRajendra Nayak 757dd708413SRajendra Nayak /* 758dd708413SRajendra Nayak * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, 759dd708413SRajendra Nayak * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 760dd708413SRajendra Nayak * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 761dd708413SRajendra Nayak */ 76256ef28acSRajendra Nayak #define OMAP4430_DPLL_SSC_EN_SHIFT 12 763dd708413SRajendra Nayak #define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12) 764dd708413SRajendra Nayak 765dd708413SRajendra Nayak /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ 76656ef28acSRajendra Nayak #define OMAP4430_DSS_DYNDEP_SHIFT 8 767dd708413SRajendra Nayak #define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8) 768dd708413SRajendra Nayak 769dd708413SRajendra Nayak /* 770dd708413SRajendra Nayak * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, 771dd708413SRajendra Nayak * CM_MPU_STATICDEP 772dd708413SRajendra Nayak */ 77356ef28acSRajendra Nayak #define OMAP4430_DSS_STATDEP_SHIFT 8 774dd708413SRajendra Nayak #define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8) 775dd708413SRajendra Nayak 776dd708413SRajendra Nayak /* Used by CM_L3_2_DYNAMICDEP */ 77756ef28acSRajendra Nayak #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 778dd708413SRajendra Nayak #define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0) 779dd708413SRajendra Nayak 780dd708413SRajendra Nayak /* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ 78156ef28acSRajendra Nayak #define OMAP4430_DUCATI_STATDEP_SHIFT 0 782dd708413SRajendra Nayak #define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0) 783dd708413SRajendra Nayak 784dd708413SRajendra Nayak /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ 78556ef28acSRajendra Nayak #define OMAP4430_FREQ_UPDATE_SHIFT 0 786dd708413SRajendra Nayak #define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0) 787dd708413SRajendra Nayak 788dd708413SRajendra Nayak /* Used by CM_L3_2_DYNAMICDEP */ 78956ef28acSRajendra Nayak #define OMAP4430_GFX_DYNDEP_SHIFT 10 790dd708413SRajendra Nayak #define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10) 791dd708413SRajendra Nayak 792dd708413SRajendra Nayak /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ 79356ef28acSRajendra Nayak #define OMAP4430_GFX_STATDEP_SHIFT 10 794dd708413SRajendra Nayak #define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10) 795dd708413SRajendra Nayak 796dd708413SRajendra Nayak /* Used by CM_SHADOW_FREQ_CONFIG2 */ 79756ef28acSRajendra Nayak #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 798dd708413SRajendra Nayak #define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0) 799dd708413SRajendra Nayak 800dd708413SRajendra Nayak /* 801dd708413SRajendra Nayak * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, 802dd708413SRajendra Nayak * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA 803dd708413SRajendra Nayak */ 80456ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 805dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4) 806dd708413SRajendra Nayak 807dd708413SRajendra Nayak /* 808dd708413SRajendra Nayak * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, 809dd708413SRajendra Nayak * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA 810dd708413SRajendra Nayak */ 81156ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 812dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5) 813dd708413SRajendra Nayak 814dd708413SRajendra Nayak /* 815dd708413SRajendra Nayak * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, 816dd708413SRajendra Nayak * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA 817dd708413SRajendra Nayak */ 81856ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 819dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8) 820dd708413SRajendra Nayak 821dd708413SRajendra Nayak /* 822dd708413SRajendra Nayak * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, 823dd708413SRajendra Nayak * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA 824dd708413SRajendra Nayak */ 82556ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 826dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12) 827dd708413SRajendra Nayak 828dd708413SRajendra Nayak /* 829dd708413SRajendra Nayak * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, 830dd708413SRajendra Nayak * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA 831dd708413SRajendra Nayak */ 83256ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 833dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4) 834dd708413SRajendra Nayak 835dd708413SRajendra Nayak /* 836dd708413SRajendra Nayak * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, 837dd708413SRajendra Nayak * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA 838dd708413SRajendra Nayak */ 83956ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 840dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5) 841dd708413SRajendra Nayak 842dd708413SRajendra Nayak /* 843dd708413SRajendra Nayak * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, 844dd708413SRajendra Nayak * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA 845dd708413SRajendra Nayak */ 84656ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 847dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8) 848dd708413SRajendra Nayak 849dd708413SRajendra Nayak /* 850dd708413SRajendra Nayak * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, 851dd708413SRajendra Nayak * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA 852dd708413SRajendra Nayak */ 85356ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 854dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12) 855dd708413SRajendra Nayak 856dd708413SRajendra Nayak /* 857dd708413SRajendra Nayak * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, 858dd708413SRajendra Nayak * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY 859dd708413SRajendra Nayak */ 86056ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 861dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4) 862dd708413SRajendra Nayak 863dd708413SRajendra Nayak /* 864dd708413SRajendra Nayak * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, 865dd708413SRajendra Nayak * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY 866dd708413SRajendra Nayak */ 86756ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 868dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5) 869dd708413SRajendra Nayak 870dd708413SRajendra Nayak /* 871dd708413SRajendra Nayak * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, 872dd708413SRajendra Nayak * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY 873dd708413SRajendra Nayak */ 87456ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 875dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8) 876dd708413SRajendra Nayak 877dd708413SRajendra Nayak /* 878dd708413SRajendra Nayak * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, 879dd708413SRajendra Nayak * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY 880dd708413SRajendra Nayak */ 88156ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 882dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12) 883dd708413SRajendra Nayak 884dd708413SRajendra Nayak /* 885dd708413SRajendra Nayak * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, 886dd708413SRajendra Nayak * CM_DIV_M7_DPLL_CORE 887dd708413SRajendra Nayak */ 88856ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 889dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4) 890dd708413SRajendra Nayak 891dd708413SRajendra Nayak /* 892dd708413SRajendra Nayak * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, 893dd708413SRajendra Nayak * CM_DIV_M7_DPLL_CORE 894dd708413SRajendra Nayak */ 89556ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 896dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5) 897dd708413SRajendra Nayak 898dd708413SRajendra Nayak /* 899dd708413SRajendra Nayak * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, 900dd708413SRajendra Nayak * CM_DIV_M7_DPLL_CORE 901dd708413SRajendra Nayak */ 90256ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 903dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8) 904dd708413SRajendra Nayak 905dd708413SRajendra Nayak /* 906dd708413SRajendra Nayak * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, 907dd708413SRajendra Nayak * CM_DIV_M7_DPLL_CORE 908dd708413SRajendra Nayak */ 90956ef28acSRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 910dd708413SRajendra Nayak #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12) 911dd708413SRajendra Nayak 912dd708413SRajendra Nayak /* 913dd708413SRajendra Nayak * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, 914dd708413SRajendra Nayak * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, 915dd708413SRajendra Nayak * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, 916dd708413SRajendra Nayak * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, 917dd708413SRajendra Nayak * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, 918dd708413SRajendra Nayak * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 919dd708413SRajendra Nayak * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, 920dd708413SRajendra Nayak * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, 921dd708413SRajendra Nayak * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, 922dd708413SRajendra Nayak * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, 923dd708413SRajendra Nayak * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, 924dd708413SRajendra Nayak * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, 925dd708413SRajendra Nayak * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, 926dd708413SRajendra Nayak * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, 927dd708413SRajendra Nayak * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, 928dd708413SRajendra Nayak * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, 929dd708413SRajendra Nayak * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, 930dd708413SRajendra Nayak * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, 931dd708413SRajendra Nayak * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, 932dd708413SRajendra Nayak * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, 933dd708413SRajendra Nayak * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, 934dd708413SRajendra Nayak * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, 935dd708413SRajendra Nayak * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, 936dd708413SRajendra Nayak * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, 937dd708413SRajendra Nayak * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, 938dd708413SRajendra Nayak * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, 939dd708413SRajendra Nayak * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, 940dd708413SRajendra Nayak * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, 941dd708413SRajendra Nayak * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, 942dd708413SRajendra Nayak * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, 943dd708413SRajendra Nayak * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 944dd708413SRajendra Nayak * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 945dd708413SRajendra Nayak * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 946dd708413SRajendra Nayak * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 947dd708413SRajendra Nayak * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, 948dd708413SRajendra Nayak * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, 949dd708413SRajendra Nayak * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 950dd708413SRajendra Nayak * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, 951dd708413SRajendra Nayak * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, 952dd708413SRajendra Nayak * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 953dd708413SRajendra Nayak * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 954dd708413SRajendra Nayak * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 955dd708413SRajendra Nayak * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, 956dd708413SRajendra Nayak * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, 957dd708413SRajendra Nayak * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, 958dd708413SRajendra Nayak * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, 959dd708413SRajendra Nayak * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, 960dd708413SRajendra Nayak * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, 961dd708413SRajendra Nayak * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, 962dd708413SRajendra Nayak * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, 963dd708413SRajendra Nayak * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL 964dd708413SRajendra Nayak */ 96556ef28acSRajendra Nayak #define OMAP4430_IDLEST_SHIFT 16 966dd708413SRajendra Nayak #define OMAP4430_IDLEST_MASK BITFIELD(16, 17) 967dd708413SRajendra Nayak 968dd708413SRajendra Nayak /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ 96956ef28acSRajendra Nayak #define OMAP4430_ISS_DYNDEP_SHIFT 9 970dd708413SRajendra Nayak #define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9) 971dd708413SRajendra Nayak 972dd708413SRajendra Nayak /* 973dd708413SRajendra Nayak * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, 974dd708413SRajendra Nayak * CM_MPU_STATICDEP, CM_TESLA_STATICDEP 975dd708413SRajendra Nayak */ 97656ef28acSRajendra Nayak #define OMAP4430_ISS_STATDEP_SHIFT 9 977dd708413SRajendra Nayak #define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9) 978dd708413SRajendra Nayak 979dd708413SRajendra Nayak /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ 98056ef28acSRajendra Nayak #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 981dd708413SRajendra Nayak #define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2) 982dd708413SRajendra Nayak 983dd708413SRajendra Nayak /* 984dd708413SRajendra Nayak * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 985dd708413SRajendra Nayak * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, 986dd708413SRajendra Nayak * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP, 987dd708413SRajendra Nayak * CM_TESLA_STATICDEP 988dd708413SRajendra Nayak */ 98956ef28acSRajendra Nayak #define OMAP4430_IVAHD_STATDEP_SHIFT 2 990dd708413SRajendra Nayak #define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2) 991dd708413SRajendra Nayak 992dd708413SRajendra Nayak /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ 99356ef28acSRajendra Nayak #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 994dd708413SRajendra Nayak #define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7) 995dd708413SRajendra Nayak 996dd708413SRajendra Nayak /* 997dd708413SRajendra Nayak * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 998dd708413SRajendra Nayak * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP 999dd708413SRajendra Nayak */ 100056ef28acSRajendra Nayak #define OMAP4430_L3INIT_STATDEP_SHIFT 7 1001dd708413SRajendra Nayak #define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7) 1002dd708413SRajendra Nayak 1003dd708413SRajendra Nayak /* 1004dd708413SRajendra Nayak * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, 1005dd708413SRajendra Nayak * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP 1006dd708413SRajendra Nayak */ 100756ef28acSRajendra Nayak #define OMAP4430_L3_1_DYNDEP_SHIFT 5 1008dd708413SRajendra Nayak #define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5) 1009dd708413SRajendra Nayak 1010dd708413SRajendra Nayak /* 1011dd708413SRajendra Nayak * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 1012dd708413SRajendra Nayak * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, 1013dd708413SRajendra Nayak * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, 1014dd708413SRajendra Nayak * CM_MPU_STATICDEP, CM_TESLA_STATICDEP 1015dd708413SRajendra Nayak */ 101656ef28acSRajendra Nayak #define OMAP4430_L3_1_STATDEP_SHIFT 5 1017dd708413SRajendra Nayak #define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5) 1018dd708413SRajendra Nayak 1019dd708413SRajendra Nayak /* 1020dd708413SRajendra Nayak * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, 1021dd708413SRajendra Nayak * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP, 1022dd708413SRajendra Nayak * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, 1023dd708413SRajendra Nayak * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP 1024dd708413SRajendra Nayak */ 102556ef28acSRajendra Nayak #define OMAP4430_L3_2_DYNDEP_SHIFT 6 1026dd708413SRajendra Nayak #define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6) 1027dd708413SRajendra Nayak 1028dd708413SRajendra Nayak /* 1029dd708413SRajendra Nayak * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 1030dd708413SRajendra Nayak * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, 1031dd708413SRajendra Nayak * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, 1032dd708413SRajendra Nayak * CM_MPU_STATICDEP, CM_TESLA_STATICDEP 1033dd708413SRajendra Nayak */ 103456ef28acSRajendra Nayak #define OMAP4430_L3_2_STATDEP_SHIFT 6 1035dd708413SRajendra Nayak #define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6) 1036dd708413SRajendra Nayak 1037dd708413SRajendra Nayak /* Used by CM_L3_1_DYNAMICDEP */ 103856ef28acSRajendra Nayak #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 1039dd708413SRajendra Nayak #define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12) 1040dd708413SRajendra Nayak 1041dd708413SRajendra Nayak /* 1042dd708413SRajendra Nayak * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 1043dd708413SRajendra Nayak * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, 1044dd708413SRajendra Nayak * CM_TESLA_STATICDEP 1045dd708413SRajendra Nayak */ 104656ef28acSRajendra Nayak #define OMAP4430_L4CFG_STATDEP_SHIFT 12 1047dd708413SRajendra Nayak #define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12) 1048dd708413SRajendra Nayak 1049dd708413SRajendra Nayak /* Used by CM_L3_2_DYNAMICDEP */ 105056ef28acSRajendra Nayak #define OMAP4430_L4PER_DYNDEP_SHIFT 13 1051dd708413SRajendra Nayak #define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13) 1052dd708413SRajendra Nayak 1053dd708413SRajendra Nayak /* 1054dd708413SRajendra Nayak * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 1055dd708413SRajendra Nayak * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, 1056dd708413SRajendra Nayak * CM_MPU_STATICDEP, CM_TESLA_STATICDEP 1057dd708413SRajendra Nayak */ 105856ef28acSRajendra Nayak #define OMAP4430_L4PER_STATDEP_SHIFT 13 1059dd708413SRajendra Nayak #define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13) 1060dd708413SRajendra Nayak 1061dd708413SRajendra Nayak /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ 106256ef28acSRajendra Nayak #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 1063dd708413SRajendra Nayak #define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14) 1064dd708413SRajendra Nayak 1065dd708413SRajendra Nayak /* 1066dd708413SRajendra Nayak * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, 1067dd708413SRajendra Nayak * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP 1068dd708413SRajendra Nayak */ 106956ef28acSRajendra Nayak #define OMAP4430_L4SEC_STATDEP_SHIFT 14 1070dd708413SRajendra Nayak #define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14) 1071dd708413SRajendra Nayak 1072dd708413SRajendra Nayak /* Used by CM_L4CFG_DYNAMICDEP */ 107356ef28acSRajendra Nayak #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 1074dd708413SRajendra Nayak #define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15) 1075dd708413SRajendra Nayak 1076dd708413SRajendra Nayak /* 1077dd708413SRajendra Nayak * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, 1078dd708413SRajendra Nayak * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP 1079dd708413SRajendra Nayak */ 108056ef28acSRajendra Nayak #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 1081dd708413SRajendra Nayak #define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15) 1082dd708413SRajendra Nayak 1083dd708413SRajendra Nayak /* 1084dd708413SRajendra Nayak * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, 1085dd708413SRajendra Nayak * CM_MPU_DYNAMICDEP 1086dd708413SRajendra Nayak */ 108756ef28acSRajendra Nayak #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 1088dd708413SRajendra Nayak #define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4) 1089dd708413SRajendra Nayak 1090dd708413SRajendra Nayak /* 1091dd708413SRajendra Nayak * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 1092dd708413SRajendra Nayak * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, 1093dd708413SRajendra Nayak * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, 1094dd708413SRajendra Nayak * CM_MPU_STATICDEP, CM_TESLA_STATICDEP 1095dd708413SRajendra Nayak */ 109656ef28acSRajendra Nayak #define OMAP4430_MEMIF_STATDEP_SHIFT 4 1097dd708413SRajendra Nayak #define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4) 1098dd708413SRajendra Nayak 1099dd708413SRajendra Nayak /* 1100dd708413SRajendra Nayak * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1101dd708413SRajendra Nayak * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, 1102dd708413SRajendra Nayak * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1103dd708413SRajendra Nayak * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, 1104dd708413SRajendra Nayak * CM_SSC_MODFREQDIV_DPLL_MPU 1105dd708413SRajendra Nayak */ 110656ef28acSRajendra Nayak #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 1107dd708413SRajendra Nayak #define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10) 1108dd708413SRajendra Nayak 1109dd708413SRajendra Nayak /* 1110dd708413SRajendra Nayak * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1111dd708413SRajendra Nayak * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, 1112dd708413SRajendra Nayak * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1113dd708413SRajendra Nayak * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, 1114dd708413SRajendra Nayak * CM_SSC_MODFREQDIV_DPLL_MPU 1115dd708413SRajendra Nayak */ 111656ef28acSRajendra Nayak #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 1117dd708413SRajendra Nayak #define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6) 1118dd708413SRajendra Nayak 1119dd708413SRajendra Nayak /* 1120dd708413SRajendra Nayak * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, 1121dd708413SRajendra Nayak * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, 1122dd708413SRajendra Nayak * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, 1123dd708413SRajendra Nayak * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, 1124dd708413SRajendra Nayak * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, 1125dd708413SRajendra Nayak * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 1126dd708413SRajendra Nayak * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, 1127dd708413SRajendra Nayak * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, 1128dd708413SRajendra Nayak * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, 1129dd708413SRajendra Nayak * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, 1130dd708413SRajendra Nayak * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, 1131dd708413SRajendra Nayak * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, 1132dd708413SRajendra Nayak * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, 1133dd708413SRajendra Nayak * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, 1134dd708413SRajendra Nayak * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, 1135dd708413SRajendra Nayak * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, 1136dd708413SRajendra Nayak * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, 1137dd708413SRajendra Nayak * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, 1138dd708413SRajendra Nayak * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, 1139dd708413SRajendra Nayak * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, 1140dd708413SRajendra Nayak * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, 1141dd708413SRajendra Nayak * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, 1142dd708413SRajendra Nayak * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, 1143dd708413SRajendra Nayak * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, 1144dd708413SRajendra Nayak * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, 1145dd708413SRajendra Nayak * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, 1146dd708413SRajendra Nayak * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, 1147dd708413SRajendra Nayak * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, 1148dd708413SRajendra Nayak * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, 1149dd708413SRajendra Nayak * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, 1150dd708413SRajendra Nayak * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1151dd708413SRajendra Nayak * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1152dd708413SRajendra Nayak * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1153dd708413SRajendra Nayak * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 1154dd708413SRajendra Nayak * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, 1155dd708413SRajendra Nayak * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, 1156dd708413SRajendra Nayak * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 1157dd708413SRajendra Nayak * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, 1158dd708413SRajendra Nayak * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, 1159dd708413SRajendra Nayak * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1160dd708413SRajendra Nayak * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1161dd708413SRajendra Nayak * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 1162dd708413SRajendra Nayak * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, 1163dd708413SRajendra Nayak * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, 1164dd708413SRajendra Nayak * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, 1165dd708413SRajendra Nayak * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, 1166dd708413SRajendra Nayak * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, 1167dd708413SRajendra Nayak * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, 1168dd708413SRajendra Nayak * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, 1169dd708413SRajendra Nayak * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, 1170dd708413SRajendra Nayak * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL 1171dd708413SRajendra Nayak */ 117256ef28acSRajendra Nayak #define OMAP4430_MODULEMODE_SHIFT 0 1173dd708413SRajendra Nayak #define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1) 1174dd708413SRajendra Nayak 1175dd708413SRajendra Nayak /* Used by CM_DSS_DSS_CLKCTRL */ 117656ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 1177dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9) 1178dd708413SRajendra Nayak 1179dd708413SRajendra Nayak /* Used by CM_WKUP_BANDGAP_CLKCTRL */ 118056ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 1181dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8) 1182dd708413SRajendra Nayak 1183dd708413SRajendra Nayak /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ 118456ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 9 1185dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9) 1186dd708413SRajendra Nayak 1187dd708413SRajendra Nayak /* Used by CM_CAM_ISS_CLKCTRL */ 118856ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 1189dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8) 1190dd708413SRajendra Nayak 1191dd708413SRajendra Nayak /* 1192dd708413SRajendra Nayak * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, 1193dd708413SRajendra Nayak * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, 1194dd708413SRajendra Nayak * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1195dd708413SRajendra Nayak * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1196dd708413SRajendra Nayak * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE 1197dd708413SRajendra Nayak */ 119856ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 1199dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8) 1200dd708413SRajendra Nayak 1201dd708413SRajendra Nayak /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ 120256ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 1203dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8) 1204dd708413SRajendra Nayak 1205dd708413SRajendra Nayak /* Used by CM_DSS_DSS_CLKCTRL */ 120656ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 1207dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8) 1208dd708413SRajendra Nayak 1209dd708413SRajendra Nayak /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ 121056ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 1211dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8) 1212dd708413SRajendra Nayak 1213dd708413SRajendra Nayak /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ 121456ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 1215dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9) 1216dd708413SRajendra Nayak 1217dd708413SRajendra Nayak /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ 121856ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 1219dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10) 1220dd708413SRajendra Nayak 1221dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 122256ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 1223dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15) 1224dd708413SRajendra Nayak 1225dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 122656ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 1227dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13) 1228dd708413SRajendra Nayak 1229dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 123056ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 1231dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14) 1232dd708413SRajendra Nayak 1233dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 123456ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 1235dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11) 1236dd708413SRajendra Nayak 1237dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 123856ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 1239dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12) 1240dd708413SRajendra Nayak 1241dd708413SRajendra Nayak /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ 124256ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 1243dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8) 1244dd708413SRajendra Nayak 1245dd708413SRajendra Nayak /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ 124656ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 1247dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9) 1248dd708413SRajendra Nayak 1249dd708413SRajendra Nayak /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ 125056ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 1251dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8) 1252dd708413SRajendra Nayak 1253dd708413SRajendra Nayak /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ 125456ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 1255dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10) 1256dd708413SRajendra Nayak 1257dd708413SRajendra Nayak /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ 125856ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 1259dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11) 1260dd708413SRajendra Nayak 1261dd708413SRajendra Nayak /* Used by CM_DSS_DSS_CLKCTRL */ 126256ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 1263dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10) 1264dd708413SRajendra Nayak 1265dd708413SRajendra Nayak /* Used by CM_DSS_DSS_CLKCTRL */ 126656ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 1267dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11) 1268dd708413SRajendra Nayak 1269dd708413SRajendra Nayak /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ 127056ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 1271dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8) 1272dd708413SRajendra Nayak 1273dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 127456ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 1275dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8) 1276dd708413SRajendra Nayak 1277dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 127856ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 1279dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9) 1280dd708413SRajendra Nayak 1281dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 128256ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 1283dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10) 1284dd708413SRajendra Nayak 1285dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 128656ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 1287dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8) 1288dd708413SRajendra Nayak 1289dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 129056ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 1291dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9) 1292dd708413SRajendra Nayak 1293dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 129456ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 1295dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10) 1296dd708413SRajendra Nayak 1297dd708413SRajendra Nayak /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ 129856ef28acSRajendra Nayak #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 1299dd708413SRajendra Nayak #define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8) 1300dd708413SRajendra Nayak 1301dd708413SRajendra Nayak /* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */ 130256ef28acSRajendra Nayak #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 1303dd708413SRajendra Nayak #define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19) 1304dd708413SRajendra Nayak 1305dd708413SRajendra Nayak /* Used by CM_CLKSEL_ABE */ 130656ef28acSRajendra Nayak #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 1307dd708413SRajendra Nayak #define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8) 1308dd708413SRajendra Nayak 1309dd708413SRajendra Nayak /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ 131056ef28acSRajendra Nayak #define OMAP4430_PERF_CURRENT_SHIFT 0 1311dd708413SRajendra Nayak #define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7) 1312dd708413SRajendra Nayak 1313dd708413SRajendra Nayak /* 1314dd708413SRajendra Nayak * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, 1315dd708413SRajendra Nayak * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, 1316dd708413SRajendra Nayak * CM_IVA_DVFS_PERF_TESLA 1317dd708413SRajendra Nayak */ 131856ef28acSRajendra Nayak #define OMAP4430_PERF_REQ_SHIFT 0 1319dd708413SRajendra Nayak #define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7) 1320dd708413SRajendra Nayak 1321dd708413SRajendra Nayak /* Used by CM_EMU_OVERRIDE_DPLL_PER */ 132256ef28acSRajendra Nayak #define OMAP4430_PER_DPLL_EMU_DIV_SHIFT 0 1323dd708413SRajendra Nayak #define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6) 1324dd708413SRajendra Nayak 1325dd708413SRajendra Nayak /* Used by CM_EMU_OVERRIDE_DPLL_PER */ 132656ef28acSRajendra Nayak #define OMAP4430_PER_DPLL_EMU_MULT_SHIFT 8 1327dd708413SRajendra Nayak #define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18) 1328dd708413SRajendra Nayak 1329dd708413SRajendra Nayak /* Used by CM_RESTORE_ST */ 133056ef28acSRajendra Nayak #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 1331dd708413SRajendra Nayak #define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0) 1332dd708413SRajendra Nayak 1333dd708413SRajendra Nayak /* Used by CM_RESTORE_ST */ 133456ef28acSRajendra Nayak #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 1335dd708413SRajendra Nayak #define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1) 1336dd708413SRajendra Nayak 1337dd708413SRajendra Nayak /* Used by CM_RESTORE_ST */ 133856ef28acSRajendra Nayak #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 1339dd708413SRajendra Nayak #define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2) 1340dd708413SRajendra Nayak 1341dd708413SRajendra Nayak /* Used by CM_EMU_DEBUGSS_CLKCTRL */ 134256ef28acSRajendra Nayak #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 1343dd708413SRajendra Nayak #define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21) 1344dd708413SRajendra Nayak 1345dd708413SRajendra Nayak /* Used by CM_EMU_DEBUGSS_CLKCTRL */ 134656ef28acSRajendra Nayak #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 1347dd708413SRajendra Nayak #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23) 1348dd708413SRajendra Nayak 1349dd708413SRajendra Nayak /* Used by CM_DYN_DEP_PRESCAL */ 135056ef28acSRajendra Nayak #define OMAP4430_PRESCAL_SHIFT 0 1351dd708413SRajendra Nayak #define OMAP4430_PRESCAL_MASK BITFIELD(0, 5) 1352dd708413SRajendra Nayak 1353dd708413SRajendra Nayak /* Used by REVISION_CM2, REVISION_CM1 */ 135456ef28acSRajendra Nayak #define OMAP4430_REV_SHIFT 0 1355dd708413SRajendra Nayak #define OMAP4430_REV_MASK BITFIELD(0, 7) 1356dd708413SRajendra Nayak 1357dd708413SRajendra Nayak /* 1358dd708413SRajendra Nayak * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, 1359dd708413SRajendra Nayak * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE 1360dd708413SRajendra Nayak */ 136156ef28acSRajendra Nayak #define OMAP4430_SAR_MODE_SHIFT 4 1362dd708413SRajendra Nayak #define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4) 1363dd708413SRajendra Nayak 1364dd708413SRajendra Nayak /* Used by CM_SCALE_FCLK */ 136556ef28acSRajendra Nayak #define OMAP4430_SCALE_FCLK_SHIFT 0 1366dd708413SRajendra Nayak #define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0) 1367dd708413SRajendra Nayak 1368dd708413SRajendra Nayak /* Used by CM_L4CFG_DYNAMICDEP */ 136956ef28acSRajendra Nayak #define OMAP4430_SDMA_DYNDEP_SHIFT 11 1370dd708413SRajendra Nayak #define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11) 1371dd708413SRajendra Nayak 1372dd708413SRajendra Nayak /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ 137356ef28acSRajendra Nayak #define OMAP4430_SDMA_STATDEP_SHIFT 11 1374dd708413SRajendra Nayak #define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11) 1375dd708413SRajendra Nayak 1376dd708413SRajendra Nayak /* Used by CM_CLKSEL_ABE */ 137756ef28acSRajendra Nayak #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 1378dd708413SRajendra Nayak #define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10) 1379dd708413SRajendra Nayak 1380dd708413SRajendra Nayak /* 1381dd708413SRajendra Nayak * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, 1382dd708413SRajendra Nayak * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, 1383dd708413SRajendra Nayak * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, 1384dd708413SRajendra Nayak * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1385dd708413SRajendra Nayak * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1386dd708413SRajendra Nayak * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1387dd708413SRajendra Nayak * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, 1388dd708413SRajendra Nayak * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, 1389dd708413SRajendra Nayak * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, 1390dd708413SRajendra Nayak * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, 1391dd708413SRajendra Nayak * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL 1392dd708413SRajendra Nayak */ 139356ef28acSRajendra Nayak #define OMAP4430_STBYST_SHIFT 18 1394dd708413SRajendra Nayak #define OMAP4430_STBYST_MASK BITFIELD(18, 18) 1395dd708413SRajendra Nayak 1396dd708413SRajendra Nayak /* 1397dd708413SRajendra Nayak * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB, 1398dd708413SRajendra Nayak * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, 1399dd708413SRajendra Nayak * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU 1400dd708413SRajendra Nayak */ 140156ef28acSRajendra Nayak #define OMAP4430_ST_DPLL_CLK_SHIFT 0 1402dd708413SRajendra Nayak #define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0) 1403dd708413SRajendra Nayak 1404dd708413SRajendra Nayak /* Used by CM_CLKDCOLDO_DPLL_USB */ 140556ef28acSRajendra Nayak #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 1406dd708413SRajendra Nayak #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9) 1407dd708413SRajendra Nayak 1408dd708413SRajendra Nayak /* 1409dd708413SRajendra Nayak * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, 1410dd708413SRajendra Nayak * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, 1411dd708413SRajendra Nayak * CM_DIV_M2_DPLL_MPU 1412dd708413SRajendra Nayak */ 141356ef28acSRajendra Nayak #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 1414dd708413SRajendra Nayak #define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9) 1415dd708413SRajendra Nayak 1416dd708413SRajendra Nayak /* 1417dd708413SRajendra Nayak * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, 1418dd708413SRajendra Nayak * CM_DIV_M3_DPLL_CORE 1419dd708413SRajendra Nayak */ 142056ef28acSRajendra Nayak #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 1421dd708413SRajendra Nayak #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9) 1422dd708413SRajendra Nayak 1423dd708413SRajendra Nayak /* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ 142456ef28acSRajendra Nayak #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 1425dd708413SRajendra Nayak #define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11) 1426dd708413SRajendra Nayak 1427dd708413SRajendra Nayak /* 1428dd708413SRajendra Nayak * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, 1429dd708413SRajendra Nayak * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA 1430dd708413SRajendra Nayak */ 143156ef28acSRajendra Nayak #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 1432dd708413SRajendra Nayak #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9) 1433dd708413SRajendra Nayak 1434dd708413SRajendra Nayak /* 1435dd708413SRajendra Nayak * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, 1436dd708413SRajendra Nayak * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA 1437dd708413SRajendra Nayak */ 143856ef28acSRajendra Nayak #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 1439dd708413SRajendra Nayak #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9) 1440dd708413SRajendra Nayak 1441dd708413SRajendra Nayak /* 1442dd708413SRajendra Nayak * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, 1443dd708413SRajendra Nayak * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY 1444dd708413SRajendra Nayak */ 144556ef28acSRajendra Nayak #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 1446dd708413SRajendra Nayak #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9) 1447dd708413SRajendra Nayak 1448dd708413SRajendra Nayak /* 1449dd708413SRajendra Nayak * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, 1450dd708413SRajendra Nayak * CM_DIV_M7_DPLL_CORE 1451dd708413SRajendra Nayak */ 145256ef28acSRajendra Nayak #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 1453dd708413SRajendra Nayak #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9) 1454dd708413SRajendra Nayak 1455dd708413SRajendra Nayak /* Used by CM_SYS_CLKSEL */ 145656ef28acSRajendra Nayak #define OMAP4430_SYS_CLKSEL_SHIFT 0 1457dd708413SRajendra Nayak #define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2) 1458dd708413SRajendra Nayak 1459dd708413SRajendra Nayak /* Used by CM_L4CFG_DYNAMICDEP */ 146056ef28acSRajendra Nayak #define OMAP4430_TESLA_DYNDEP_SHIFT 1 1461dd708413SRajendra Nayak #define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1) 1462dd708413SRajendra Nayak 1463dd708413SRajendra Nayak /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ 146456ef28acSRajendra Nayak #define OMAP4430_TESLA_STATDEP_SHIFT 1 1465dd708413SRajendra Nayak #define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1) 1466dd708413SRajendra Nayak 1467dd708413SRajendra Nayak /* 1468dd708413SRajendra Nayak * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, 1469dd708413SRajendra Nayak * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, 1470dd708413SRajendra Nayak * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP 1471dd708413SRajendra Nayak */ 147256ef28acSRajendra Nayak #define OMAP4430_WINDOWSIZE_SHIFT 24 1473dd708413SRajendra Nayak #define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27) 1474dd708413SRajendra Nayak #endif 1475