1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2010 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include <linux/list.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/clk-provider.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 #include <linux/regmap.h> 27 #include <linux/of_address.h> 28 #include <linux/bootmem.h> 29 #include <asm/cpu.h> 30 31 #include <trace/events/power.h> 32 33 #include "soc.h" 34 #include "clockdomain.h" 35 #include "clock.h" 36 #include "cm.h" 37 #include "cm2xxx.h" 38 #include "cm3xxx.h" 39 #include "cm-regbits-24xx.h" 40 #include "cm-regbits-34xx.h" 41 #include "common.h" 42 43 /* 44 * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait 45 * for a module to indicate that it is no longer in idle 46 */ 47 #define MAX_MODULE_ENABLE_WAIT 100000 48 49 u16 cpu_mask; 50 51 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ 52 #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 53 #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 54 #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 55 #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 56 57 /* 58 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. 59 * From device data manual section 4.3 "DPLL and DLL Specifications". 60 */ 61 #define OMAP3PLUS_DPLL_FINT_MIN 32000 62 #define OMAP3PLUS_DPLL_FINT_MAX 52000000 63 64 /* 65 * clkdm_control: if true, then when a clock is enabled in the 66 * hardware, its clockdomain will first be enabled; and when a clock 67 * is disabled in the hardware, its clockdomain will be disabled 68 * afterwards. 69 */ 70 static bool clkdm_control = true; 71 72 static LIST_HEAD(clk_hw_omap_clocks); 73 74 struct clk_iomap { 75 struct regmap *regmap; 76 void __iomem *mem; 77 }; 78 79 static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS]; 80 81 static void clk_memmap_writel(u32 val, void __iomem *reg) 82 { 83 struct clk_omap_reg *r = (struct clk_omap_reg *)® 84 struct clk_iomap *io = clk_memmaps[r->index]; 85 86 if (io->regmap) 87 regmap_write(io->regmap, r->offset, val); 88 else 89 writel_relaxed(val, io->mem + r->offset); 90 } 91 92 static u32 clk_memmap_readl(void __iomem *reg) 93 { 94 u32 val; 95 struct clk_omap_reg *r = (struct clk_omap_reg *)® 96 struct clk_iomap *io = clk_memmaps[r->index]; 97 98 if (io->regmap) 99 regmap_read(io->regmap, r->offset, &val); 100 else 101 val = readl_relaxed(io->mem + r->offset); 102 103 return val; 104 } 105 106 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) 107 { 108 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) 109 writel_relaxed(val, reg); 110 else 111 clk_memmap_writel(val, reg); 112 } 113 114 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) 115 { 116 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) 117 return readl_relaxed(reg); 118 else 119 return clk_memmap_readl(reg); 120 } 121 122 static struct ti_clk_ll_ops omap_clk_ll_ops = { 123 .clk_readl = clk_memmap_readl, 124 .clk_writel = clk_memmap_writel, 125 }; 126 127 /** 128 * omap2_clk_provider_init - initialize a clock provider 129 * @match_table: DT device table to match for devices to init 130 * @np: device node pointer for the this clock provider 131 * @index: index for the clock provider 132 + @syscon: syscon regmap pointer 133 * @mem: iomem pointer for the clock provider memory area, only used if 134 * syscon is not provided 135 * 136 * Initializes a clock provider module (CM/PRM etc.), registering 137 * the memory mapping at specified index and initializing the 138 * low level driver infrastructure. Returns 0 in success. 139 */ 140 int __init omap2_clk_provider_init(struct device_node *np, int index, 141 struct regmap *syscon, void __iomem *mem) 142 { 143 struct clk_iomap *io; 144 145 ti_clk_ll_ops = &omap_clk_ll_ops; 146 147 io = kzalloc(sizeof(*io), GFP_KERNEL); 148 149 io->regmap = syscon; 150 io->mem = mem; 151 152 clk_memmaps[index] = io; 153 154 ti_dt_clk_init_provider(np, index); 155 156 return 0; 157 } 158 159 /** 160 * omap2_clk_legacy_provider_init - initialize a legacy clock provider 161 * @index: index for the clock provider 162 * @mem: iomem pointer for the clock provider memory area 163 * 164 * Initializes a legacy clock provider memory mapping. 165 */ 166 void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem) 167 { 168 struct clk_iomap *io; 169 170 ti_clk_ll_ops = &omap_clk_ll_ops; 171 172 io = memblock_virt_alloc(sizeof(*io), 0); 173 174 io->mem = mem; 175 176 clk_memmaps[index] = io; 177 } 178 179 /* 180 * OMAP2+ specific clock functions 181 */ 182 183 /* Private functions */ 184 185 186 /** 187 * _wait_idlest_generic - wait for a module to leave the idle state 188 * @clk: module clock to wait for (needed for register offsets) 189 * @reg: virtual address of module IDLEST register 190 * @mask: value to mask against to determine if the module is active 191 * @idlest: idle state indicator (0 or 1) for the clock 192 * @name: name of the clock (for printk) 193 * 194 * Wait for a module to leave idle, where its idle-status register is 195 * not inside the CM module. Returns 1 if the module left idle 196 * promptly, or 0 if the module did not leave idle before the timeout 197 * elapsed. XXX Deprecated - should be moved into drivers for the 198 * individual IP block that the IDLEST register exists in. 199 */ 200 static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, 201 u32 mask, u8 idlest, const char *name) 202 { 203 int i = 0, ena = 0; 204 205 ena = (idlest) ? 0 : mask; 206 207 omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), 208 MAX_MODULE_ENABLE_WAIT, i); 209 210 if (i < MAX_MODULE_ENABLE_WAIT) 211 pr_debug("omap clock: module associated with clock %s ready after %d loops\n", 212 name, i); 213 else 214 pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", 215 name, MAX_MODULE_ENABLE_WAIT); 216 217 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; 218 }; 219 220 /** 221 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE 222 * @clk: struct clk * belonging to the module 223 * 224 * If the necessary clocks for the OMAP hardware IP block that 225 * corresponds to clock @clk are enabled, then wait for the module to 226 * indicate readiness (i.e., to leave IDLE). This code does not 227 * belong in the clock code and will be moved in the medium term to 228 * module-dependent code. No return value. 229 */ 230 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) 231 { 232 void __iomem *companion_reg, *idlest_reg; 233 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; 234 s16 prcm_mod; 235 int r; 236 237 /* Not all modules have multiple clocks that their IDLEST depends on */ 238 if (clk->ops->find_companion) { 239 clk->ops->find_companion(clk, &companion_reg, &other_bit); 240 if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) 241 return; 242 } 243 244 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 245 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); 246 if (r) { 247 /* IDLEST register not in the CM module */ 248 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), 249 idlest_val, __clk_get_name(clk->hw.clk)); 250 } else { 251 omap_cm_wait_module_ready(0, prcm_mod, idlest_reg_id, 252 idlest_bit); 253 }; 254 } 255 256 /* Public functions */ 257 258 /** 259 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 260 * @clk: OMAP clock struct ptr to use 261 * 262 * Convert a clockdomain name stored in a struct clk 'clk' into a 263 * clockdomain pointer, and save it into the struct clk. Intended to be 264 * called during clk_register(). No return value. 265 */ 266 void omap2_init_clk_clkdm(struct clk_hw *hw) 267 { 268 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 269 struct clockdomain *clkdm; 270 const char *clk_name; 271 272 if (!clk->clkdm_name) 273 return; 274 275 clk_name = __clk_get_name(hw->clk); 276 277 clkdm = clkdm_lookup(clk->clkdm_name); 278 if (clkdm) { 279 pr_debug("clock: associated clk %s to clkdm %s\n", 280 clk_name, clk->clkdm_name); 281 clk->clkdm = clkdm; 282 } else { 283 pr_debug("clock: could not associate clk %s to clkdm %s\n", 284 clk_name, clk->clkdm_name); 285 } 286 } 287 288 /** 289 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable 290 * 291 * Prevent the OMAP clock code from calling into the clockdomain code 292 * when a hardware clock in that clockdomain is enabled or disabled. 293 * Intended to be called at init time from omap*_clk_init(). No 294 * return value. 295 */ 296 void __init omap2_clk_disable_clkdm_control(void) 297 { 298 clkdm_control = false; 299 } 300 301 /** 302 * omap2_clk_dflt_find_companion - find companion clock to @clk 303 * @clk: struct clk * to find the companion clock of 304 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 305 * @other_bit: u8 ** to return the companion clock bit shift in 306 * 307 * Note: We don't need special code here for INVERT_ENABLE for the 308 * time being since INVERT_ENABLE only applies to clocks enabled by 309 * CM_CLKEN_PLL 310 * 311 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 312 * just a matter of XORing the bits. 313 * 314 * Some clocks don't have companion clocks. For example, modules with 315 * only an interface clock (such as MAILBOXES) don't have a companion 316 * clock. Right now, this code relies on the hardware exporting a bit 317 * in the correct companion register that indicates that the 318 * nonexistent 'companion clock' is active. Future patches will 319 * associate this type of code with per-module data structures to 320 * avoid this issue, and remove the casts. No return value. 321 */ 322 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 323 void __iomem **other_reg, u8 *other_bit) 324 { 325 u32 r; 326 327 /* 328 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 329 * it's just a matter of XORing the bits. 330 */ 331 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 332 333 *other_reg = (__force void __iomem *)r; 334 *other_bit = clk->enable_bit; 335 } 336 337 /** 338 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 339 * @clk: struct clk * to find IDLEST info for 340 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 341 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in 342 * @idlest_val: u8 * to return the idle status indicator 343 * 344 * Return the CM_IDLEST register address and bit shift corresponding 345 * to the module that "owns" this clock. This default code assumes 346 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 347 * the IDLEST register address ID corresponds to the CM_*CLKEN 348 * register address ID (e.g., that CM_FCLKEN2 corresponds to 349 * CM_IDLEST2). This is not true for all modules. No return value. 350 */ 351 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 352 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) 353 { 354 u32 r; 355 356 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 357 *idlest_reg = (__force void __iomem *)r; 358 *idlest_bit = clk->enable_bit; 359 360 /* 361 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 362 * 34xx reverses this, just to keep us on our toes 363 * AM35xx uses both, depending on the module. 364 */ 365 *idlest_val = ti_clk_get_features()->cm_idlest_val; 366 } 367 368 /** 369 * omap2_dflt_clk_enable - enable a clock in the hardware 370 * @hw: struct clk_hw * of the clock to enable 371 * 372 * Enable the clock @hw in the hardware. We first call into the OMAP 373 * clockdomain code to "enable" the corresponding clockdomain if this 374 * is the first enabled user of the clockdomain. Then program the 375 * hardware to enable the clock. Then wait for the IP block that uses 376 * this clock to leave idle (if applicable). Returns the error value 377 * from clkdm_clk_enable() if it terminated with an error, or -EINVAL 378 * if @hw has a null clock enable_reg, or zero upon success. 379 */ 380 int omap2_dflt_clk_enable(struct clk_hw *hw) 381 { 382 struct clk_hw_omap *clk; 383 u32 v; 384 int ret = 0; 385 386 clk = to_clk_hw_omap(hw); 387 388 if (clkdm_control && clk->clkdm) { 389 ret = clkdm_clk_enable(clk->clkdm, hw->clk); 390 if (ret) { 391 WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", 392 __func__, __clk_get_name(hw->clk), 393 clk->clkdm->name, ret); 394 return ret; 395 } 396 } 397 398 if (unlikely(clk->enable_reg == NULL)) { 399 pr_err("%s: %s missing enable_reg\n", __func__, 400 __clk_get_name(hw->clk)); 401 ret = -EINVAL; 402 goto err; 403 } 404 405 /* FIXME should not have INVERT_ENABLE bit here */ 406 v = omap2_clk_readl(clk, clk->enable_reg); 407 if (clk->flags & INVERT_ENABLE) 408 v &= ~(1 << clk->enable_bit); 409 else 410 v |= (1 << clk->enable_bit); 411 omap2_clk_writel(v, clk, clk->enable_reg); 412 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ 413 414 if (clk->ops && clk->ops->find_idlest) 415 _omap2_module_wait_ready(clk); 416 417 return 0; 418 419 err: 420 if (clkdm_control && clk->clkdm) 421 clkdm_clk_disable(clk->clkdm, hw->clk); 422 return ret; 423 } 424 425 /** 426 * omap2_dflt_clk_disable - disable a clock in the hardware 427 * @hw: struct clk_hw * of the clock to disable 428 * 429 * Disable the clock @hw in the hardware, and call into the OMAP 430 * clockdomain code to "disable" the corresponding clockdomain if all 431 * clocks/hwmods in that clockdomain are now disabled. No return 432 * value. 433 */ 434 void omap2_dflt_clk_disable(struct clk_hw *hw) 435 { 436 struct clk_hw_omap *clk; 437 u32 v; 438 439 clk = to_clk_hw_omap(hw); 440 if (!clk->enable_reg) { 441 /* 442 * 'independent' here refers to a clock which is not 443 * controlled by its parent. 444 */ 445 pr_err("%s: independent clock %s has no enable_reg\n", 446 __func__, __clk_get_name(hw->clk)); 447 return; 448 } 449 450 v = omap2_clk_readl(clk, clk->enable_reg); 451 if (clk->flags & INVERT_ENABLE) 452 v |= (1 << clk->enable_bit); 453 else 454 v &= ~(1 << clk->enable_bit); 455 omap2_clk_writel(v, clk, clk->enable_reg); 456 /* No OCP barrier needed here since it is a disable operation */ 457 458 if (clkdm_control && clk->clkdm) 459 clkdm_clk_disable(clk->clkdm, hw->clk); 460 } 461 462 /** 463 * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw 464 * @hw: struct clk_hw * of the clock being enabled 465 * 466 * Increment the usecount of the clockdomain of the clock pointed to 467 * by @hw; if the usecount is 1, the clockdomain will be "enabled." 468 * Only needed for clocks that don't use omap2_dflt_clk_enable() as 469 * their enable function pointer. Passes along the return value of 470 * clkdm_clk_enable(), -EINVAL if @hw is not associated with a 471 * clockdomain, or 0 if clock framework-based clockdomain control is 472 * not implemented. 473 */ 474 int omap2_clkops_enable_clkdm(struct clk_hw *hw) 475 { 476 struct clk_hw_omap *clk; 477 int ret = 0; 478 479 clk = to_clk_hw_omap(hw); 480 481 if (unlikely(!clk->clkdm)) { 482 pr_err("%s: %s: no clkdm set ?!\n", __func__, 483 __clk_get_name(hw->clk)); 484 return -EINVAL; 485 } 486 487 if (unlikely(clk->enable_reg)) 488 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, 489 __clk_get_name(hw->clk)); 490 491 if (!clkdm_control) { 492 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 493 __func__, __clk_get_name(hw->clk)); 494 return 0; 495 } 496 497 ret = clkdm_clk_enable(clk->clkdm, hw->clk); 498 WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", 499 __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); 500 501 return ret; 502 } 503 504 /** 505 * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw 506 * @hw: struct clk_hw * of the clock being disabled 507 * 508 * Decrement the usecount of the clockdomain of the clock pointed to 509 * by @hw; if the usecount is 0, the clockdomain will be "disabled." 510 * Only needed for clocks that don't use omap2_dflt_clk_disable() as their 511 * disable function pointer. No return value. 512 */ 513 void omap2_clkops_disable_clkdm(struct clk_hw *hw) 514 { 515 struct clk_hw_omap *clk; 516 517 clk = to_clk_hw_omap(hw); 518 519 if (unlikely(!clk->clkdm)) { 520 pr_err("%s: %s: no clkdm set ?!\n", __func__, 521 __clk_get_name(hw->clk)); 522 return; 523 } 524 525 if (unlikely(clk->enable_reg)) 526 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, 527 __clk_get_name(hw->clk)); 528 529 if (!clkdm_control) { 530 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 531 __func__, __clk_get_name(hw->clk)); 532 return; 533 } 534 535 clkdm_clk_disable(clk->clkdm, hw->clk); 536 } 537 538 /** 539 * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? 540 * @hw: struct clk_hw * to check 541 * 542 * Return 1 if the clock represented by @hw is enabled in the 543 * hardware, or 0 otherwise. Intended for use in the struct 544 * clk_ops.is_enabled function pointer. 545 */ 546 int omap2_dflt_clk_is_enabled(struct clk_hw *hw) 547 { 548 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 549 u32 v; 550 551 v = omap2_clk_readl(clk, clk->enable_reg); 552 553 if (clk->flags & INVERT_ENABLE) 554 v ^= BIT(clk->enable_bit); 555 556 v &= BIT(clk->enable_bit); 557 558 return v ? 1 : 0; 559 } 560 561 static int __initdata mpurate; 562 563 /* 564 * By default we use the rate set by the bootloader. 565 * You can override this with mpurate= cmdline option. 566 */ 567 static int __init omap_clk_setup(char *str) 568 { 569 get_option(&str, &mpurate); 570 571 if (!mpurate) 572 return 1; 573 574 if (mpurate < 1000) 575 mpurate *= 1000000; 576 577 return 1; 578 } 579 __setup("mpurate=", omap_clk_setup); 580 581 /** 582 * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock 583 * @clk: struct clk * to initialize 584 * 585 * Add an OMAP clock @clk to the internal list of OMAP clocks. Used 586 * temporarily for autoidle handling, until this support can be 587 * integrated into the common clock framework code in some way. No 588 * return value. 589 */ 590 void omap2_init_clk_hw_omap_clocks(struct clk *clk) 591 { 592 struct clk_hw_omap *c; 593 594 if (__clk_get_flags(clk) & CLK_IS_BASIC) 595 return; 596 597 c = to_clk_hw_omap(__clk_get_hw(clk)); 598 list_add(&c->node, &clk_hw_omap_clocks); 599 } 600 601 /** 602 * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that 603 * support it 604 * 605 * Enable clock autoidle on all OMAP clocks that have allow_idle 606 * function pointers associated with them. This function is intended 607 * to be temporary until support for this is added to the common clock 608 * code. Returns 0. 609 */ 610 int omap2_clk_enable_autoidle_all(void) 611 { 612 struct clk_hw_omap *c; 613 614 list_for_each_entry(c, &clk_hw_omap_clocks, node) 615 if (c->ops && c->ops->allow_idle) 616 c->ops->allow_idle(c); 617 618 of_ti_clk_allow_autoidle_all(); 619 620 return 0; 621 } 622 623 /** 624 * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that 625 * support it 626 * 627 * Disable clock autoidle on all OMAP clocks that have allow_idle 628 * function pointers associated with them. This function is intended 629 * to be temporary until support for this is added to the common clock 630 * code. Returns 0. 631 */ 632 int omap2_clk_disable_autoidle_all(void) 633 { 634 struct clk_hw_omap *c; 635 636 list_for_each_entry(c, &clk_hw_omap_clocks, node) 637 if (c->ops && c->ops->deny_idle) 638 c->ops->deny_idle(c); 639 640 of_ti_clk_deny_autoidle_all(); 641 642 return 0; 643 } 644 645 /** 646 * omap2_clk_deny_idle - disable autoidle on an OMAP clock 647 * @clk: struct clk * to disable autoidle for 648 * 649 * Disable autoidle on an OMAP clock. 650 */ 651 int omap2_clk_deny_idle(struct clk *clk) 652 { 653 struct clk_hw_omap *c; 654 655 if (__clk_get_flags(clk) & CLK_IS_BASIC) 656 return -EINVAL; 657 658 c = to_clk_hw_omap(__clk_get_hw(clk)); 659 if (c->ops && c->ops->deny_idle) 660 c->ops->deny_idle(c); 661 return 0; 662 } 663 664 /** 665 * omap2_clk_allow_idle - enable autoidle on an OMAP clock 666 * @clk: struct clk * to enable autoidle for 667 * 668 * Enable autoidle on an OMAP clock. 669 */ 670 int omap2_clk_allow_idle(struct clk *clk) 671 { 672 struct clk_hw_omap *c; 673 674 if (__clk_get_flags(clk) & CLK_IS_BASIC) 675 return -EINVAL; 676 677 c = to_clk_hw_omap(__clk_get_hw(clk)); 678 if (c->ops && c->ops->allow_idle) 679 c->ops->allow_idle(c); 680 return 0; 681 } 682 683 /** 684 * omap2_clk_enable_init_clocks - prepare & enable a list of clocks 685 * @clk_names: ptr to an array of strings of clock names to enable 686 * @num_clocks: number of clock names in @clk_names 687 * 688 * Prepare and enable a list of clocks, named by @clk_names. No 689 * return value. XXX Deprecated; only needed until these clocks are 690 * properly claimed and enabled by the drivers or core code that uses 691 * them. XXX What code disables & calls clk_put on these clocks? 692 */ 693 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) 694 { 695 struct clk *init_clk; 696 int i; 697 698 for (i = 0; i < num_clocks; i++) { 699 init_clk = clk_get(NULL, clk_names[i]); 700 if (WARN(IS_ERR(init_clk), "could not find init clock %s\n", 701 clk_names[i])) 702 continue; 703 clk_prepare_enable(init_clk); 704 } 705 } 706 707 const struct clk_hw_omap_ops clkhwops_wait = { 708 .find_idlest = omap2_clk_dflt_find_idlest, 709 .find_companion = omap2_clk_dflt_find_companion, 710 }; 711 712 /** 713 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 714 * @mpurate_ck_name: clk name of the clock to change rate 715 * 716 * Change the ARM MPU clock rate to the rate specified on the command 717 * line, if one was specified. @mpurate_ck_name should be 718 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. 719 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently 720 * handled by the virt_prcm_set clock, but this should be handled by 721 * the OPP layer. XXX This is intended to be handled by the OPP layer 722 * code in the near future and should be removed from the clock code. 723 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects 724 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name 725 * cannot be found, or 0 upon success. 726 */ 727 int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) 728 { 729 struct clk *mpurate_ck; 730 int r; 731 732 if (!mpurate) 733 return -EINVAL; 734 735 mpurate_ck = clk_get(NULL, mpurate_ck_name); 736 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) 737 return -ENOENT; 738 739 r = clk_set_rate(mpurate_ck, mpurate); 740 if (r < 0) { 741 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", 742 mpurate_ck_name, mpurate, r); 743 clk_put(mpurate_ck); 744 return -EINVAL; 745 } 746 747 calibrate_delay(); 748 clk_put(mpurate_ck); 749 750 return 0; 751 } 752 753 /** 754 * omap2_clk_print_new_rates - print summary of current clock tree rates 755 * @hfclkin_ck_name: clk name for the off-chip HF oscillator 756 * @core_ck_name: clk name for the on-chip CORE_CLK 757 * @mpu_ck_name: clk name for the ARM MPU clock 758 * 759 * Prints a short message to the console with the HFCLKIN oscillator 760 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. 761 * Called by the boot-time MPU rate switching code. XXX This is intended 762 * to be handled by the OPP layer code in the near future and should be 763 * removed from the clock code. No return value. 764 */ 765 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, 766 const char *core_ck_name, 767 const char *mpu_ck_name) 768 { 769 struct clk *hfclkin_ck, *core_ck, *mpu_ck; 770 unsigned long hfclkin_rate; 771 772 mpu_ck = clk_get(NULL, mpu_ck_name); 773 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) 774 return; 775 776 core_ck = clk_get(NULL, core_ck_name); 777 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) 778 return; 779 780 hfclkin_ck = clk_get(NULL, hfclkin_ck_name); 781 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) 782 return; 783 784 hfclkin_rate = clk_get_rate(hfclkin_ck); 785 786 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", 787 (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), 788 (clk_get_rate(core_ck) / 1000000), 789 (clk_get_rate(mpu_ck) / 1000000)); 790 } 791 792 /** 793 * ti_clk_init_features - init clock features struct for the SoC 794 * 795 * Initializes the clock features struct based on the SoC type. 796 */ 797 void __init ti_clk_init_features(void) 798 { 799 struct ti_clk_features features = { 0 }; 800 /* Fint setup for DPLLs */ 801 if (cpu_is_omap3430()) { 802 features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; 803 features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; 804 features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; 805 features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; 806 } else { 807 features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; 808 features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; 809 } 810 811 /* Bypass value setup for DPLLs */ 812 if (cpu_is_omap24xx()) { 813 features.dpll_bypass_vals |= 814 (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | 815 (1 << OMAP2XXX_EN_DPLL_FRBYPASS); 816 } else if (cpu_is_omap34xx()) { 817 features.dpll_bypass_vals |= 818 (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | 819 (1 << OMAP3XXX_EN_DPLL_FRBYPASS); 820 } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || 821 soc_is_omap54xx() || soc_is_dra7xx()) { 822 features.dpll_bypass_vals |= 823 (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | 824 (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | 825 (1 << OMAP4XXX_EN_DPLL_MNBYPASS); 826 } 827 828 /* Jitter correction only available on OMAP343X */ 829 if (cpu_is_omap343x()) 830 features.flags |= TI_CLK_DPLL_HAS_FREQSEL; 831 832 /* Idlest value for interface clocks. 833 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 834 * 34xx reverses this, just to keep us on our toes 835 * AM35xx uses both, depending on the module. 836 */ 837 if (cpu_is_omap24xx()) 838 features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; 839 else if (cpu_is_omap34xx()) 840 features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; 841 842 /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */ 843 if (omap_rev() == OMAP3430_REV_ES1_0) 844 features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; 845 846 ti_clk_setup_features(&features); 847 } 848