1 /* 2 * Amstrad E3 FIQ handling 3 * 4 * Copyright (C) 2009 Janusz Krzysztofik 5 * Copyright (c) 2006 Matt Callow 6 * Copyright (c) 2004 Amstrad Plc 7 * Copyright (C) 2001 RidgeRun, Inc. 8 * 9 * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c 10 * in the MontaVista 2.4 kernel (and the Amstrad changes therein) 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License version 2 as published by 14 * the Free Software Foundation. 15 */ 16 #include <linux/gpio/consumer.h> 17 #include <linux/gpio/machine.h> 18 #include <linux/gpio/driver.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/io.h> 23 #include <linux/platform_data/ams-delta-fiq.h> 24 #include <linux/platform_device.h> 25 26 #include <asm/fiq.h> 27 28 #include "ams-delta-fiq.h" 29 #include "board-ams-delta.h" 30 31 static struct fiq_handler fh = { 32 .name = "ams-delta-fiq" 33 }; 34 35 /* 36 * This buffer is shared between FIQ and IRQ contexts. 37 * The FIQ and IRQ isrs can both read and write it. 38 * It is structured as a header section several 32bit slots, 39 * followed by the circular buffer where the FIQ isr stores 40 * keystrokes received from the qwerty keyboard. See 41 * <linux/platform_data/ams-delta-fiq.h> for details of offsets. 42 */ 43 static unsigned int fiq_buffer[1024]; 44 45 static struct irq_chip *irq_chip; 46 static struct irq_data *irq_data[16]; 47 static unsigned int irq_counter[16]; 48 49 static const char *pin_name[16] __initconst = { 50 [AMS_DELTA_GPIO_PIN_KEYBRD_DATA] = "keybrd_data", 51 [AMS_DELTA_GPIO_PIN_KEYBRD_CLK] = "keybrd_clk", 52 }; 53 54 static irqreturn_t deferred_fiq(int irq, void *dev_id) 55 { 56 struct irq_data *d; 57 int gpio, irq_num, fiq_count; 58 59 /* 60 * For each handled GPIO interrupt, keep calling its interrupt handler 61 * until the IRQ counter catches the FIQ incremented interrupt counter. 62 */ 63 for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK; 64 gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) { 65 d = irq_data[gpio]; 66 irq_num = d->irq; 67 fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio]; 68 69 if (irq_counter[gpio] < fiq_count && 70 gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) { 71 /* 72 * handle_simple_irq() that OMAP GPIO edge 73 * interrupts default to since commit 80ac93c27441 74 * requires interrupt already acked and unmasked. 75 */ 76 if (irq_chip->irq_ack) 77 irq_chip->irq_ack(d); 78 if (irq_chip->irq_unmask) 79 irq_chip->irq_unmask(d); 80 } 81 for (; irq_counter[gpio] < fiq_count; irq_counter[gpio]++) 82 generic_handle_irq(irq_num); 83 } 84 return IRQ_HANDLED; 85 } 86 87 void __init ams_delta_init_fiq(struct gpio_chip *chip, 88 struct platform_device *serio) 89 { 90 struct gpio_desc *gpiod, *data = NULL, *clk = NULL; 91 void *fiqhandler_start; 92 unsigned int fiqhandler_length; 93 struct pt_regs FIQ_regs; 94 unsigned long val, offset; 95 int i, retval; 96 97 /* Store irq_chip location for IRQ handler use */ 98 irq_chip = chip->irq.chip; 99 if (!irq_chip) { 100 pr_err("%s: GPIO chip %s is missing IRQ function\n", __func__, 101 chip->label); 102 return; 103 } 104 105 for (i = 0; i < ARRAY_SIZE(irq_data); i++) { 106 gpiod = gpiochip_request_own_desc(chip, i, pin_name[i], 107 GPIO_ACTIVE_HIGH, GPIOD_IN); 108 if (IS_ERR(gpiod)) { 109 pr_err("%s: failed to get GPIO pin %d (%ld)\n", 110 __func__, i, PTR_ERR(gpiod)); 111 return; 112 } 113 /* Store irq_data location for IRQ handler use */ 114 irq_data[i] = irq_get_irq_data(gpiod_to_irq(gpiod)); 115 116 /* 117 * FIQ handler takes full control over serio data and clk GPIO 118 * pins. Initiaize them and keep requested so nobody can 119 * interfere. Fail if any of those two couldn't be requested. 120 */ 121 switch (i) { 122 case AMS_DELTA_GPIO_PIN_KEYBRD_DATA: 123 data = gpiod; 124 gpiod_direction_input(data); 125 break; 126 case AMS_DELTA_GPIO_PIN_KEYBRD_CLK: 127 clk = gpiod; 128 gpiod_direction_input(clk); 129 break; 130 default: 131 gpiochip_free_own_desc(gpiod); 132 break; 133 } 134 } 135 if (!data || !clk) 136 goto out_gpio; 137 138 fiqhandler_start = &qwerty_fiqin_start; 139 fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start; 140 pr_info("Installing fiq handler from %p, length 0x%x\n", 141 fiqhandler_start, fiqhandler_length); 142 143 retval = claim_fiq(&fh); 144 if (retval) { 145 pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n", 146 retval); 147 goto out_gpio; 148 } 149 150 retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq, 151 IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL); 152 if (retval < 0) { 153 pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval); 154 release_fiq(&fh); 155 goto out_gpio; 156 } 157 /* 158 * Since no set_type() method is provided by OMAP irq chip, 159 * switch to edge triggered interrupt type manually. 160 */ 161 offset = IRQ_ILR0_REG_OFFSET + 162 ((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4; 163 val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1); 164 omap_writel(val, DEFERRED_FIQ_IH_BASE + offset); 165 166 set_fiq_handler(fiqhandler_start, fiqhandler_length); 167 168 /* 169 * Initialise the buffer which is shared 170 * between FIQ mode and IRQ mode 171 */ 172 fiq_buffer[FIQ_GPIO_INT_MASK] = 0; 173 fiq_buffer[FIQ_MASK] = 0; 174 fiq_buffer[FIQ_STATE] = 0; 175 fiq_buffer[FIQ_KEY] = 0; 176 fiq_buffer[FIQ_KEYS_CNT] = 0; 177 fiq_buffer[FIQ_KEYS_HICNT] = 0; 178 fiq_buffer[FIQ_TAIL_OFFSET] = 0; 179 fiq_buffer[FIQ_HEAD_OFFSET] = 0; 180 fiq_buffer[FIQ_BUF_LEN] = 256; 181 fiq_buffer[FIQ_MISSED_KEYS] = 0; 182 fiq_buffer[FIQ_BUFFER_START] = 183 (unsigned int) &fiq_buffer[FIQ_CIRC_BUFF]; 184 185 for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++) 186 fiq_buffer[i] = 0; 187 188 /* 189 * FIQ mode r9 always points to the fiq_buffer, because the FIQ isr 190 * will run in an unpredictable context. The fiq_buffer is the FIQ isr's 191 * only means of communication with the IRQ level and other kernel 192 * context code. 193 */ 194 FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer; 195 set_fiq_regs(&FIQ_regs); 196 197 pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer); 198 199 /* 200 * Redirect GPIO interrupts to FIQ 201 */ 202 offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4; 203 val = omap_readl(OMAP_IH1_BASE + offset) | 1; 204 omap_writel(val, OMAP_IH1_BASE + offset); 205 206 /* Initialize serio device IRQ resource and platform_data */ 207 serio->resource[0].start = gpiod_to_irq(clk); 208 serio->resource[0].end = serio->resource[0].start; 209 serio->dev.platform_data = fiq_buffer; 210 211 /* 212 * Since FIQ handler performs handling of GPIO registers for 213 * "keybrd_clk" IRQ pin, ams_delta_serio driver used to set 214 * handle_simple_irq() as active IRQ handler for that pin to avoid 215 * bad interaction with gpio-omap driver. This is no longer needed 216 * as handle_simple_irq() is now the default handler for OMAP GPIO 217 * edge interrupts. 218 * This comment replaces the obsolete code which has been removed 219 * from the ams_delta_serio driver and stands here only as a reminder 220 * of that dependency on gpio-omap driver behavior. 221 */ 222 223 return; 224 225 out_gpio: 226 if (data) 227 gpiochip_free_own_desc(data); 228 if (clk) 229 gpiochip_free_own_desc(clk); 230 } 231