1 /* 2 * Amstrad E3 FIQ handling 3 * 4 * Copyright (C) 2009 Janusz Krzysztofik 5 * Copyright (c) 2006 Matt Callow 6 * Copyright (c) 2004 Amstrad Plc 7 * Copyright (C) 2001 RidgeRun, Inc. 8 * 9 * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c 10 * in the MontaVista 2.4 kernel (and the Amstrad changes therein) 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License version 2 as published by 14 * the Free Software Foundation. 15 */ 16 #include <linux/gpio/consumer.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/module.h> 21 #include <linux/io.h> 22 #include <linux/platform_data/ams-delta-fiq.h> 23 #include <linux/platform_device.h> 24 25 #include <asm/fiq.h> 26 27 #include "ams-delta-fiq.h" 28 #include "board-ams-delta.h" 29 30 static struct fiq_handler fh = { 31 .name = "ams-delta-fiq" 32 }; 33 34 /* 35 * This buffer is shared between FIQ and IRQ contexts. 36 * The FIQ and IRQ isrs can both read and write it. 37 * It is structured as a header section several 32bit slots, 38 * followed by the circular buffer where the FIQ isr stores 39 * keystrokes received from the qwerty keyboard. See 40 * <linux/platform_data/ams-delta-fiq.h> for details of offsets. 41 */ 42 static unsigned int fiq_buffer[1024]; 43 44 static struct irq_chip *irq_chip; 45 static struct irq_data *irq_data[16]; 46 static unsigned int irq_counter[16]; 47 48 static const char *pin_name[16] __initconst = { 49 [AMS_DELTA_GPIO_PIN_KEYBRD_DATA] = "keybrd_data", 50 [AMS_DELTA_GPIO_PIN_KEYBRD_CLK] = "keybrd_clk", 51 }; 52 53 static irqreturn_t deferred_fiq(int irq, void *dev_id) 54 { 55 struct irq_data *d; 56 int gpio, irq_num, fiq_count; 57 58 /* 59 * For each handled GPIO interrupt, keep calling its interrupt handler 60 * until the IRQ counter catches the FIQ incremented interrupt counter. 61 */ 62 for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK; 63 gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) { 64 d = irq_data[gpio]; 65 irq_num = d->irq; 66 fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio]; 67 68 if (irq_counter[gpio] < fiq_count && 69 gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) { 70 /* 71 * handle_simple_irq() that OMAP GPIO edge 72 * interrupts default to since commit 80ac93c27441 73 * requires interrupt already acked and unmasked. 74 */ 75 if (irq_chip->irq_ack) 76 irq_chip->irq_ack(d); 77 if (irq_chip->irq_unmask) 78 irq_chip->irq_unmask(d); 79 } 80 for (; irq_counter[gpio] < fiq_count; irq_counter[gpio]++) 81 generic_handle_irq(irq_num); 82 } 83 return IRQ_HANDLED; 84 } 85 86 void __init ams_delta_init_fiq(struct gpio_chip *chip, 87 struct platform_device *serio) 88 { 89 struct gpio_desc *gpiod, *data = NULL, *clk = NULL; 90 void *fiqhandler_start; 91 unsigned int fiqhandler_length; 92 struct pt_regs FIQ_regs; 93 unsigned long val, offset; 94 int i, retval; 95 96 /* Store irq_chip location for IRQ handler use */ 97 irq_chip = chip->irq.chip; 98 if (!irq_chip) { 99 pr_err("%s: GPIO chip %s is missing IRQ function\n", __func__, 100 chip->label); 101 return; 102 } 103 104 for (i = 0; i < ARRAY_SIZE(irq_data); i++) { 105 gpiod = gpiochip_request_own_desc(chip, i, pin_name[i]); 106 if (IS_ERR(gpiod)) { 107 pr_err("%s: failed to get GPIO pin %d (%ld)\n", 108 __func__, i, PTR_ERR(gpiod)); 109 return; 110 } 111 /* Store irq_data location for IRQ handler use */ 112 irq_data[i] = irq_get_irq_data(gpiod_to_irq(gpiod)); 113 114 /* 115 * FIQ handler takes full control over serio data and clk GPIO 116 * pins. Initiaize them and keep requested so nobody can 117 * interfere. Fail if any of those two couldn't be requested. 118 */ 119 switch (i) { 120 case AMS_DELTA_GPIO_PIN_KEYBRD_DATA: 121 data = gpiod; 122 gpiod_direction_input(data); 123 break; 124 case AMS_DELTA_GPIO_PIN_KEYBRD_CLK: 125 clk = gpiod; 126 gpiod_direction_input(clk); 127 break; 128 default: 129 gpiochip_free_own_desc(gpiod); 130 break; 131 } 132 } 133 if (!data || !clk) 134 goto out_gpio; 135 136 fiqhandler_start = &qwerty_fiqin_start; 137 fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start; 138 pr_info("Installing fiq handler from %p, length 0x%x\n", 139 fiqhandler_start, fiqhandler_length); 140 141 retval = claim_fiq(&fh); 142 if (retval) { 143 pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n", 144 retval); 145 goto out_gpio; 146 } 147 148 retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq, 149 IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL); 150 if (retval < 0) { 151 pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval); 152 release_fiq(&fh); 153 goto out_gpio; 154 } 155 /* 156 * Since no set_type() method is provided by OMAP irq chip, 157 * switch to edge triggered interrupt type manually. 158 */ 159 offset = IRQ_ILR0_REG_OFFSET + 160 ((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4; 161 val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1); 162 omap_writel(val, DEFERRED_FIQ_IH_BASE + offset); 163 164 set_fiq_handler(fiqhandler_start, fiqhandler_length); 165 166 /* 167 * Initialise the buffer which is shared 168 * between FIQ mode and IRQ mode 169 */ 170 fiq_buffer[FIQ_GPIO_INT_MASK] = 0; 171 fiq_buffer[FIQ_MASK] = 0; 172 fiq_buffer[FIQ_STATE] = 0; 173 fiq_buffer[FIQ_KEY] = 0; 174 fiq_buffer[FIQ_KEYS_CNT] = 0; 175 fiq_buffer[FIQ_KEYS_HICNT] = 0; 176 fiq_buffer[FIQ_TAIL_OFFSET] = 0; 177 fiq_buffer[FIQ_HEAD_OFFSET] = 0; 178 fiq_buffer[FIQ_BUF_LEN] = 256; 179 fiq_buffer[FIQ_MISSED_KEYS] = 0; 180 fiq_buffer[FIQ_BUFFER_START] = 181 (unsigned int) &fiq_buffer[FIQ_CIRC_BUFF]; 182 183 for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++) 184 fiq_buffer[i] = 0; 185 186 /* 187 * FIQ mode r9 always points to the fiq_buffer, because the FIQ isr 188 * will run in an unpredictable context. The fiq_buffer is the FIQ isr's 189 * only means of communication with the IRQ level and other kernel 190 * context code. 191 */ 192 FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer; 193 set_fiq_regs(&FIQ_regs); 194 195 pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer); 196 197 /* 198 * Redirect GPIO interrupts to FIQ 199 */ 200 offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4; 201 val = omap_readl(OMAP_IH1_BASE + offset) | 1; 202 omap_writel(val, OMAP_IH1_BASE + offset); 203 204 /* Initialize serio device IRQ resource and platform_data */ 205 serio->resource[0].start = gpiod_to_irq(clk); 206 serio->resource[0].end = serio->resource[0].start; 207 serio->dev.platform_data = fiq_buffer; 208 209 /* 210 * Since FIQ handler performs handling of GPIO registers for 211 * "keybrd_clk" IRQ pin, ams_delta_serio driver used to set 212 * handle_simple_irq() as active IRQ handler for that pin to avoid 213 * bad interaction with gpio-omap driver. This is no longer needed 214 * as handle_simple_irq() is now the default handler for OMAP GPIO 215 * edge interrupts. 216 * This comment replaces the obsolete code which has been removed 217 * from the ams_delta_serio driver and stands here only as a reminder 218 * of that dependency on gpio-omap driver behavior. 219 */ 220 221 return; 222 223 out_gpio: 224 if (data) 225 gpiochip_free_own_desc(data); 226 if (clk) 227 gpiochip_free_own_desc(clk); 228 } 229