1312b62b6SDaniel Palmer // SPDX-License-Identifier: GPL-2.0 2312b62b6SDaniel Palmer /* 3312b62b6SDaniel Palmer * Device Tree support for MStar/Sigmastar Armv7 SoCs 4312b62b6SDaniel Palmer * 5312b62b6SDaniel Palmer * Copyright (c) 2020 thingy.jp 6312b62b6SDaniel Palmer * Author: Daniel Palmer <daniel@thingy.jp> 7312b62b6SDaniel Palmer */ 8312b62b6SDaniel Palmer 9312b62b6SDaniel Palmer #include <linux/init.h> 10312b62b6SDaniel Palmer #include <asm/mach/arch.h> 11312b62b6SDaniel Palmer #include <asm/mach/map.h> 12312b62b6SDaniel Palmer #include <linux/of.h> 13312b62b6SDaniel Palmer #include <linux/of_address.h> 14312b62b6SDaniel Palmer #include <linux/io.h> 15312b62b6SDaniel Palmer 16312b62b6SDaniel Palmer /* 17312b62b6SDaniel Palmer * In the u-boot code the area these registers are in is 18312b62b6SDaniel Palmer * called "L3 bridge" and there are register descriptions 19312b62b6SDaniel Palmer * for something in the same area called "AXI". 20312b62b6SDaniel Palmer * 21312b62b6SDaniel Palmer * It's not exactly known what this is but the vendor code 22312b62b6SDaniel Palmer * for both u-boot and linux share calls to "flush the miu pipe". 23312b62b6SDaniel Palmer * This seems to be to force pending CPU writes to memory so that 24312b62b6SDaniel Palmer * the state is right before DMA capable devices try to read 25312b62b6SDaniel Palmer * descriptors and data the CPU has prepared. Without doing this 26312b62b6SDaniel Palmer * ethernet doesn't work reliably for example. 27312b62b6SDaniel Palmer */ 28312b62b6SDaniel Palmer 29312b62b6SDaniel Palmer #define MSTARV7_L3BRIDGE_FLUSH 0x14 30312b62b6SDaniel Palmer #define MSTARV7_L3BRIDGE_STATUS 0x40 31312b62b6SDaniel Palmer #define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0) 32312b62b6SDaniel Palmer #define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12) 33312b62b6SDaniel Palmer 34312b62b6SDaniel Palmer static void __iomem *l3bridge; 35312b62b6SDaniel Palmer 36312b62b6SDaniel Palmer static const char * const mstarv7_board_dt_compat[] __initconst = { 37312b62b6SDaniel Palmer "mstar,infinity", 38312b62b6SDaniel Palmer "mstar,infinity3", 39312b62b6SDaniel Palmer "mstar,mercury5", 40312b62b6SDaniel Palmer NULL, 41312b62b6SDaniel Palmer }; 42312b62b6SDaniel Palmer 43312b62b6SDaniel Palmer /* 44312b62b6SDaniel Palmer * This may need locking to deal with situations where an interrupt 45312b62b6SDaniel Palmer * happens while we are in here and mb() gets called by the interrupt handler. 46312b62b6SDaniel Palmer * 47312b62b6SDaniel Palmer * The vendor code did have a spin lock but it doesn't seem to be needed and 48312b62b6SDaniel Palmer * removing it hasn't caused any side effects so far. 49312b62b6SDaniel Palmer * 50312b62b6SDaniel Palmer * [writel|readl]_relaxed have to be used here because otherwise 51312b62b6SDaniel Palmer * we'd end up right back in here. 52312b62b6SDaniel Palmer */ 53312b62b6SDaniel Palmer static void mstarv7_mb(void) 54312b62b6SDaniel Palmer { 55312b62b6SDaniel Palmer /* toggle the flush miu pipe fire bit */ 56312b62b6SDaniel Palmer writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH); 57312b62b6SDaniel Palmer writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge 58312b62b6SDaniel Palmer + MSTARV7_L3BRIDGE_FLUSH); 59312b62b6SDaniel Palmer while (!(readl_relaxed(l3bridge + MSTARV7_L3BRIDGE_STATUS) 60312b62b6SDaniel Palmer & MSTARV7_L3BRIDGE_STATUS_DONE)) { 61312b62b6SDaniel Palmer /* wait for flush to complete */ 62312b62b6SDaniel Palmer } 63312b62b6SDaniel Palmer } 64312b62b6SDaniel Palmer 65312b62b6SDaniel Palmer static void __init mstarv7_init(void) 66312b62b6SDaniel Palmer { 67312b62b6SDaniel Palmer struct device_node *np; 68312b62b6SDaniel Palmer 69312b62b6SDaniel Palmer np = of_find_compatible_node(NULL, NULL, "mstar,l3bridge"); 70312b62b6SDaniel Palmer l3bridge = of_iomap(np, 0); 71312b62b6SDaniel Palmer if (l3bridge) 72312b62b6SDaniel Palmer soc_mb = mstarv7_mb; 73312b62b6SDaniel Palmer else 74312b62b6SDaniel Palmer pr_warn("Failed to install memory barrier, DMA will be broken!\n"); 75312b62b6SDaniel Palmer } 76312b62b6SDaniel Palmer 77312b62b6SDaniel Palmer DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)") 78312b62b6SDaniel Palmer .dt_compat = mstarv7_board_dt_compat, 79312b62b6SDaniel Palmer .init_machine = mstarv7_init, 80312b62b6SDaniel Palmer MACHINE_END 81