1 /* 2 * Copyright 2010-2011 Calxeda, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #include <linux/clk.h> 17 #include <linux/clkdev.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 #include <linux/of_address.h> 26 #include <linux/smp.h> 27 #include <linux/amba/bus.h> 28 #include <linux/clk-provider.h> 29 30 #include <asm/arch_timer.h> 31 #include <asm/cacheflush.h> 32 #include <asm/cputype.h> 33 #include <asm/smp_plat.h> 34 #include <asm/smp_twd.h> 35 #include <asm/hardware/arm_timer.h> 36 #include <asm/hardware/timer-sp.h> 37 #include <asm/hardware/gic.h> 38 #include <asm/hardware/cache-l2x0.h> 39 #include <asm/mach/arch.h> 40 #include <asm/mach/map.h> 41 #include <asm/mach/time.h> 42 43 #include "core.h" 44 #include "sysregs.h" 45 46 void __iomem *sregs_base; 47 void __iomem *scu_base_addr; 48 49 static void __init highbank_scu_map_io(void) 50 { 51 unsigned long base; 52 53 /* Get SCU base */ 54 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); 55 56 scu_base_addr = ioremap(base, SZ_4K); 57 } 58 59 #define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu))) 60 #define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu)) 61 62 void highbank_set_cpu_jump(int cpu, void *jump_addr) 63 { 64 cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0); 65 writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu)); 66 __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); 67 outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), 68 HB_JUMP_TABLE_PHYS(cpu) + 15); 69 } 70 71 const static struct of_device_id irq_match[] = { 72 { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, }, 73 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, 74 {} 75 }; 76 77 #ifdef CONFIG_CACHE_L2X0 78 static void highbank_l2x0_disable(void) 79 { 80 /* Disable PL310 L2 Cache controller */ 81 highbank_smc1(0x102, 0x0); 82 } 83 #endif 84 85 static void __init highbank_init_irq(void) 86 { 87 of_irq_init(irq_match); 88 89 if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9")) 90 highbank_scu_map_io(); 91 92 #ifdef CONFIG_CACHE_L2X0 93 /* Enable PL310 L2 Cache controller */ 94 highbank_smc1(0x102, 0x1); 95 l2x0_of_init(0, ~0UL); 96 outer_cache.disable = highbank_l2x0_disable; 97 #endif 98 } 99 100 static struct clk_lookup lookup = { 101 .dev_id = "sp804", 102 .con_id = NULL, 103 }; 104 105 static void __init highbank_timer_init(void) 106 { 107 int irq; 108 struct device_node *np; 109 void __iomem *timer_base; 110 111 /* Map system registers */ 112 np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); 113 sregs_base = of_iomap(np, 0); 114 WARN_ON(!sregs_base); 115 116 np = of_find_compatible_node(NULL, NULL, "arm,sp804"); 117 timer_base = of_iomap(np, 0); 118 WARN_ON(!timer_base); 119 irq = irq_of_parse_and_map(np, 0); 120 121 of_clk_init(NULL); 122 lookup.clk = of_clk_get(np, 0); 123 clkdev_add(&lookup); 124 125 sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); 126 sp804_clockevents_init(timer_base, irq, "timer0"); 127 128 twd_local_timer_of_register(); 129 130 arch_timer_of_register(); 131 arch_timer_sched_clock_init(); 132 } 133 134 static struct sys_timer highbank_timer = { 135 .init = highbank_timer_init, 136 }; 137 138 static void highbank_power_off(void) 139 { 140 highbank_set_pwr_shutdown(); 141 142 while (1) 143 cpu_do_idle(); 144 } 145 146 static int highbank_platform_notifier(struct notifier_block *nb, 147 unsigned long event, void *__dev) 148 { 149 struct resource *res; 150 int reg = -1; 151 struct device *dev = __dev; 152 153 if (event != BUS_NOTIFY_ADD_DEVICE) 154 return NOTIFY_DONE; 155 156 if (of_device_is_compatible(dev->of_node, "calxeda,hb-ahci")) 157 reg = 0xc; 158 else if (of_device_is_compatible(dev->of_node, "calxeda,hb-sdhci")) 159 reg = 0x18; 160 else if (of_device_is_compatible(dev->of_node, "arm,pl330")) 161 reg = 0x20; 162 else if (of_device_is_compatible(dev->of_node, "calxeda,hb-xgmac")) { 163 res = platform_get_resource(to_platform_device(dev), 164 IORESOURCE_MEM, 0); 165 if (res) { 166 if (res->start == 0xfff50000) 167 reg = 0; 168 else if (res->start == 0xfff51000) 169 reg = 4; 170 } 171 } 172 173 if (reg < 0) 174 return NOTIFY_DONE; 175 176 if (of_property_read_bool(dev->of_node, "dma-coherent")) { 177 writel(0xff31, sregs_base + reg); 178 set_dma_ops(dev, &arm_coherent_dma_ops); 179 } else 180 writel(0, sregs_base + reg); 181 182 return NOTIFY_OK; 183 } 184 185 static struct notifier_block highbank_amba_nb = { 186 .notifier_call = highbank_platform_notifier, 187 }; 188 189 static struct notifier_block highbank_platform_nb = { 190 .notifier_call = highbank_platform_notifier, 191 }; 192 193 static void __init highbank_init(void) 194 { 195 pm_power_off = highbank_power_off; 196 highbank_pm_init(); 197 198 bus_register_notifier(&platform_bus_type, &highbank_platform_nb); 199 bus_register_notifier(&amba_bustype, &highbank_amba_nb); 200 201 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 202 } 203 204 static const char *highbank_match[] __initconst = { 205 "calxeda,highbank", 206 "calxeda,ecx-2000", 207 NULL, 208 }; 209 210 DT_MACHINE_START(HIGHBANK, "Highbank") 211 .smp = smp_ops(highbank_smp_ops), 212 .map_io = debug_ll_io_init, 213 .init_irq = highbank_init_irq, 214 .timer = &highbank_timer, 215 .handle_irq = gic_handle_irq, 216 .init_machine = highbank_init, 217 .dt_compat = highbank_match, 218 .restart = highbank_restart, 219 MACHINE_END 220