1 /* 2 * Copyright 2010-2011 Calxeda, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #include <linux/clk.h> 17 #include <linux/clkdev.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 #include <linux/irqchip.h> 22 #include <linux/irqdomain.h> 23 #include <linux/of.h> 24 #include <linux/of_irq.h> 25 #include <linux/of_platform.h> 26 #include <linux/of_address.h> 27 #include <linux/smp.h> 28 #include <linux/amba/bus.h> 29 #include <linux/clk-provider.h> 30 31 #include <asm/arch_timer.h> 32 #include <asm/cacheflush.h> 33 #include <asm/cputype.h> 34 #include <asm/smp_plat.h> 35 #include <asm/smp_twd.h> 36 #include <asm/hardware/arm_timer.h> 37 #include <asm/hardware/timer-sp.h> 38 #include <asm/hardware/cache-l2x0.h> 39 #include <asm/mach/arch.h> 40 #include <asm/mach/map.h> 41 #include <asm/mach/time.h> 42 43 #include "core.h" 44 #include "sysregs.h" 45 46 void __iomem *sregs_base; 47 void __iomem *scu_base_addr; 48 49 static void __init highbank_scu_map_io(void) 50 { 51 unsigned long base; 52 53 /* Get SCU base */ 54 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); 55 56 scu_base_addr = ioremap(base, SZ_4K); 57 } 58 59 #define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu))) 60 #define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu)) 61 62 void highbank_set_cpu_jump(int cpu, void *jump_addr) 63 { 64 cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0); 65 writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu)); 66 __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); 67 outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), 68 HB_JUMP_TABLE_PHYS(cpu) + 15); 69 } 70 71 #ifdef CONFIG_CACHE_L2X0 72 static void highbank_l2x0_disable(void) 73 { 74 /* Disable PL310 L2 Cache controller */ 75 highbank_smc1(0x102, 0x0); 76 } 77 #endif 78 79 static void __init highbank_init_irq(void) 80 { 81 irqchip_init(); 82 83 if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9")) 84 highbank_scu_map_io(); 85 86 #ifdef CONFIG_CACHE_L2X0 87 /* Enable PL310 L2 Cache controller */ 88 highbank_smc1(0x102, 0x1); 89 l2x0_of_init(0, ~0UL); 90 outer_cache.disable = highbank_l2x0_disable; 91 #endif 92 } 93 94 static struct clk_lookup lookup = { 95 .dev_id = "sp804", 96 .con_id = NULL, 97 }; 98 99 static void __init highbank_timer_init(void) 100 { 101 int irq; 102 struct device_node *np; 103 void __iomem *timer_base; 104 105 /* Map system registers */ 106 np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); 107 sregs_base = of_iomap(np, 0); 108 WARN_ON(!sregs_base); 109 110 np = of_find_compatible_node(NULL, NULL, "arm,sp804"); 111 timer_base = of_iomap(np, 0); 112 WARN_ON(!timer_base); 113 irq = irq_of_parse_and_map(np, 0); 114 115 of_clk_init(NULL); 116 lookup.clk = of_clk_get(np, 0); 117 clkdev_add(&lookup); 118 119 sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); 120 sp804_clockevents_init(timer_base, irq, "timer0"); 121 122 twd_local_timer_of_register(); 123 124 arch_timer_of_register(); 125 arch_timer_sched_clock_init(); 126 } 127 128 static void highbank_power_off(void) 129 { 130 highbank_set_pwr_shutdown(); 131 132 while (1) 133 cpu_do_idle(); 134 } 135 136 static int highbank_platform_notifier(struct notifier_block *nb, 137 unsigned long event, void *__dev) 138 { 139 struct resource *res; 140 int reg = -1; 141 struct device *dev = __dev; 142 143 if (event != BUS_NOTIFY_ADD_DEVICE) 144 return NOTIFY_DONE; 145 146 if (of_device_is_compatible(dev->of_node, "calxeda,hb-ahci")) 147 reg = 0xc; 148 else if (of_device_is_compatible(dev->of_node, "calxeda,hb-sdhci")) 149 reg = 0x18; 150 else if (of_device_is_compatible(dev->of_node, "arm,pl330")) 151 reg = 0x20; 152 else if (of_device_is_compatible(dev->of_node, "calxeda,hb-xgmac")) { 153 res = platform_get_resource(to_platform_device(dev), 154 IORESOURCE_MEM, 0); 155 if (res) { 156 if (res->start == 0xfff50000) 157 reg = 0; 158 else if (res->start == 0xfff51000) 159 reg = 4; 160 } 161 } 162 163 if (reg < 0) 164 return NOTIFY_DONE; 165 166 if (of_property_read_bool(dev->of_node, "dma-coherent")) { 167 writel(0xff31, sregs_base + reg); 168 set_dma_ops(dev, &arm_coherent_dma_ops); 169 } else 170 writel(0, sregs_base + reg); 171 172 return NOTIFY_OK; 173 } 174 175 static struct notifier_block highbank_amba_nb = { 176 .notifier_call = highbank_platform_notifier, 177 }; 178 179 static struct notifier_block highbank_platform_nb = { 180 .notifier_call = highbank_platform_notifier, 181 }; 182 183 static void __init highbank_init(void) 184 { 185 pm_power_off = highbank_power_off; 186 highbank_pm_init(); 187 188 bus_register_notifier(&platform_bus_type, &highbank_platform_nb); 189 bus_register_notifier(&amba_bustype, &highbank_amba_nb); 190 191 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 192 } 193 194 static const char *highbank_match[] __initconst = { 195 "calxeda,highbank", 196 "calxeda,ecx-2000", 197 NULL, 198 }; 199 200 DT_MACHINE_START(HIGHBANK, "Highbank") 201 .smp = smp_ops(highbank_smp_ops), 202 .map_io = debug_ll_io_init, 203 .init_irq = highbank_init_irq, 204 .init_time = highbank_timer_init, 205 .init_machine = highbank_init, 206 .dt_compat = highbank_match, 207 .restart = highbank_restart, 208 MACHINE_END 209