1 /* 2 * Copyright 2010-2011 Calxeda, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #include <linux/clk.h> 17 #include <linux/clkdev.h> 18 #include <linux/clocksource.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/io.h> 21 #include <linux/irqchip.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 #include <linux/of_address.h> 26 #include <linux/amba/bus.h> 27 28 #include <asm/cacheflush.h> 29 #include <asm/cputype.h> 30 #include <asm/smp_plat.h> 31 #include <asm/hardware/cache-l2x0.h> 32 #include <asm/mach/arch.h> 33 #include <asm/mach/map.h> 34 35 #include "core.h" 36 #include "sysregs.h" 37 38 void __iomem *sregs_base; 39 void __iomem *scu_base_addr; 40 41 static void __init highbank_scu_map_io(void) 42 { 43 unsigned long base; 44 45 /* Get SCU base */ 46 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); 47 48 scu_base_addr = ioremap(base, SZ_4K); 49 } 50 51 #define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu))) 52 #define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu)) 53 54 void highbank_set_cpu_jump(int cpu, void *jump_addr) 55 { 56 cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0); 57 writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu)); 58 __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); 59 outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), 60 HB_JUMP_TABLE_PHYS(cpu) + 15); 61 } 62 63 static void highbank_l2x0_disable(void) 64 { 65 /* Disable PL310 L2 Cache controller */ 66 highbank_smc1(0x102, 0x0); 67 } 68 69 static void __init highbank_init_irq(void) 70 { 71 irqchip_init(); 72 73 if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9")) 74 highbank_scu_map_io(); 75 76 /* Enable PL310 L2 Cache controller */ 77 if (IS_ENABLED(CONFIG_CACHE_L2X0) && 78 of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) { 79 highbank_smc1(0x102, 0x1); 80 l2x0_of_init(0, ~0UL); 81 outer_cache.disable = highbank_l2x0_disable; 82 } 83 } 84 85 static void highbank_power_off(void) 86 { 87 highbank_set_pwr_shutdown(); 88 89 while (1) 90 cpu_do_idle(); 91 } 92 93 static int highbank_platform_notifier(struct notifier_block *nb, 94 unsigned long event, void *__dev) 95 { 96 struct resource *res; 97 int reg = -1; 98 u32 val; 99 struct device *dev = __dev; 100 101 if (event != BUS_NOTIFY_ADD_DEVICE) 102 return NOTIFY_DONE; 103 104 if (of_device_is_compatible(dev->of_node, "calxeda,hb-ahci")) 105 reg = 0xc; 106 else if (of_device_is_compatible(dev->of_node, "calxeda,hb-sdhci")) 107 reg = 0x18; 108 else if (of_device_is_compatible(dev->of_node, "arm,pl330")) 109 reg = 0x20; 110 else if (of_device_is_compatible(dev->of_node, "calxeda,hb-xgmac")) { 111 res = platform_get_resource(to_platform_device(dev), 112 IORESOURCE_MEM, 0); 113 if (res) { 114 if (res->start == 0xfff50000) 115 reg = 0; 116 else if (res->start == 0xfff51000) 117 reg = 4; 118 } 119 } 120 121 if (reg < 0) 122 return NOTIFY_DONE; 123 124 if (of_property_read_bool(dev->of_node, "dma-coherent")) { 125 val = readl(sregs_base + reg); 126 writel(val | 0xff01, sregs_base + reg); 127 set_dma_ops(dev, &arm_coherent_dma_ops); 128 } 129 130 return NOTIFY_OK; 131 } 132 133 static struct notifier_block highbank_amba_nb = { 134 .notifier_call = highbank_platform_notifier, 135 }; 136 137 static struct notifier_block highbank_platform_nb = { 138 .notifier_call = highbank_platform_notifier, 139 }; 140 141 static void __init highbank_init(void) 142 { 143 struct device_node *np; 144 145 /* Map system registers */ 146 np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); 147 sregs_base = of_iomap(np, 0); 148 WARN_ON(!sregs_base); 149 150 pm_power_off = highbank_power_off; 151 highbank_pm_init(); 152 153 bus_register_notifier(&platform_bus_type, &highbank_platform_nb); 154 bus_register_notifier(&amba_bustype, &highbank_amba_nb); 155 156 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 157 } 158 159 static const char *highbank_match[] __initconst = { 160 "calxeda,highbank", 161 "calxeda,ecx-2000", 162 NULL, 163 }; 164 165 DT_MACHINE_START(HIGHBANK, "Highbank") 166 #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) 167 .dma_zone_size = (4ULL * SZ_1G), 168 #endif 169 .smp = smp_ops(highbank_smp_ops), 170 .init_irq = highbank_init_irq, 171 .init_machine = highbank_init, 172 .dt_compat = highbank_match, 173 .restart = highbank_restart, 174 MACHINE_END 175