1220e6cf7SRob Herring /* 2220e6cf7SRob Herring * Copyright 2010-2011 Calxeda, Inc. 3220e6cf7SRob Herring * 4220e6cf7SRob Herring * This program is free software; you can redistribute it and/or modify it 5220e6cf7SRob Herring * under the terms and conditions of the GNU General Public License, 6220e6cf7SRob Herring * version 2, as published by the Free Software Foundation. 7220e6cf7SRob Herring * 8220e6cf7SRob Herring * This program is distributed in the hope it will be useful, but WITHOUT 9220e6cf7SRob Herring * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10220e6cf7SRob Herring * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11220e6cf7SRob Herring * more details. 12220e6cf7SRob Herring * 13220e6cf7SRob Herring * You should have received a copy of the GNU General Public License along with 14220e6cf7SRob Herring * this program. If not, see <http://www.gnu.org/licenses/>. 15220e6cf7SRob Herring */ 16220e6cf7SRob Herring #include <linux/clk.h> 17220e6cf7SRob Herring #include <linux/clkdev.h> 181dc737c4SRob Herring #include <linux/dma-mapping.h> 19220e6cf7SRob Herring #include <linux/io.h> 20220e6cf7SRob Herring #include <linux/irq.h> 21220e6cf7SRob Herring #include <linux/irqdomain.h> 22220e6cf7SRob Herring #include <linux/of.h> 23220e6cf7SRob Herring #include <linux/of_irq.h> 24220e6cf7SRob Herring #include <linux/of_platform.h> 25220e6cf7SRob Herring #include <linux/of_address.h> 26bf14fc54SWill Deacon #include <linux/smp.h> 271dc737c4SRob Herring #include <linux/amba/bus.h> 28220e6cf7SRob Herring 29220e6cf7SRob Herring #include <asm/cacheflush.h> 30eb50439bSWill Deacon #include <asm/smp_plat.h> 317ac9b9ebSMarc Zyngier #include <asm/smp_twd.h> 32220e6cf7SRob Herring #include <asm/hardware/arm_timer.h> 33220e6cf7SRob Herring #include <asm/hardware/timer-sp.h> 34220e6cf7SRob Herring #include <asm/hardware/gic.h> 35220e6cf7SRob Herring #include <asm/hardware/cache-l2x0.h> 36220e6cf7SRob Herring #include <asm/mach/arch.h> 37220e6cf7SRob Herring #include <asm/mach/time.h> 38220e6cf7SRob Herring 39220e6cf7SRob Herring #include "core.h" 40220e6cf7SRob Herring #include "sysregs.h" 41220e6cf7SRob Herring 42220e6cf7SRob Herring void __iomem *sregs_base; 437a2848d3SRob Herring void __iomem *scu_base_addr; 44220e6cf7SRob Herring 45220e6cf7SRob Herring static void __init highbank_scu_map_io(void) 46220e6cf7SRob Herring { 47220e6cf7SRob Herring unsigned long base; 48220e6cf7SRob Herring 49220e6cf7SRob Herring /* Get SCU base */ 50220e6cf7SRob Herring asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); 51220e6cf7SRob Herring 527a2848d3SRob Herring scu_base_addr = ioremap(base, SZ_4K); 53220e6cf7SRob Herring } 54220e6cf7SRob Herring 55220e6cf7SRob Herring static void __init highbank_map_io(void) 56220e6cf7SRob Herring { 57220e6cf7SRob Herring highbank_lluart_map_io(); 58220e6cf7SRob Herring } 59220e6cf7SRob Herring 60220e6cf7SRob Herring #define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu))) 61220e6cf7SRob Herring #define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu)) 62220e6cf7SRob Herring 63220e6cf7SRob Herring void highbank_set_cpu_jump(int cpu, void *jump_addr) 64220e6cf7SRob Herring { 65bf14fc54SWill Deacon cpu = cpu_logical_map(cpu); 66adf55f7fSRob Herring writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu)); 67220e6cf7SRob Herring __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); 68220e6cf7SRob Herring outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), 69220e6cf7SRob Herring HB_JUMP_TABLE_PHYS(cpu) + 15); 70220e6cf7SRob Herring } 71220e6cf7SRob Herring 72220e6cf7SRob Herring const static struct of_device_id irq_match[] = { 73220e6cf7SRob Herring { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, 74220e6cf7SRob Herring {} 75220e6cf7SRob Herring }; 76220e6cf7SRob Herring 778e56130dSRob Herring #ifdef CONFIG_CACHE_L2X0 788e56130dSRob Herring static void highbank_l2x0_disable(void) 798e56130dSRob Herring { 808e56130dSRob Herring /* Disable PL310 L2 Cache controller */ 818e56130dSRob Herring highbank_smc1(0x102, 0x0); 828e56130dSRob Herring } 838e56130dSRob Herring #endif 848e56130dSRob Herring 85220e6cf7SRob Herring static void __init highbank_init_irq(void) 86220e6cf7SRob Herring { 87220e6cf7SRob Herring of_irq_init(irq_match); 888e56130dSRob Herring 897a2848d3SRob Herring if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9")) 907a2848d3SRob Herring highbank_scu_map_io(); 917a2848d3SRob Herring 928e56130dSRob Herring #ifdef CONFIG_CACHE_L2X0 938e56130dSRob Herring /* Enable PL310 L2 Cache controller */ 948e56130dSRob Herring highbank_smc1(0x102, 0x1); 95220e6cf7SRob Herring l2x0_of_init(0, ~0UL); 968e56130dSRob Herring outer_cache.disable = highbank_l2x0_disable; 978e56130dSRob Herring #endif 98220e6cf7SRob Herring } 99220e6cf7SRob Herring 1008d4d9f52SRob Herring static struct clk_lookup lookup = { 1018d4d9f52SRob Herring .dev_id = "sp804", 1028d4d9f52SRob Herring .con_id = NULL, 1038d4d9f52SRob Herring }; 1048d4d9f52SRob Herring 105220e6cf7SRob Herring static void __init highbank_timer_init(void) 106220e6cf7SRob Herring { 107220e6cf7SRob Herring int irq; 108220e6cf7SRob Herring struct device_node *np; 109220e6cf7SRob Herring void __iomem *timer_base; 110220e6cf7SRob Herring 111220e6cf7SRob Herring /* Map system registers */ 112220e6cf7SRob Herring np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); 113220e6cf7SRob Herring sregs_base = of_iomap(np, 0); 114220e6cf7SRob Herring WARN_ON(!sregs_base); 115220e6cf7SRob Herring 116220e6cf7SRob Herring np = of_find_compatible_node(NULL, NULL, "arm,sp804"); 117220e6cf7SRob Herring timer_base = of_iomap(np, 0); 118220e6cf7SRob Herring WARN_ON(!timer_base); 119220e6cf7SRob Herring irq = irq_of_parse_and_map(np, 0); 120220e6cf7SRob Herring 121220e6cf7SRob Herring highbank_clocks_init(); 1228d4d9f52SRob Herring lookup.clk = of_clk_get(np, 0); 1238d4d9f52SRob Herring clkdev_add(&lookup); 124220e6cf7SRob Herring 125f3b7cd2aSRob Herring sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); 126220e6cf7SRob Herring sp804_clockevents_init(timer_base, irq, "timer0"); 1277ac9b9ebSMarc Zyngier 1287ac9b9ebSMarc Zyngier twd_local_timer_of_register(); 129220e6cf7SRob Herring } 130220e6cf7SRob Herring 131220e6cf7SRob Herring static struct sys_timer highbank_timer = { 132220e6cf7SRob Herring .init = highbank_timer_init, 133220e6cf7SRob Herring }; 134220e6cf7SRob Herring 135220e6cf7SRob Herring static void highbank_power_off(void) 136220e6cf7SRob Herring { 137220e6cf7SRob Herring hignbank_set_pwr_shutdown(); 138220e6cf7SRob Herring 139220e6cf7SRob Herring while (1) 140220e6cf7SRob Herring cpu_do_idle(); 141220e6cf7SRob Herring } 142220e6cf7SRob Herring 1431dc737c4SRob Herring static int highbank_platform_notifier(struct notifier_block *nb, 1441dc737c4SRob Herring unsigned long event, void *__dev) 1451dc737c4SRob Herring { 1461dc737c4SRob Herring struct resource *res; 1471dc737c4SRob Herring int reg = -1; 1481dc737c4SRob Herring struct device *dev = __dev; 1491dc737c4SRob Herring 1501dc737c4SRob Herring if (event != BUS_NOTIFY_ADD_DEVICE) 1511dc737c4SRob Herring return NOTIFY_DONE; 1521dc737c4SRob Herring 1531dc737c4SRob Herring if (of_device_is_compatible(dev->of_node, "calxeda,hb-ahci")) 1541dc737c4SRob Herring reg = 0xc; 1551dc737c4SRob Herring else if (of_device_is_compatible(dev->of_node, "calxeda,hb-sdhci")) 1561dc737c4SRob Herring reg = 0x18; 1571dc737c4SRob Herring else if (of_device_is_compatible(dev->of_node, "arm,pl330")) 1581dc737c4SRob Herring reg = 0x20; 1591dc737c4SRob Herring else if (of_device_is_compatible(dev->of_node, "calxeda,hb-xgmac")) { 1601dc737c4SRob Herring res = platform_get_resource(to_platform_device(dev), 1611dc737c4SRob Herring IORESOURCE_MEM, 0); 1621dc737c4SRob Herring if (res) { 1631dc737c4SRob Herring if (res->start == 0xfff50000) 1641dc737c4SRob Herring reg = 0; 1651dc737c4SRob Herring else if (res->start == 0xfff51000) 1661dc737c4SRob Herring reg = 4; 1671dc737c4SRob Herring } 1681dc737c4SRob Herring } 1691dc737c4SRob Herring 1701dc737c4SRob Herring if (reg < 0) 1711dc737c4SRob Herring return NOTIFY_DONE; 1721dc737c4SRob Herring 1731dc737c4SRob Herring if (of_property_read_bool(dev->of_node, "dma-coherent")) { 1741dc737c4SRob Herring writel(0xff31, sregs_base + reg); 1751dc737c4SRob Herring set_dma_ops(dev, &arm_coherent_dma_ops); 1761dc737c4SRob Herring } else 1771dc737c4SRob Herring writel(0, sregs_base + reg); 1781dc737c4SRob Herring 1791dc737c4SRob Herring return NOTIFY_OK; 1801dc737c4SRob Herring } 1811dc737c4SRob Herring 1821dc737c4SRob Herring static struct notifier_block highbank_amba_nb = { 1831dc737c4SRob Herring .notifier_call = highbank_platform_notifier, 1841dc737c4SRob Herring }; 1851dc737c4SRob Herring 1861dc737c4SRob Herring static struct notifier_block highbank_platform_nb = { 1871dc737c4SRob Herring .notifier_call = highbank_platform_notifier, 1881dc737c4SRob Herring }; 1891dc737c4SRob Herring 190220e6cf7SRob Herring static void __init highbank_init(void) 191220e6cf7SRob Herring { 192220e6cf7SRob Herring pm_power_off = highbank_power_off; 193a283580cSRob Herring highbank_pm_init(); 194220e6cf7SRob Herring 1951dc737c4SRob Herring bus_register_notifier(&platform_bus_type, &highbank_platform_nb); 1961dc737c4SRob Herring bus_register_notifier(&amba_bustype, &highbank_amba_nb); 1971dc737c4SRob Herring 198220e6cf7SRob Herring of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 199220e6cf7SRob Herring } 200220e6cf7SRob Herring 201220e6cf7SRob Herring static const char *highbank_match[] __initconst = { 202220e6cf7SRob Herring "calxeda,highbank", 203220e6cf7SRob Herring NULL, 204220e6cf7SRob Herring }; 205220e6cf7SRob Herring 206220e6cf7SRob Herring DT_MACHINE_START(HIGHBANK, "Highbank") 2077ad71b61SMarc Zyngier .smp = smp_ops(highbank_smp_ops), 208220e6cf7SRob Herring .map_io = highbank_map_io, 209220e6cf7SRob Herring .init_irq = highbank_init_irq, 210220e6cf7SRob Herring .timer = &highbank_timer, 2117e01799cSMarc Zyngier .handle_irq = gic_handle_irq, 212220e6cf7SRob Herring .init_machine = highbank_init, 213220e6cf7SRob Herring .dt_compat = highbank_match, 21400e9967eSRussell King .restart = highbank_restart, 215220e6cf7SRob Herring MACHINE_END 216