1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * arch/arm/include/asm/pgtable-3level.h
4  *
5  * Copyright (C) 2011 ARM Ltd.
6  * Author: Catalin Marinas <catalin.marinas@arm.com>
7  */
8 #ifndef _ASM_PGTABLE_3LEVEL_H
9 #define _ASM_PGTABLE_3LEVEL_H
10 
11 /*
12  * With LPAE, there are 3 levels of page tables. Each level has 512 entries of
13  * 8 bytes each, occupying a 4K page. The first level table covers a range of
14  * 512GB, each entry representing 1GB. Since we are limited to 4GB input
15  * address range, only 4 entries in the PGD are used.
16  *
17  * There are enough spare bits in a page table entry for the kernel specific
18  * state.
19  */
20 #define PTRS_PER_PTE		512
21 #define PTRS_PER_PMD		512
22 #define PTRS_PER_PGD		4
23 
24 #define PTE_HWTABLE_PTRS	(0)
25 #define PTE_HWTABLE_OFF		(0)
26 #define PTE_HWTABLE_SIZE	(PTRS_PER_PTE * sizeof(u64))
27 
28 #define MAX_POSSIBLE_PHYSMEM_BITS 40
29 
30 /*
31  * PGDIR_SHIFT determines the size a top-level page table entry can map.
32  */
33 #define PGDIR_SHIFT		30
34 
35 /*
36  * PMD_SHIFT determines the size a middle-level page table entry can map.
37  */
38 #define PMD_SHIFT		21
39 
40 #define PMD_SIZE		(1UL << PMD_SHIFT)
41 #define PMD_MASK		(~((1 << PMD_SHIFT) - 1))
42 #define PGDIR_SIZE		(1UL << PGDIR_SHIFT)
43 #define PGDIR_MASK		(~((1 << PGDIR_SHIFT) - 1))
44 
45 /*
46  * section address mask and size definitions.
47  */
48 #define SECTION_SHIFT		21
49 #define SECTION_SIZE		(1UL << SECTION_SHIFT)
50 #define SECTION_MASK		(~((1 << SECTION_SHIFT) - 1))
51 
52 #define USER_PTRS_PER_PGD	(PAGE_OFFSET / PGDIR_SIZE)
53 
54 /*
55  * Hugetlb definitions.
56  */
57 #define HPAGE_SHIFT		PMD_SHIFT
58 #define HPAGE_SIZE		(_AC(1, UL) << HPAGE_SHIFT)
59 #define HPAGE_MASK		(~(HPAGE_SIZE - 1))
60 #define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)
61 
62 /*
63  * "Linux" PTE definitions for LPAE.
64  *
65  * These bits overlap with the hardware bits but the naming is preserved for
66  * consistency with the classic page table format.
67  */
68 #define L_PTE_VALID		(_AT(pteval_t, 1) << 0)		/* Valid */
69 #define L_PTE_PRESENT		(_AT(pteval_t, 3) << 0)		/* Present */
70 #define L_PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
71 #define L_PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
72 #define L_PTE_YOUNG		(_AT(pteval_t, 1) << 10)	/* AF */
73 #define L_PTE_XN		(_AT(pteval_t, 1) << 54)	/* XN */
74 #define L_PTE_DIRTY		(_AT(pteval_t, 1) << 55)
75 #define L_PTE_SPECIAL		(_AT(pteval_t, 1) << 56)
76 #define L_PTE_NONE		(_AT(pteval_t, 1) << 57)	/* PROT_NONE */
77 #define L_PTE_RDONLY		(_AT(pteval_t, 1) << 58)	/* READ ONLY */
78 
79 /* We borrow bit 7 to store the exclusive marker in swap PTEs. */
80 #define L_PTE_SWP_EXCLUSIVE	(_AT(pteval_t, 1) << 7)
81 
82 #define L_PMD_SECT_VALID	(_AT(pmdval_t, 1) << 0)
83 #define L_PMD_SECT_DIRTY	(_AT(pmdval_t, 1) << 55)
84 #define L_PMD_SECT_NONE		(_AT(pmdval_t, 1) << 57)
85 #define L_PMD_SECT_RDONLY	(_AT(pteval_t, 1) << 58)
86 
87 /*
88  * To be used in assembly code with the upper page attributes.
89  */
90 #define L_PTE_XN_HIGH		(1 << (54 - 32))
91 #define L_PTE_DIRTY_HIGH	(1 << (55 - 32))
92 
93 /*
94  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
95  */
96 #define L_PTE_MT_UNCACHED	(_AT(pteval_t, 0) << 2)	/* strongly ordered */
97 #define L_PTE_MT_BUFFERABLE	(_AT(pteval_t, 1) << 2)	/* normal non-cacheable */
98 #define L_PTE_MT_WRITETHROUGH	(_AT(pteval_t, 2) << 2)	/* normal inner write-through */
99 #define L_PTE_MT_WRITEBACK	(_AT(pteval_t, 3) << 2)	/* normal inner write-back */
100 #define L_PTE_MT_WRITEALLOC	(_AT(pteval_t, 7) << 2)	/* normal inner write-alloc */
101 #define L_PTE_MT_DEV_SHARED	(_AT(pteval_t, 4) << 2)	/* device */
102 #define L_PTE_MT_DEV_NONSHARED	(_AT(pteval_t, 4) << 2)	/* device */
103 #define L_PTE_MT_DEV_WC		(_AT(pteval_t, 1) << 2)	/* normal non-cacheable */
104 #define L_PTE_MT_DEV_CACHED	(_AT(pteval_t, 3) << 2)	/* normal inner write-back */
105 #define L_PTE_MT_MASK		(_AT(pteval_t, 7) << 2)
106 
107 /*
108  * Software PGD flags.
109  */
110 #define L_PGD_SWAPPER		(_AT(pgdval_t, 1) << 55)	/* swapper_pg_dir entry */
111 
112 #ifndef __ASSEMBLY__
113 
114 #define pud_none(pud)		(!pud_val(pud))
115 #define pud_bad(pud)		(!(pud_val(pud) & 2))
116 #define pud_present(pud)	(pud_val(pud))
117 #define pmd_table(pmd)		((pmd_val(pmd) & PMD_TYPE_MASK) == \
118 						 PMD_TYPE_TABLE)
119 #define pmd_sect(pmd)		((pmd_val(pmd) & PMD_TYPE_MASK) == \
120 						 PMD_TYPE_SECT)
121 #define pmd_large(pmd)		pmd_sect(pmd)
122 #define pmd_leaf(pmd)		pmd_sect(pmd)
123 
124 #define pud_clear(pudp)			\
125 	do {				\
126 		*pudp = __pud(0);	\
127 		clean_pmd_entry(pudp);	\
128 	} while (0)
129 
130 #define set_pud(pudp, pud)		\
131 	do {				\
132 		*pudp = pud;		\
133 		flush_pmd_entry(pudp);	\
134 	} while (0)
135 
136 static inline pmd_t *pud_pgtable(pud_t pud)
137 {
138 	return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
139 }
140 
141 #define pmd_bad(pmd)		(!(pmd_val(pmd) & 2))
142 
143 #define copy_pmd(pmdpd,pmdps)		\
144 	do {				\
145 		*pmdpd = *pmdps;	\
146 		flush_pmd_entry(pmdpd);	\
147 	} while (0)
148 
149 #define pmd_clear(pmdp)			\
150 	do {				\
151 		*pmdp = __pmd(0);	\
152 		clean_pmd_entry(pmdp);	\
153 	} while (0)
154 
155 /*
156  * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
157  * that are written to a page table but not for ptes created with mk_pte.
158  *
159  * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
160  * hugetlb_cow, where it is compared with an entry in a page table.
161  * This comparison test fails erroneously leading ultimately to a memory leak.
162  *
163  * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
164  * present before running the comparison.
165  */
166 #define __HAVE_ARCH_PTE_SAME
167 #define pte_same(pte_a,pte_b)	((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG	\
168 					: pte_val(pte_a))				\
169 				== (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG	\
170 					: pte_val(pte_b)))
171 
172 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
173 
174 #define pte_huge(pte)		(pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
175 #define pte_mkhuge(pte)		(__pte(pte_val(pte) & ~PTE_TABLE_BIT))
176 
177 #define pmd_isset(pmd, val)	((u32)(val) == (val) ? pmd_val(pmd) & (val) \
178 						: !!(pmd_val(pmd) & (val)))
179 #define pmd_isclear(pmd, val)	(!(pmd_val(pmd) & (val)))
180 
181 #define pmd_present(pmd)	(pmd_isset((pmd), L_PMD_SECT_VALID))
182 #define pmd_young(pmd)		(pmd_isset((pmd), PMD_SECT_AF))
183 #define pte_special(pte)	(pte_isset((pte), L_PTE_SPECIAL))
184 static inline pte_t pte_mkspecial(pte_t pte)
185 {
186 	pte_val(pte) |= L_PTE_SPECIAL;
187 	return pte;
188 }
189 
190 #define pmd_write(pmd)		(pmd_isclear((pmd), L_PMD_SECT_RDONLY))
191 #define pmd_dirty(pmd)		(pmd_isset((pmd), L_PMD_SECT_DIRTY))
192 
193 #define pmd_hugewillfault(pmd)	(!pmd_young(pmd) || !pmd_write(pmd))
194 #define pmd_thp_or_huge(pmd)	(pmd_huge(pmd) || pmd_trans_huge(pmd))
195 
196 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
197 #define pmd_trans_huge(pmd)	(pmd_val(pmd) && !pmd_table(pmd))
198 #endif
199 
200 #define PMD_BIT_FUNC(fn,op) \
201 static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
202 
203 PMD_BIT_FUNC(wrprotect,	|= L_PMD_SECT_RDONLY);
204 PMD_BIT_FUNC(mkold,	&= ~PMD_SECT_AF);
205 PMD_BIT_FUNC(mkwrite_novma,   &= ~L_PMD_SECT_RDONLY);
206 PMD_BIT_FUNC(mkdirty,   |= L_PMD_SECT_DIRTY);
207 PMD_BIT_FUNC(mkclean,   &= ~L_PMD_SECT_DIRTY);
208 PMD_BIT_FUNC(mkyoung,   |= PMD_SECT_AF);
209 
210 #define pmd_mkhuge(pmd)		(__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
211 
212 #define pmd_pfn(pmd)		(((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
213 #define pfn_pmd(pfn,prot)	(__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
214 #define mk_pmd(page,prot)	pfn_pmd(page_to_pfn(page),prot)
215 
216 /* No hardware dirty/accessed bits -- generic_pmdp_establish() fits */
217 #define pmdp_establish generic_pmdp_establish
218 
219 /* represent a notpresent pmd by faulting entry, this is used by pmdp_invalidate */
220 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
221 {
222 	return __pmd(pmd_val(pmd) & ~L_PMD_SECT_VALID);
223 }
224 
225 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
226 {
227 	const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | L_PMD_SECT_RDONLY |
228 				L_PMD_SECT_VALID | L_PMD_SECT_NONE;
229 	pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
230 	return pmd;
231 }
232 
233 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
234 			      pmd_t *pmdp, pmd_t pmd)
235 {
236 	BUG_ON(addr >= TASK_SIZE);
237 
238 	/* create a faulting entry if PROT_NONE protected */
239 	if (pmd_val(pmd) & L_PMD_SECT_NONE)
240 		pmd_val(pmd) &= ~L_PMD_SECT_VALID;
241 
242 	if (pmd_write(pmd) && pmd_dirty(pmd))
243 		pmd_val(pmd) &= ~PMD_SECT_AP2;
244 	else
245 		pmd_val(pmd) |= PMD_SECT_AP2;
246 
247 	*pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
248 	flush_pmd_entry(pmdp);
249 }
250 
251 #endif /* __ASSEMBLY__ */
252 
253 #endif /* _ASM_PGTABLE_3LEVEL_H */
254