1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/include/asm/pgtable-3level.h 4 * 5 * Copyright (C) 2011 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 #ifndef _ASM_PGTABLE_3LEVEL_H 9 #define _ASM_PGTABLE_3LEVEL_H 10 11 /* 12 * With LPAE, there are 3 levels of page tables. Each level has 512 entries of 13 * 8 bytes each, occupying a 4K page. The first level table covers a range of 14 * 512GB, each entry representing 1GB. Since we are limited to 4GB input 15 * address range, only 4 entries in the PGD are used. 16 * 17 * There are enough spare bits in a page table entry for the kernel specific 18 * state. 19 */ 20 #define PTRS_PER_PTE 512 21 #define PTRS_PER_PMD 512 22 #define PTRS_PER_PGD 4 23 24 #define PTE_HWTABLE_PTRS (0) 25 #define PTE_HWTABLE_OFF (0) 26 #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64)) 27 28 /* 29 * PGDIR_SHIFT determines the size a top-level page table entry can map. 30 */ 31 #define PGDIR_SHIFT 30 32 33 /* 34 * PMD_SHIFT determines the size a middle-level page table entry can map. 35 */ 36 #define PMD_SHIFT 21 37 38 #define PMD_SIZE (1UL << PMD_SHIFT) 39 #define PMD_MASK (~((1 << PMD_SHIFT) - 1)) 40 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 41 #define PGDIR_MASK (~((1 << PGDIR_SHIFT) - 1)) 42 43 /* 44 * section address mask and size definitions. 45 */ 46 #define SECTION_SHIFT 21 47 #define SECTION_SIZE (1UL << SECTION_SHIFT) 48 #define SECTION_MASK (~((1 << SECTION_SHIFT) - 1)) 49 50 #define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE) 51 52 /* 53 * Hugetlb definitions. 54 */ 55 #define HPAGE_SHIFT PMD_SHIFT 56 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 57 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 58 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 59 60 /* 61 * "Linux" PTE definitions for LPAE. 62 * 63 * These bits overlap with the hardware bits but the naming is preserved for 64 * consistency with the classic page table format. 65 */ 66 #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */ 67 #define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */ 68 #define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 69 #define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 70 #define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */ 71 #define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */ 72 #define L_PTE_DIRTY (_AT(pteval_t, 1) << 55) 73 #define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56) 74 #define L_PTE_NONE (_AT(pteval_t, 1) << 57) /* PROT_NONE */ 75 #define L_PTE_RDONLY (_AT(pteval_t, 1) << 58) /* READ ONLY */ 76 77 #define L_PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 78 #define L_PMD_SECT_DIRTY (_AT(pmdval_t, 1) << 55) 79 #define L_PMD_SECT_NONE (_AT(pmdval_t, 1) << 57) 80 #define L_PMD_SECT_RDONLY (_AT(pteval_t, 1) << 58) 81 82 /* 83 * To be used in assembly code with the upper page attributes. 84 */ 85 #define L_PTE_XN_HIGH (1 << (54 - 32)) 86 #define L_PTE_DIRTY_HIGH (1 << (55 - 32)) 87 88 /* 89 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 90 */ 91 #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */ 92 #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 93 #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */ 94 #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 95 #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */ 96 #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */ 97 #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */ 98 #define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 99 #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 100 #define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2) 101 102 /* 103 * Software PGD flags. 104 */ 105 #define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */ 106 107 #ifndef __ASSEMBLY__ 108 109 #define pud_none(pud) (!pud_val(pud)) 110 #define pud_bad(pud) (!(pud_val(pud) & 2)) 111 #define pud_present(pud) (pud_val(pud)) 112 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 113 PMD_TYPE_TABLE) 114 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 115 PMD_TYPE_SECT) 116 #define pmd_large(pmd) pmd_sect(pmd) 117 #define pmd_leaf(pmd) pmd_sect(pmd) 118 119 #define pud_clear(pudp) \ 120 do { \ 121 *pudp = __pud(0); \ 122 clean_pmd_entry(pudp); \ 123 } while (0) 124 125 #define set_pud(pudp, pud) \ 126 do { \ 127 *pudp = pud; \ 128 flush_pmd_entry(pudp); \ 129 } while (0) 130 131 static inline pmd_t *pud_page_vaddr(pud_t pud) 132 { 133 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); 134 } 135 136 /* Find an entry in the second-level page table.. */ 137 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 138 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) 139 { 140 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr); 141 } 142 143 #define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) 144 145 #define copy_pmd(pmdpd,pmdps) \ 146 do { \ 147 *pmdpd = *pmdps; \ 148 flush_pmd_entry(pmdpd); \ 149 } while (0) 150 151 #define pmd_clear(pmdp) \ 152 do { \ 153 *pmdp = __pmd(0); \ 154 clean_pmd_entry(pmdp); \ 155 } while (0) 156 157 /* 158 * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes 159 * that are written to a page table but not for ptes created with mk_pte. 160 * 161 * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to 162 * hugetlb_cow, where it is compared with an entry in a page table. 163 * This comparison test fails erroneously leading ultimately to a memory leak. 164 * 165 * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is 166 * present before running the comparison. 167 */ 168 #define __HAVE_ARCH_PTE_SAME 169 #define pte_same(pte_a,pte_b) ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG \ 170 : pte_val(pte_a)) \ 171 == (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG \ 172 : pte_val(pte_b))) 173 174 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext))) 175 176 #define pte_huge(pte) (pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT)) 177 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 178 179 #define pmd_isset(pmd, val) ((u32)(val) == (val) ? pmd_val(pmd) & (val) \ 180 : !!(pmd_val(pmd) & (val))) 181 #define pmd_isclear(pmd, val) (!(pmd_val(pmd) & (val))) 182 183 #define pmd_present(pmd) (pmd_isset((pmd), L_PMD_SECT_VALID)) 184 #define pmd_young(pmd) (pmd_isset((pmd), PMD_SECT_AF)) 185 #define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL)) 186 static inline pte_t pte_mkspecial(pte_t pte) 187 { 188 pte_val(pte) |= L_PTE_SPECIAL; 189 return pte; 190 } 191 192 #define pmd_write(pmd) (pmd_isclear((pmd), L_PMD_SECT_RDONLY)) 193 #define pmd_dirty(pmd) (pmd_isset((pmd), L_PMD_SECT_DIRTY)) 194 #define pud_page(pud) pmd_page(__pmd(pud_val(pud))) 195 #define pud_write(pud) pmd_write(__pmd(pud_val(pud))) 196 197 #define pmd_hugewillfault(pmd) (!pmd_young(pmd) || !pmd_write(pmd)) 198 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 199 200 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 201 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !pmd_table(pmd)) 202 #endif 203 204 #define PMD_BIT_FUNC(fn,op) \ 205 static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; } 206 207 PMD_BIT_FUNC(wrprotect, |= L_PMD_SECT_RDONLY); 208 PMD_BIT_FUNC(mkold, &= ~PMD_SECT_AF); 209 PMD_BIT_FUNC(mkwrite, &= ~L_PMD_SECT_RDONLY); 210 PMD_BIT_FUNC(mkdirty, |= L_PMD_SECT_DIRTY); 211 PMD_BIT_FUNC(mkclean, &= ~L_PMD_SECT_DIRTY); 212 PMD_BIT_FUNC(mkyoung, |= PMD_SECT_AF); 213 214 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 215 216 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 217 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 218 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 219 220 /* No hardware dirty/accessed bits -- generic_pmdp_establish() fits */ 221 #define pmdp_establish generic_pmdp_establish 222 223 /* represent a notpresent pmd by faulting entry, this is used by pmdp_invalidate */ 224 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 225 { 226 return __pmd(pmd_val(pmd) & ~L_PMD_SECT_VALID); 227 } 228 229 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 230 { 231 const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | L_PMD_SECT_RDONLY | 232 L_PMD_SECT_VALID | L_PMD_SECT_NONE; 233 pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask); 234 return pmd; 235 } 236 237 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 238 pmd_t *pmdp, pmd_t pmd) 239 { 240 BUG_ON(addr >= TASK_SIZE); 241 242 /* create a faulting entry if PROT_NONE protected */ 243 if (pmd_val(pmd) & L_PMD_SECT_NONE) 244 pmd_val(pmd) &= ~L_PMD_SECT_VALID; 245 246 if (pmd_write(pmd) && pmd_dirty(pmd)) 247 pmd_val(pmd) &= ~PMD_SECT_AP2; 248 else 249 pmd_val(pmd) |= PMD_SECT_AP2; 250 251 *pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG); 252 flush_pmd_entry(pmdp); 253 } 254 255 #endif /* __ASSEMBLY__ */ 256 257 #endif /* _ASM_PGTABLE_3LEVEL_H */ 258