1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright 2014-2022 Toradex 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pwm/pwm.h> 10 11/ { 12 model = "Toradex Colibri iMX6DL/S Module"; 13 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; 14 15 backlight: backlight { 16 compatible = "pwm-backlight"; 17 brightness-levels = <0 45 63 88 119 158 203 255>; 18 default-brightness-level = <4>; 19 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_gpio_bl_on>; 22 power-supply = <®_module_3v3>; 23 pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>; 24 status = "disabled"; 25 }; 26 27 extcon_usbc_det: usbc-det { 28 compatible = "linux,extcon-usb-gpio"; 29 id-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ 30 pinctrl-names = "default"; 31 pinctrl-0 = <&pinctrl_usbc_det>; 32 }; 33 34 gpio-keys { 35 compatible = "gpio-keys"; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&pinctrl_gpio_keys>; 38 39 key-wakeup { 40 debounce-interval = <10>; 41 gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ 42 label = "Wake-Up"; 43 linux,code = <KEY_WAKEUP>; 44 wakeup-source; 45 }; 46 }; 47 48 lcd_display: disp0 { 49 compatible = "fsl,imx-parallel-display"; 50 interface-pix-fmt = "bgr666"; 51 pinctrl-names = "default"; 52 pinctrl-0 = <&pinctrl_ipu1_lcdif>; 53 status = "disabled"; 54 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 port@0 { 59 reg = <0>; 60 61 lcd_display_in: endpoint { 62 remote-endpoint = <&ipu1_di0_disp0>; 63 }; 64 }; 65 66 port@1 { 67 reg = <1>; 68 69 lcd_display_out: endpoint { 70 remote-endpoint = <&lcd_panel_in>; 71 }; 72 }; 73 }; 74 75 /* Will be filled by the bootloader */ 76 memory@10000000 { 77 device_type = "memory"; 78 reg = <0x10000000 0>; 79 }; 80 81 panel_dpi: panel-dpi { 82 /* 83 * edt,et057090dhu: EDT 5.7" LCD TFT 84 * edt,et070080dh6: EDT 7.0" LCD TFT 85 */ 86 compatible = "edt,et057090dhu"; 87 backlight = <&backlight>; 88 status = "disabled"; 89 90 port { 91 lcd_panel_in: endpoint { 92 remote-endpoint = <&lcd_display_out>; 93 }; 94 }; 95 }; 96 97 reg_module_3v3: regulator-module-3v3 { 98 compatible = "regulator-fixed"; 99 regulator-name = "+V3.3"; 100 regulator-min-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>; 102 regulator-always-on; 103 }; 104 105 reg_module_3v3_audio: regulator-module-3v3-audio { 106 compatible = "regulator-fixed"; 107 regulator-name = "+V3.3_AUDIO"; 108 regulator-min-microvolt = <3300000>; 109 regulator-max-microvolt = <3300000>; 110 regulator-always-on; 111 }; 112 113 reg_usb_host_vbus: regulator-usb-host-vbus { 114 compatible = "regulator-fixed"; 115 gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */ 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 118 regulator-max-microvolt = <5000000>; 119 regulator-min-microvolt = <5000000>; 120 regulator-name = "usb_host_vbus"; 121 status = "disabled"; 122 }; 123 124 sound { 125 compatible = "fsl,imx-audio-sgtl5000"; 126 audio-codec = <&codec>; 127 audio-routing = 128 "Headphone Jack", "HP_OUT", 129 "LINE_IN", "Line In Jack", 130 "MIC_IN", "Mic Jack", 131 "Mic Jack", "Mic Bias"; 132 model = "imx6dl-colibri-sgtl5000"; 133 mux-int-port = <1>; 134 mux-ext-port = <5>; 135 ssi-controller = <&ssi1>; 136 }; 137 138 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ 139 sound_spdif: sound-spdif { 140 compatible = "fsl,imx-audio-spdif"; 141 spdif-controller = <&spdif>; 142 spdif-in; 143 spdif-out; 144 model = "imx-spdif"; 145 status = "disabled"; 146 }; 147}; 148 149&audmux { 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; 152 status = "okay"; 153}; 154 155/* Optional on SODIMM 55/63 */ 156&can1 { 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_flexcan1>; 159 status = "disabled"; 160}; 161 162/* Optional on SODIMM 178/188 */ 163&can2 { 164 pinctrl-names = "default"; 165 pinctrl-0 = <&pinctrl_flexcan2>; 166 status = "disabled"; 167}; 168 169&clks { 170 fsl,pmic-stby-poweroff; 171}; 172 173/* Colibri SSP */ 174&ecspi4 { 175 cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_ecspi4>; 178 status = "disabled"; 179}; 180 181&fec { 182 phy-mode = "rmii"; 183 phy-handle = <ðphy>; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_enet>; 186 status = "okay"; 187 188 mdio { 189 #address-cells = <1>; 190 #size-cells = <0>; 191 192 ethphy: ethernet-phy@0 { 193 reg = <0>; 194 micrel,led-mode = <0>; 195 }; 196 }; 197}; 198 199&gpio1 { 200 gpio-line-names = "", 201 "SODIMM_67", 202 "SODIMM_180", 203 "SODIMM_196", 204 "SODIMM_174", 205 "SODIMM_176", 206 "SODIMM_194", 207 "SODIMM_55", 208 "SODIMM_63", 209 "SODIMM_28", 210 "SODIMM_93", 211 "SODIMM_69", 212 "SODIMM_99", 213 "SODIMM_130", 214 "SODIMM_106", 215 "SODIMM_98", 216 "SODIMM_192", 217 "SODIMM_49", 218 "SODIMM_190", 219 "SODIMM_51", 220 "SODIMM_47", 221 "SODIMM_53", 222 "", 223 "SODIMM_22"; 224}; 225 226&gpio2 { 227 gpio-line-names = "SODIMM_132", 228 "SODIMM_134", 229 "SODIMM_135", 230 "SODIMM_133", 231 "SODIMM_102", 232 "SODIMM_43", 233 "SODIMM_127", 234 "SODIMM_37", 235 "SODIMM_104", 236 "SODIMM_59", 237 "SODIMM_30", 238 "SODIMM_100", 239 "SODIMM_38", 240 "SODIMM_34", 241 "SODIMM_32", 242 "SODIMM_36", 243 "SODIMM_59", 244 "SODIMM_67", 245 "SODIMM_97", 246 "SODIMM_79", 247 "SODIMM_103", 248 "SODIMM_101", 249 "SODIMM_45", 250 "SODIMM_105", 251 "SODIMM_107", 252 "SODIMM_91", 253 "SODIMM_89", 254 "SODIMM_150", 255 "SODIMM_126", 256 "SODIMM_128", 257 "", 258 "SODIMM_94"; 259}; 260 261&gpio3 { 262 gpio-line-names = "SODIMM_111", 263 "SODIMM_113", 264 "SODIMM_115", 265 "SODIMM_117", 266 "SODIMM_119", 267 "SODIMM_121", 268 "SODIMM_123", 269 "SODIMM_125", 270 "SODIMM_110", 271 "SODIMM_112", 272 "SODIMM_114", 273 "SODIMM_116", 274 "SODIMM_118", 275 "SODIMM_120", 276 "SODIMM_122", 277 "SODIMM_124", 278 "", 279 "SODIMM_96", 280 "SODIMM_77", 281 "SODIMM_25", 282 "SODIMM_27", 283 "SODIMM_88", 284 "SODIMM_90", 285 "SODIMM_31", 286 "SODIMM_23", 287 "SODIMM_29", 288 "SODIMM_71", 289 "SODIMM_73", 290 "SODIMM_92", 291 "SODIMM_81", 292 "SODIMM_131", 293 "SODIMM_129"; 294}; 295 296&gpio4 { 297 gpio-line-names = "", 298 "", 299 "", 300 "", 301 "", 302 "SODIMM_168", 303 "", 304 "", 305 "", 306 "", 307 "SODIMM_184", 308 "SODIMM_186", 309 "HDMI_15", 310 "HDMI_16", 311 "SODIMM_178", 312 "SODIMM_188", 313 "SODIMM_56", 314 "SODIMM_44", 315 "SODIMM_68", 316 "SODIMM_82", 317 "SODIMM_24", 318 "SODIMM_76", 319 "SODIMM_70", 320 "SODIMM_60", 321 "SODIMM_58", 322 "SODIMM_78", 323 "SODIMM_72", 324 "SODIMM_80", 325 "SODIMM_46", 326 "SODIMM_62", 327 "SODIMM_48", 328 "SODIMM_74"; 329}; 330 331&gpio5 { 332 gpio-line-names = "SODIMM_95", 333 "", 334 "SODIMM_86", 335 "", 336 "SODIMM_65", 337 "SODIMM_50", 338 "SODIMM_52", 339 "SODIMM_54", 340 "SODIMM_66", 341 "SODIMM_64", 342 "SODIMM_57", 343 "SODIMM_61", 344 "SODIMM_136", 345 "SODIMM_138", 346 "SODIMM_140", 347 "SODIMM_142", 348 "SODIMM_144", 349 "SODIMM_146", 350 "SODIMM_172", 351 "SODIMM_170", 352 "SODIMM_149", 353 "SODIMM_151", 354 "SODIMM_153", 355 "SODIMM_155", 356 "SODIMM_157", 357 "SODIMM_159", 358 "SODIMM_161", 359 "SODIMM_163", 360 "SODIMM_33", 361 "SODIMM_35", 362 "SODIMM_165", 363 "SODIMM_167"; 364}; 365 366&gpio6 { 367 gpio-line-names = "SODIMM_169", 368 "SODIMM_171", 369 "SODIMM_173", 370 "SODIMM_175", 371 "SODIMM_177", 372 "SODIMM_179", 373 "SODIMM_85", 374 "SODIMM_166", 375 "SODIMM_160", 376 "SODIMM_162", 377 "SODIMM_158", 378 "SODIMM_164", 379 "", 380 "", 381 "SODIMM_156", 382 "SODIMM_75", 383 "SODIMM_154", 384 "", 385 "", 386 "", 387 "", 388 "", 389 "", 390 "", 391 "", 392 "", 393 "", 394 "", 395 "", 396 "", 397 "", 398 "SODIMM_152"; 399}; 400 401&gpio7 { 402 gpio-line-names = "", 403 "", 404 "", 405 "", 406 "", 407 "", 408 "", 409 "", 410 "", 411 "SODIMM_19", 412 "SODIMM_21", 413 "", 414 "SODIMM_137"; 415}; 416 417&hdmi { 418 pinctrl-names = "default"; 419 pinctrl-0 = <&pinctrl_hdmi_ddc>; 420 status = "disabled"; 421}; 422 423/* 424 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 425 * touch screen controller 426 */ 427&i2c2 { 428 clock-frequency = <100000>; 429 pinctrl-names = "default", "gpio"; 430 pinctrl-0 = <&pinctrl_i2c2>; 431 pinctrl-1 = <&pinctrl_i2c2_gpio>; 432 scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 433 sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 434 status = "okay"; 435 436 pmic: pmic@8 { 437 compatible = "fsl,pfuze100"; 438 fsl,pmic-stby-poweroff; 439 reg = <0x08>; 440 441 regulators { 442 sw1a_reg: sw1ab { 443 regulator-always-on; 444 regulator-boot-on; 445 regulator-max-microvolt = <1875000>; 446 regulator-min-microvolt = <300000>; 447 regulator-ramp-delay = <6250>; 448 }; 449 450 sw1c_reg: sw1c { 451 regulator-always-on; 452 regulator-boot-on; 453 regulator-max-microvolt = <1875000>; 454 regulator-min-microvolt = <300000>; 455 regulator-ramp-delay = <6250>; 456 }; 457 458 sw3a_reg: sw3a { 459 regulator-always-on; 460 regulator-boot-on; 461 regulator-max-microvolt = <1975000>; 462 regulator-min-microvolt = <400000>; 463 }; 464 465 swbst_reg: swbst { 466 regulator-always-on; 467 regulator-boot-on; 468 regulator-max-microvolt = <5150000>; 469 regulator-min-microvolt = <5000000>; 470 }; 471 472 snvs_reg: vsnvs { 473 regulator-always-on; 474 regulator-boot-on; 475 regulator-max-microvolt = <3000000>; 476 regulator-min-microvolt = <1000000>; 477 }; 478 479 vref_reg: vrefddr { 480 regulator-always-on; 481 regulator-boot-on; 482 }; 483 484 /* vgen1: unused */ 485 486 vgen2_reg: vgen2 { 487 regulator-always-on; 488 regulator-boot-on; 489 regulator-max-microvolt = <1550000>; 490 regulator-min-microvolt = <800000>; 491 }; 492 493 /* 494 * +V3.3_1.8_SD1 coming off VGEN3 and supplying 495 * the i.MX 6 NVCC_SD1. 496 */ 497 vgen3_reg: vgen3 { 498 regulator-always-on; 499 regulator-boot-on; 500 regulator-max-microvolt = <3300000>; 501 regulator-min-microvolt = <1800000>; 502 }; 503 504 vgen4_reg: vgen4 { 505 regulator-always-on; 506 regulator-boot-on; 507 regulator-max-microvolt = <1800000>; 508 regulator-min-microvolt = <1800000>; 509 }; 510 511 vgen5_reg: vgen5 { 512 regulator-always-on; 513 regulator-boot-on; 514 regulator-max-microvolt = <3300000>; 515 regulator-min-microvolt = <1800000>; 516 }; 517 518 vgen6_reg: vgen6 { 519 regulator-always-on; 520 regulator-boot-on; 521 regulator-max-microvolt = <3300000>; 522 regulator-min-microvolt = <1800000>; 523 }; 524 }; 525 }; 526 527 codec: sgtl5000@a { 528 compatible = "fsl,sgtl5000"; 529 clocks = <&clks IMX6QDL_CLK_CKO>; 530 lrclk-strength = <3>; 531 pinctrl-names = "default"; 532 pinctrl-0 = <&pinctrl_sgtl5000>; 533 reg = <0x0a>; 534 #sound-dai-cells = <0>; 535 VDDA-supply = <®_module_3v3_audio>; 536 VDDIO-supply = <®_module_3v3>; 537 VDDD-supply = <&vgen4_reg>; 538 }; 539 540 /* STMPE811 touch screen controller */ 541 stmpe811@41 { 542 compatible = "st,stmpe811"; 543 blocks = <0x5>; 544 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 545 interrupt-parent = <&gpio6>; 546 id = <0>; 547 irq-trigger = <0x1>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&pinctrl_touch_int>; 550 reg = <0x41>; 551 /* 3.25 MHz ADC clock speed */ 552 st,adc-freq = <1>; 553 /* 12-bit ADC */ 554 st,mod-12b = <1>; 555 /* internal ADC reference */ 556 st,ref-sel = <0>; 557 /* ADC converstion time: 80 clocks */ 558 st,sample-time = <4>; 559 560 stmpe_ts: stmpe_touchscreen { 561 compatible = "st,stmpe-ts"; 562 /* 8 sample average control */ 563 st,ave-ctrl = <3>; 564 /* 7 length fractional part in z */ 565 st,fraction-z = <7>; 566 /* 567 * 50 mA typical 80 mA max touchscreen drivers 568 * current limit value 569 */ 570 st,i-drive = <1>; 571 /* 1 ms panel driver settling time */ 572 st,settling = <3>; 573 /* 5 ms touch detect interrupt delay */ 574 st,touch-det-delay = <5>; 575 status = "disabled"; 576 }; 577 578 stmpe_adc: stmpe_adc { 579 compatible = "st,stmpe-adc"; 580 /* forbid to use ADC channels 3-0 (touch) */ 581 st,norequest-mask = <0x0F>; 582 }; 583 }; 584}; 585 586/* 587 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) 588 */ 589&i2c3 { 590 clock-frequency = <100000>; 591 pinctrl-names = "default", "gpio"; 592 pinctrl-0 = <&pinctrl_i2c3>; 593 pinctrl-1 = <&pinctrl_i2c3_gpio>; 594 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 595 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 596 status = "disabled"; 597 598 atmel_mxt_ts: touchscreen@4a { 599 compatible = "atmel,maxtouch"; 600 interrupt-parent = <&gpio2>; 601 interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ 602 pinctrl-names = "default"; 603 pinctrl-0 = <&pinctrl_atmel_conn>; 604 reg = <0x4a>; 605 reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* SODIMM 106 */ 606 status = "disabled"; 607 }; 608}; 609 610&ipu1_di0_disp0 { 611 remote-endpoint = <&lcd_display_in>; 612}; 613 614/* Colibri PWM<B> */ 615&pwm1 { 616 pinctrl-names = "default"; 617 pinctrl-0 = <&pinctrl_pwm1>; 618 status = "disabled"; 619}; 620 621/* Colibri PWM<D> */ 622&pwm2 { 623 pinctrl-names = "default"; 624 pinctrl-0 = <&pinctrl_pwm2>; 625 status = "disabled"; 626}; 627 628/* Colibri PWM<A> */ 629&pwm3 { 630 pinctrl-names = "default"; 631 pinctrl-0 = <&pinctrl_pwm3>; 632 status = "disabled"; 633}; 634 635/* Colibri PWM<C> */ 636&pwm4 { 637 pinctrl-names = "default"; 638 pinctrl-0 = <&pinctrl_pwm4>; 639 status = "disabled"; 640}; 641 642/* Optional S/PDIF out on SODIMM 137 */ 643&spdif { 644 pinctrl-names = "default"; 645 pinctrl-0 = <&pinctrl_spdif>; 646 status = "disabled"; 647}; 648 649&ssi1 { 650 status = "okay"; 651}; 652 653/* Colibri UART_A */ 654&uart1 { 655 fsl,dte-mode; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 658 uart-has-rtscts; 659 status = "disabled"; 660}; 661 662/* Colibri UART_B */ 663&uart2 { 664 fsl,dte-mode; 665 pinctrl-names = "default"; 666 pinctrl-0 = <&pinctrl_uart2_dte>; 667 uart-has-rtscts; 668 status = "disabled"; 669}; 670 671/* Colibri UART_C */ 672&uart3 { 673 fsl,dte-mode; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&pinctrl_uart3_dte>; 676 status = "disabled"; 677}; 678 679/* Colibri USBH */ 680&usbh1 { 681 vbus-supply = <®_usb_host_vbus>; 682}; 683 684/* Colibri USBC */ 685&usbotg { 686 dr_mode = "otg"; 687 extcon = <0>, <&extcon_usbc_det>; 688 status = "disabled"; 689}; 690 691/* Colibri MMC */ 692&usdhc1 { 693 cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ 694 bus-width = <4>; 695 no-1-8-v; 696 disable-wp; 697 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 698 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; 699 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; 700 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; 701 pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>; 702 vmmc-supply = <®_module_3v3>; 703 vqmmc-supply = <&vgen3_reg>; 704 status = "disabled"; 705}; 706 707/* eMMC */ 708&usdhc3 { 709 bus-width = <8>; 710 no-1-8-v; 711 non-removable; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&pinctrl_usdhc3>; 714 vqmmc-supply = <®_module_3v3>; 715 status = "okay"; 716}; 717 718&weim { 719 pinctrl-names = "default"; 720 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 721 &pinctrl_weim_cs1 &pinctrl_weim_cs2 722 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; 723 #address-cells = <2>; 724 #size-cells = <1>; 725 status = "disabled"; 726}; 727 728&iomuxc { 729 pinctrl-names = "default"; 730 pinctrl-0 = <&pinctrl_usbh_oc_1>; 731 732 /* Atmel MXT touchsceen + Capacitive Touch Adapter */ 733 /* NOTE: This pin group conflicts with pin groups 734 * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously. 735 */ 736 pinctrl_atmel_adap: atmeladaptergrp { 737 fsl,pins = < 738 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */ 739 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */ 740 >; 741 }; 742 743 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ 744 /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and 745 * pinctrl_weim_cs2. Don't use them simultaneously. 746 */ 747 pinctrl_atmel_conn: atmelconnectorgrp { 748 fsl,pins = < 749 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */ 750 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */ 751 >; 752 }; 753 754 pinctrl_audmux: audmuxgrp { 755 fsl,pins = < 756 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 757 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 758 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 759 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 760 >; 761 }; 762 763 pinctrl_cam_mclk: cammclkgrp { 764 fsl,pins = < 765 /* Parallel Camera CAM sys_mclk */ 766 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 767 >; 768 }; 769 770 /* CSI pins used as GPIOs */ 771 pinctrl_csi_gpio_1: csigpio1grp { 772 fsl,pins = < 773 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 774 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 775 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 776 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 777 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 778 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 779 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 780 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 781 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 782 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 783 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 784 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 785 >; 786 }; 787 788 pinctrl_csi_gpio_2: csigpio2grp { 789 fsl,pins = < 790 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 791 >; 792 }; 793 794 pinctrl_ecspi4: ecspi4grp { 795 fsl,pins = < 796 /* SPI CS */ 797 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 798 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 799 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 800 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 801 >; 802 }; 803 804 pinctrl_enet: enetgrp { 805 fsl,pins = < 806 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 807 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 808 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 809 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 810 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 811 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 812 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 813 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 814 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 815 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) 816 >; 817 }; 818 819 pinctrl_flexcan1: flexcan1grp { 820 fsl,pins = < 821 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 822 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 823 >; 824 }; 825 826 pinctrl_flexcan2: flexcan2grp { 827 fsl,pins = < 828 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 829 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 830 >; 831 }; 832 833 pinctrl_gpio_1: gpio1grp { 834 fsl,pins = < 835 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 836 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 837 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 838 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 839 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 840 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 841 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 842 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 843 >; 844 }; 845 pinctrl_gpio_2: gpio2grp { 846 fsl,pins = < 847 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 848 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 849 >; 850 }; 851 852 pinctrl_gpio_bl_on: gpioblongrp { 853 fsl,pins = < 854 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 855 >; 856 }; 857 858 pinctrl_gpio_keys: gpiokeysgrp { 859 fsl,pins = < 860 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 861 >; 862 }; 863 864 pinctrl_hdmi_ddc: hdmiddcgrp { 865 fsl,pins = < 866 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 867 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 868 >; 869 }; 870 871 pinctrl_i2c2: i2c2grp { 872 fsl,pins = < 873 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 874 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 875 >; 876 }; 877 878 pinctrl_i2c2_gpio: i2c2gpiogrp { 879 fsl,pins = < 880 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 881 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 882 >; 883 }; 884 885 pinctrl_i2c3: i2c3grp { 886 fsl,pins = < 887 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 888 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 889 >; 890 }; 891 892 pinctrl_i2c3_gpio: i2c3gpiogrp { 893 fsl,pins = < 894 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 895 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 896 >; 897 }; 898 899 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ 900 fsl,pins = < 901 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 902 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 903 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 904 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 905 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 906 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 907 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 908 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 909 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 910 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 911 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 912 /* Disable PWM pins on camera interface */ 913 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 914 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 915 >; 916 }; 917 918 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 919 fsl,pins = < 920 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 921 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 922 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 923 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 924 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 925 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 926 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 927 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 928 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 929 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 930 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 931 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 932 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 933 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 934 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 935 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 936 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 937 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 938 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 939 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 940 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 941 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 942 >; 943 }; 944 945 pinctrl_lvds_transceiver: lvdstxgrp { 946 fsl,pins = < 947 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */ 948 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */ 949 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */ 950 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */ 951 >; 952 }; 953 954 pinctrl_mic_gnd: micgndgrp { 955 fsl,pins = < 956 /* Controls Mic GND, PU or '1' pull Mic GND to GND */ 957 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 958 >; 959 }; 960 961 pinctrl_mmc_cd: mmccdgrp { 962 fsl,pins = < 963 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 964 >; 965 }; 966 967 pinctrl_mmc_cd_sleep: mmccdslpgrp { 968 fsl,pins = < 969 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0 970 >; 971 }; 972 973 pinctrl_pwm1: pwm1grp { 974 fsl,pins = < 975 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 976 >; 977 }; 978 979 pinctrl_pwm2: pwm2grp { 980 fsl,pins = < 981 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 982 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 983 >; 984 }; 985 986 pinctrl_pwm3: pwm3grp { 987 fsl,pins = < 988 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 989 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 990 >; 991 }; 992 993 pinctrl_pwm4: pwm4grp { 994 fsl,pins = < 995 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 996 >; 997 }; 998 999 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { 1000 fsl,pins = < 1001 /* SODIMM 129 / USBH_PEN */ 1002 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 1003 >; 1004 }; 1005 1006 pinctrl_sgtl5000: sgtl5000grp { 1007 fsl,pins = < 1008 /* SGTL5000 sys_mclk */ 1009 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 1010 >; 1011 }; 1012 1013 pinctrl_spdif: spdifgrp { 1014 fsl,pins = < 1015 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 1016 >; 1017 }; 1018 1019 pinctrl_touch_int: gpiotouchintgrp { 1020 fsl,pins = < 1021 /* STMPE811 interrupt */ 1022 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 1023 >; 1024 }; 1025 1026 pinctrl_uart1_dce: uart1dcegrp { 1027 fsl,pins = < 1028 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 1029 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 1030 >; 1031 }; 1032 1033 /* DTE mode */ 1034 pinctrl_uart1_dte: uart1dtegrp { 1035 fsl,pins = < 1036 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 1037 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 1038 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 1039 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 1040 >; 1041 }; 1042 1043 /* Additional DTR, DSR, DCD */ 1044 pinctrl_uart1_ctrl: uart1ctrlgrp { 1045 fsl,pins = < 1046 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 1047 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 1048 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 1049 >; 1050 }; 1051 1052 pinctrl_uart2_dte: uart2dtegrp { 1053 fsl,pins = < 1054 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 1055 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 1056 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 1057 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 1058 >; 1059 }; 1060 1061 pinctrl_uart3_dte: uart3dtegrp { 1062 fsl,pins = < 1063 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 1064 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 1065 >; 1066 }; 1067 1068 pinctrl_usbc_det: usbcdetgrp { 1069 fsl,pins = < 1070 /* SODIMM 137 / USBC_DET */ 1071 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 1072 /* USBC_DET_OVERWRITE */ 1073 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 1074 /* USBC_DET_EN */ 1075 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 1076 >; 1077 }; 1078 1079 pinctrl_usbc_id_1: usbcid1grp { 1080 fsl,pins = < 1081 /* USBC_ID */ 1082 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 1083 >; 1084 }; 1085 1086 pinctrl_usbh_oc_1: usbhoc1grp { 1087 fsl,pins = < 1088 /* USBH_OC */ 1089 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 1090 >; 1091 }; 1092 1093 pinctrl_usdhc1: usdhc1grp { 1094 fsl,pins = < 1095 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 1096 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 1097 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 1098 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 1099 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 1100 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 1101 >; 1102 }; 1103 1104 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1105 fsl,pins = < 1106 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 1107 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 1108 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 1109 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 1110 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 1111 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 1112 >; 1113 }; 1114 1115 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1116 fsl,pins = < 1117 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 1118 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 1119 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 1120 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 1121 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 1122 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 1123 >; 1124 }; 1125 1126 /* avoid backfeeding with removed card power */ 1127 pinctrl_usdhc1_sleep: usdhc1sleepgrp { 1128 fsl,pins = < 1129 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 1130 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 1131 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 1132 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 1133 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 1134 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 1135 >; 1136 }; 1137 1138 pinctrl_usdhc3: usdhc3grp { 1139 fsl,pins = < 1140 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1141 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1142 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1143 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1144 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1145 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1146 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 1147 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 1148 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 1149 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 1150 /* eMMC reset */ 1151 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 1152 >; 1153 }; 1154 1155 pinctrl_weim_cs0: weimcs0grp { 1156 fsl,pins = < 1157 /* nEXT_CS0 */ 1158 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 1159 >; 1160 }; 1161 1162 pinctrl_weim_cs1: weimcs1grp { 1163 fsl,pins = < 1164 /* nEXT_CS1 */ 1165 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 1166 >; 1167 }; 1168 1169 pinctrl_weim_cs2: weimcs2grp { 1170 fsl,pins = < 1171 /* nEXT_CS2 */ 1172 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 1173 >; 1174 }; 1175 1176 /* ADDRESS[16:18] [25] used as GPIO */ 1177 pinctrl_weim_gpio_1: weimgpio1grp { 1178 fsl,pins = < 1179 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 1180 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 1181 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 1182 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 1183 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 1184 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 1185 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1186 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 1187 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 1188 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 1189 >; 1190 }; 1191 1192 /* ADDRESS[19:24] used as GPIO */ 1193 pinctrl_weim_gpio_2: weimgpio2grp { 1194 fsl,pins = < 1195 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 1196 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 1197 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 1198 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 1199 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 1200 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 1201 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1202 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 1203 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 1204 >; 1205 }; 1206 1207 /* DATA[16:31] used as GPIO */ 1208 pinctrl_weim_gpio_3: weimgpio3grp { 1209 fsl,pins = < 1210 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 1211 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 1212 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 1213 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 1214 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 1215 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 1216 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 1217 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 1218 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 1219 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 1220 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 1221 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 1222 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 1223 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 1224 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 1225 >; 1226 }; 1227 1228 /* DQM[0:3] used as GPIO */ 1229 pinctrl_weim_gpio_4: weimgpio4grp { 1230 fsl,pins = < 1231 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 1232 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 1233 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 1234 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 1235 >; 1236 }; 1237 1238 /* RDY used as GPIO */ 1239 pinctrl_weim_gpio_5: weimgpio5grp { 1240 fsl,pins = < 1241 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 1242 >; 1243 }; 1244 1245 /* ADDRESS[16] DATA[30] used as GPIO */ 1246 pinctrl_weim_gpio_6: weimgpio6grp { 1247 fsl,pins = < 1248 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 1249 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 1250 >; 1251 }; 1252 1253 pinctrl_weim_npwe: weimnpwegrp { 1254 fsl,pins = < 1255 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 1256 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 1257 >; 1258 }; 1259 1260 pinctrl_weim_sram: weimsramgrp { 1261 fsl,pins = < 1262 /* Data */ 1263 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 1264 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 1265 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 1266 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 1267 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 1268 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 1269 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 1270 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 1271 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 1272 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 1273 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 1274 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 1275 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 1276 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 1277 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 1278 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 1279 /* Address */ 1280 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 1281 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 1282 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 1283 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 1284 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 1285 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 1286 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 1287 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 1288 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 1289 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 1290 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 1291 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 1292 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 1293 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 1294 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 1295 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 1296 /* Ctrl */ 1297 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 1298 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 1299 >; 1300 }; 1301 1302 pinctrl_weim_rdnwr: weimrdnwrgrp { 1303 fsl,pins = < 1304 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 1305 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 1306 >; 1307 }; 1308}; 1309