1config ARM 2 bool 3 default y 4 select ARCH_CLOCKSOURCE_DATA 5 select ARCH_HAS_DEBUG_VIRTUAL 6 select ARCH_HAS_DEVMEM_IS_ALLOWED 7 select ARCH_HAS_ELF_RANDOMIZE 8 select ARCH_HAS_SET_MEMORY 9 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 10 select ARCH_HAS_STRICT_MODULE_RWX if MMU 11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 12 select ARCH_HAVE_CUSTOM_GPIO_H 13 select ARCH_HAS_GCOV_PROFILE_ALL 14 select ARCH_MIGHT_HAVE_PC_PARPORT 15 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 16 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 17 select ARCH_SUPPORTS_ATOMIC_RMW 18 select ARCH_USE_BUILTIN_BSWAP 19 select ARCH_USE_CMPXCHG_LOCKREF 20 select ARCH_WANT_IPC_PARSE_VERSION 21 select BUILDTIME_EXTABLE_SORT if MMU 22 select CLONE_BACKWARDS 23 select CPU_PM if (SUSPEND || CPU_IDLE) 24 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 25 select EDAC_SUPPORT 26 select EDAC_ATOMIC_SCRUB 27 select GENERIC_ALLOCATOR 28 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 29 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 30 select GENERIC_CPU_AUTOPROBE 31 select GENERIC_EARLY_IOREMAP 32 select GENERIC_IDLE_POLL_SETUP 33 select GENERIC_IRQ_PROBE 34 select GENERIC_IRQ_SHOW 35 select GENERIC_IRQ_SHOW_LEVEL 36 select GENERIC_PCI_IOMAP 37 select GENERIC_SCHED_CLOCK 38 select GENERIC_SMP_IDLE_THREAD 39 select GENERIC_STRNCPY_FROM_USER 40 select GENERIC_STRNLEN_USER 41 select HANDLE_DOMAIN_IRQ 42 select HARDIRQS_SW_RESEND 43 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 44 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 45 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 46 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 47 select HAVE_ARCH_MMAP_RND_BITS if MMU 48 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 49 select HAVE_ARCH_TRACEHOOK 50 select HAVE_ARM_SMCCC if CPU_V7 51 select HAVE_CBPF_JIT 52 select HAVE_CC_STACKPROTECTOR 53 select HAVE_CONTEXT_TRACKING 54 select HAVE_C_RECORDMCOUNT 55 select HAVE_DEBUG_KMEMLEAK 56 select HAVE_DMA_API_DEBUG 57 select HAVE_DMA_CONTIGUOUS if MMU 58 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU 59 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 60 select HAVE_EXIT_THREAD 61 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 62 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 63 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 64 select HAVE_GCC_PLUGINS 65 select HAVE_GENERIC_DMA_COHERENT 66 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 67 select HAVE_IDE if PCI || ISA || PCMCIA 68 select HAVE_IRQ_TIME_ACCOUNTING 69 select HAVE_KERNEL_GZIP 70 select HAVE_KERNEL_LZ4 71 select HAVE_KERNEL_LZMA 72 select HAVE_KERNEL_LZO 73 select HAVE_KERNEL_XZ 74 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 75 select HAVE_KRETPROBES if (HAVE_KPROBES) 76 select HAVE_MEMBLOCK 77 select HAVE_MOD_ARCH_SPECIFIC 78 select HAVE_NMI 79 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 80 select HAVE_OPTPROBES if !THUMB2_KERNEL 81 select HAVE_PERF_EVENTS 82 select HAVE_PERF_REGS 83 select HAVE_PERF_USER_STACK_DUMP 84 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 85 select HAVE_REGS_AND_STACK_ACCESS_API 86 select HAVE_SYSCALL_TRACEPOINTS 87 select HAVE_UID16 88 select HAVE_VIRT_CPU_ACCOUNTING_GEN 89 select IRQ_FORCED_THREADING 90 select MODULES_USE_ELF_REL 91 select NO_BOOTMEM 92 select OF_EARLY_FLATTREE if OF 93 select OF_RESERVED_MEM if OF 94 select OLD_SIGACTION 95 select OLD_SIGSUSPEND3 96 select PERF_USE_VMALLOC 97 select RTC_LIB 98 select SYS_SUPPORTS_APM_EMULATION 99 # Above selects are sorted alphabetically; please add new ones 100 # according to that. Thanks. 101 help 102 The ARM series is a line of low-power-consumption RISC chip designs 103 licensed by ARM Ltd and targeted at embedded applications and 104 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 105 manufactured, but legacy ARM-based PC hardware remains popular in 106 Europe. There is an ARM Linux project with a web page at 107 <http://www.arm.linux.org.uk/>. 108 109config ARM_HAS_SG_CHAIN 110 select ARCH_HAS_SG_CHAIN 111 bool 112 113config NEED_SG_DMA_LENGTH 114 bool 115 116config ARM_DMA_USE_IOMMU 117 bool 118 select ARM_HAS_SG_CHAIN 119 select NEED_SG_DMA_LENGTH 120 121if ARM_DMA_USE_IOMMU 122 123config ARM_DMA_IOMMU_ALIGNMENT 124 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 125 range 4 9 126 default 8 127 help 128 DMA mapping framework by default aligns all buffers to the smallest 129 PAGE_SIZE order which is greater than or equal to the requested buffer 130 size. This works well for buffers up to a few hundreds kilobytes, but 131 for larger buffers it just a waste of address space. Drivers which has 132 relatively small addressing window (like 64Mib) might run out of 133 virtual space with just a few allocations. 134 135 With this parameter you can specify the maximum PAGE_SIZE order for 136 DMA IOMMU buffers. Larger buffers will be aligned only to this 137 specified order. The order is expressed as a power of two multiplied 138 by the PAGE_SIZE. 139 140endif 141 142config MIGHT_HAVE_PCI 143 bool 144 145config SYS_SUPPORTS_APM_EMULATION 146 bool 147 148config HAVE_TCM 149 bool 150 select GENERIC_ALLOCATOR 151 152config HAVE_PROC_CPU 153 bool 154 155config NO_IOPORT_MAP 156 bool 157 158config EISA 159 bool 160 ---help--- 161 The Extended Industry Standard Architecture (EISA) bus was 162 developed as an open alternative to the IBM MicroChannel bus. 163 164 The EISA bus provided some of the features of the IBM MicroChannel 165 bus while maintaining backward compatibility with cards made for 166 the older ISA bus. The EISA bus saw limited use between 1988 and 167 1995 when it was made obsolete by the PCI bus. 168 169 Say Y here if you are building a kernel for an EISA-based machine. 170 171 Otherwise, say N. 172 173config SBUS 174 bool 175 176config STACKTRACE_SUPPORT 177 bool 178 default y 179 180config LOCKDEP_SUPPORT 181 bool 182 default y 183 184config TRACE_IRQFLAGS_SUPPORT 185 bool 186 default !CPU_V7M 187 188config RWSEM_XCHGADD_ALGORITHM 189 bool 190 default y 191 192config ARCH_HAS_ILOG2_U32 193 bool 194 195config ARCH_HAS_ILOG2_U64 196 bool 197 198config ARCH_HAS_BANDGAP 199 bool 200 201config FIX_EARLYCON_MEM 202 def_bool y if MMU 203 204config GENERIC_HWEIGHT 205 bool 206 default y 207 208config GENERIC_CALIBRATE_DELAY 209 bool 210 default y 211 212config ARCH_MAY_HAVE_PC_FDC 213 bool 214 215config ZONE_DMA 216 bool 217 218config NEED_DMA_MAP_STATE 219 def_bool y 220 221config ARCH_SUPPORTS_UPROBES 222 def_bool y 223 224config ARCH_HAS_DMA_SET_COHERENT_MASK 225 bool 226 227config GENERIC_ISA_DMA 228 bool 229 230config FIQ 231 bool 232 233config NEED_RET_TO_USER 234 bool 235 236config ARCH_MTD_XIP 237 bool 238 239config VECTORS_BASE 240 hex 241 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 242 default DRAM_BASE if REMAP_VECTORS_TO_RAM 243 default 0x00000000 244 help 245 The base address of exception vectors. This must be two pages 246 in size. 247 248config ARM_PATCH_PHYS_VIRT 249 bool "Patch physical to virtual translations at runtime" if EMBEDDED 250 default y 251 depends on !XIP_KERNEL && MMU 252 help 253 Patch phys-to-virt and virt-to-phys translation functions at 254 boot and module load time according to the position of the 255 kernel in system memory. 256 257 This can only be used with non-XIP MMU kernels where the base 258 of physical memory is at a 16MB boundary. 259 260 Only disable this option if you know that you do not require 261 this feature (eg, building a kernel for a single machine) and 262 you need to shrink the kernel to the minimal size. 263 264config NEED_MACH_IO_H 265 bool 266 help 267 Select this when mach/io.h is required to provide special 268 definitions for this platform. The need for mach/io.h should 269 be avoided when possible. 270 271config NEED_MACH_MEMORY_H 272 bool 273 help 274 Select this when mach/memory.h is required to provide special 275 definitions for this platform. The need for mach/memory.h should 276 be avoided when possible. 277 278config PHYS_OFFSET 279 hex "Physical address of main memory" if MMU 280 depends on !ARM_PATCH_PHYS_VIRT 281 default DRAM_BASE if !MMU 282 default 0x00000000 if ARCH_EBSA110 || \ 283 ARCH_FOOTBRIDGE || \ 284 ARCH_INTEGRATOR || \ 285 ARCH_IOP13XX || \ 286 ARCH_KS8695 || \ 287 ARCH_REALVIEW 288 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 289 default 0x20000000 if ARCH_S5PV210 290 default 0xc0000000 if ARCH_SA1100 291 help 292 Please provide the physical address corresponding to the 293 location of main memory in your system. 294 295config GENERIC_BUG 296 def_bool y 297 depends on BUG 298 299config PGTABLE_LEVELS 300 int 301 default 3 if ARM_LPAE 302 default 2 303 304source "init/Kconfig" 305 306source "kernel/Kconfig.freezer" 307 308menu "System Type" 309 310config MMU 311 bool "MMU-based Paged Memory Management Support" 312 default y 313 help 314 Select if you want MMU-based virtualised addressing space 315 support by paged memory management. If unsure, say 'Y'. 316 317config ARCH_MMAP_RND_BITS_MIN 318 default 8 319 320config ARCH_MMAP_RND_BITS_MAX 321 default 14 if PAGE_OFFSET=0x40000000 322 default 15 if PAGE_OFFSET=0x80000000 323 default 16 324 325# 326# The "ARM system type" choice list is ordered alphabetically by option 327# text. Please add new entries in the option alphabetic order. 328# 329choice 330 prompt "ARM system type" 331 default ARM_SINGLE_ARMV7M if !MMU 332 default ARCH_MULTIPLATFORM if MMU 333 334config ARCH_MULTIPLATFORM 335 bool "Allow multiple platforms to be selected" 336 depends on MMU 337 select ARM_HAS_SG_CHAIN 338 select ARM_PATCH_PHYS_VIRT 339 select AUTO_ZRELADDR 340 select CLKSRC_OF 341 select COMMON_CLK 342 select GENERIC_CLOCKEVENTS 343 select MIGHT_HAVE_PCI 344 select MULTI_IRQ_HANDLER 345 select PCI_DOMAINS if PCI 346 select SPARSE_IRQ 347 select USE_OF 348 349config ARM_SINGLE_ARMV7M 350 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 351 depends on !MMU 352 select ARM_NVIC 353 select AUTO_ZRELADDR 354 select CLKSRC_OF 355 select COMMON_CLK 356 select CPU_V7M 357 select GENERIC_CLOCKEVENTS 358 select NO_IOPORT_MAP 359 select SPARSE_IRQ 360 select USE_OF 361 362config ARCH_GEMINI 363 bool "Cortina Systems Gemini" 364 select CLKSRC_MMIO 365 select CPU_FA526 366 select GENERIC_CLOCKEVENTS 367 select GPIOLIB 368 help 369 Support for the Cortina Systems Gemini family SoCs 370 371config ARCH_EBSA110 372 bool "EBSA-110" 373 select ARCH_USES_GETTIMEOFFSET 374 select CPU_SA110 375 select ISA 376 select NEED_MACH_IO_H 377 select NEED_MACH_MEMORY_H 378 select NO_IOPORT_MAP 379 help 380 This is an evaluation board for the StrongARM processor available 381 from Digital. It has limited hardware on-board, including an 382 Ethernet interface, two PCMCIA sockets, two serial ports and a 383 parallel port. 384 385config ARCH_EP93XX 386 bool "EP93xx-based" 387 select ARCH_HAS_HOLES_MEMORYMODEL 388 select ARM_AMBA 389 select ARM_PATCH_PHYS_VIRT 390 select ARM_VIC 391 select AUTO_ZRELADDR 392 select CLKDEV_LOOKUP 393 select CLKSRC_MMIO 394 select CPU_ARM920T 395 select GENERIC_CLOCKEVENTS 396 select GPIOLIB 397 help 398 This enables support for the Cirrus EP93xx series of CPUs. 399 400config ARCH_FOOTBRIDGE 401 bool "FootBridge" 402 select CPU_SA110 403 select FOOTBRIDGE 404 select GENERIC_CLOCKEVENTS 405 select HAVE_IDE 406 select NEED_MACH_IO_H if !MMU 407 select NEED_MACH_MEMORY_H 408 help 409 Support for systems based on the DC21285 companion chip 410 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 411 412config ARCH_NETX 413 bool "Hilscher NetX based" 414 select ARM_VIC 415 select CLKSRC_MMIO 416 select CPU_ARM926T 417 select GENERIC_CLOCKEVENTS 418 help 419 This enables support for systems based on the Hilscher NetX Soc 420 421config ARCH_IOP13XX 422 bool "IOP13xx-based" 423 depends on MMU 424 select CPU_XSC3 425 select NEED_MACH_MEMORY_H 426 select NEED_RET_TO_USER 427 select PCI 428 select PLAT_IOP 429 select VMSPLIT_1G 430 select SPARSE_IRQ 431 help 432 Support for Intel's IOP13XX (XScale) family of processors. 433 434config ARCH_IOP32X 435 bool "IOP32x-based" 436 depends on MMU 437 select CPU_XSCALE 438 select GPIO_IOP 439 select GPIOLIB 440 select NEED_RET_TO_USER 441 select PCI 442 select PLAT_IOP 443 help 444 Support for Intel's 80219 and IOP32X (XScale) family of 445 processors. 446 447config ARCH_IOP33X 448 bool "IOP33x-based" 449 depends on MMU 450 select CPU_XSCALE 451 select GPIO_IOP 452 select GPIOLIB 453 select NEED_RET_TO_USER 454 select PCI 455 select PLAT_IOP 456 help 457 Support for Intel's IOP33X (XScale) family of processors. 458 459config ARCH_IXP4XX 460 bool "IXP4xx-based" 461 depends on MMU 462 select ARCH_HAS_DMA_SET_COHERENT_MASK 463 select ARCH_SUPPORTS_BIG_ENDIAN 464 select CLKSRC_MMIO 465 select CPU_XSCALE 466 select DMABOUNCE if PCI 467 select GENERIC_CLOCKEVENTS 468 select GPIOLIB 469 select MIGHT_HAVE_PCI 470 select NEED_MACH_IO_H 471 select USB_EHCI_BIG_ENDIAN_DESC 472 select USB_EHCI_BIG_ENDIAN_MMIO 473 help 474 Support for Intel's IXP4XX (XScale) family of processors. 475 476config ARCH_DOVE 477 bool "Marvell Dove" 478 select CPU_PJ4 479 select GENERIC_CLOCKEVENTS 480 select GPIOLIB 481 select MIGHT_HAVE_PCI 482 select MULTI_IRQ_HANDLER 483 select MVEBU_MBUS 484 select PINCTRL 485 select PINCTRL_DOVE 486 select PLAT_ORION_LEGACY 487 select SPARSE_IRQ 488 select PM_GENERIC_DOMAINS if PM 489 help 490 Support for the Marvell Dove SoC 88AP510 491 492config ARCH_KS8695 493 bool "Micrel/Kendin KS8695" 494 select CLKSRC_MMIO 495 select CPU_ARM922T 496 select GENERIC_CLOCKEVENTS 497 select GPIOLIB 498 select NEED_MACH_MEMORY_H 499 help 500 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 501 System-on-Chip devices. 502 503config ARCH_W90X900 504 bool "Nuvoton W90X900 CPU" 505 select CLKDEV_LOOKUP 506 select CLKSRC_MMIO 507 select CPU_ARM926T 508 select GENERIC_CLOCKEVENTS 509 select GPIOLIB 510 help 511 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 512 At present, the w90x900 has been renamed nuc900, regarding 513 the ARM series product line, you can login the following 514 link address to know more. 515 516 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 517 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 518 519config ARCH_LPC32XX 520 bool "NXP LPC32XX" 521 select ARM_AMBA 522 select CLKDEV_LOOKUP 523 select CLKSRC_LPC32XX 524 select COMMON_CLK 525 select CPU_ARM926T 526 select GENERIC_CLOCKEVENTS 527 select GPIOLIB 528 select MULTI_IRQ_HANDLER 529 select SPARSE_IRQ 530 select USE_OF 531 help 532 Support for the NXP LPC32XX family of processors 533 534config ARCH_PXA 535 bool "PXA2xx/PXA3xx-based" 536 depends on MMU 537 select ARCH_MTD_XIP 538 select ARM_CPU_SUSPEND if PM 539 select AUTO_ZRELADDR 540 select COMMON_CLK 541 select CLKDEV_LOOKUP 542 select CLKSRC_PXA 543 select CLKSRC_MMIO 544 select CLKSRC_OF 545 select CPU_XSCALE if !CPU_XSC3 546 select GENERIC_CLOCKEVENTS 547 select GPIO_PXA 548 select GPIOLIB 549 select HAVE_IDE 550 select IRQ_DOMAIN 551 select MULTI_IRQ_HANDLER 552 select PLAT_PXA 553 select SPARSE_IRQ 554 help 555 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 556 557config ARCH_RPC 558 bool "RiscPC" 559 depends on MMU 560 select ARCH_ACORN 561 select ARCH_MAY_HAVE_PC_FDC 562 select ARCH_SPARSEMEM_ENABLE 563 select ARCH_USES_GETTIMEOFFSET 564 select CPU_SA110 565 select FIQ 566 select HAVE_IDE 567 select HAVE_PATA_PLATFORM 568 select ISA_DMA_API 569 select NEED_MACH_IO_H 570 select NEED_MACH_MEMORY_H 571 select NO_IOPORT_MAP 572 help 573 On the Acorn Risc-PC, Linux can support the internal IDE disk and 574 CD-ROM interface, serial and parallel port, and the floppy drive. 575 576config ARCH_SA1100 577 bool "SA1100-based" 578 select ARCH_MTD_XIP 579 select ARCH_SPARSEMEM_ENABLE 580 select CLKDEV_LOOKUP 581 select CLKSRC_MMIO 582 select CLKSRC_PXA 583 select CLKSRC_OF if OF 584 select CPU_FREQ 585 select CPU_SA1100 586 select GENERIC_CLOCKEVENTS 587 select GPIOLIB 588 select HAVE_IDE 589 select IRQ_DOMAIN 590 select ISA 591 select MULTI_IRQ_HANDLER 592 select NEED_MACH_MEMORY_H 593 select SPARSE_IRQ 594 help 595 Support for StrongARM 11x0 based boards. 596 597config ARCH_S3C24XX 598 bool "Samsung S3C24XX SoCs" 599 select ATAGS 600 select CLKDEV_LOOKUP 601 select CLKSRC_SAMSUNG_PWM 602 select GENERIC_CLOCKEVENTS 603 select GPIO_SAMSUNG 604 select GPIOLIB 605 select HAVE_S3C2410_I2C if I2C 606 select HAVE_S3C2410_WATCHDOG if WATCHDOG 607 select HAVE_S3C_RTC if RTC_CLASS 608 select MULTI_IRQ_HANDLER 609 select NEED_MACH_IO_H 610 select SAMSUNG_ATAGS 611 help 612 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 613 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 614 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 615 Samsung SMDK2410 development board (and derivatives). 616 617config ARCH_DAVINCI 618 bool "TI DaVinci" 619 select ARCH_HAS_HOLES_MEMORYMODEL 620 select CLKDEV_LOOKUP 621 select CPU_ARM926T 622 select GENERIC_ALLOCATOR 623 select GENERIC_CLOCKEVENTS 624 select GENERIC_IRQ_CHIP 625 select GPIOLIB 626 select HAVE_IDE 627 select USE_OF 628 select ZONE_DMA 629 help 630 Support for TI's DaVinci platform. 631 632config ARCH_OMAP1 633 bool "TI OMAP1" 634 depends on MMU 635 select ARCH_HAS_HOLES_MEMORYMODEL 636 select ARCH_OMAP 637 select CLKDEV_LOOKUP 638 select CLKSRC_MMIO 639 select GENERIC_CLOCKEVENTS 640 select GENERIC_IRQ_CHIP 641 select GPIOLIB 642 select HAVE_IDE 643 select IRQ_DOMAIN 644 select MULTI_IRQ_HANDLER 645 select NEED_MACH_IO_H if PCCARD 646 select NEED_MACH_MEMORY_H 647 select SPARSE_IRQ 648 help 649 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 650 651endchoice 652 653menu "Multiple platform selection" 654 depends on ARCH_MULTIPLATFORM 655 656comment "CPU Core family selection" 657 658config ARCH_MULTI_V4 659 bool "ARMv4 based platforms (FA526)" 660 depends on !ARCH_MULTI_V6_V7 661 select ARCH_MULTI_V4_V5 662 select CPU_FA526 663 664config ARCH_MULTI_V4T 665 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 666 depends on !ARCH_MULTI_V6_V7 667 select ARCH_MULTI_V4_V5 668 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 669 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 670 CPU_ARM925T || CPU_ARM940T) 671 672config ARCH_MULTI_V5 673 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 674 depends on !ARCH_MULTI_V6_V7 675 select ARCH_MULTI_V4_V5 676 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 677 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 678 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 679 680config ARCH_MULTI_V4_V5 681 bool 682 683config ARCH_MULTI_V6 684 bool "ARMv6 based platforms (ARM11)" 685 select ARCH_MULTI_V6_V7 686 select CPU_V6K 687 688config ARCH_MULTI_V7 689 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 690 default y 691 select ARCH_MULTI_V6_V7 692 select CPU_V7 693 select HAVE_SMP 694 695config ARCH_MULTI_V6_V7 696 bool 697 select MIGHT_HAVE_CACHE_L2X0 698 699config ARCH_MULTI_CPU_AUTO 700 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 701 select ARCH_MULTI_V5 702 703endmenu 704 705config ARCH_VIRT 706 bool "Dummy Virtual Machine" 707 depends on ARCH_MULTI_V7 708 select ARM_AMBA 709 select ARM_GIC 710 select ARM_GIC_V2M if PCI 711 select ARM_GIC_V3 712 select ARM_GIC_V3_ITS if PCI 713 select ARM_PSCI 714 select HAVE_ARM_ARCH_TIMER 715 716# 717# This is sorted alphabetically by mach-* pathname. However, plat-* 718# Kconfigs may be included either alphabetically (according to the 719# plat- suffix) or along side the corresponding mach-* source. 720# 721source "arch/arm/mach-mvebu/Kconfig" 722 723source "arch/arm/mach-alpine/Kconfig" 724 725source "arch/arm/mach-artpec/Kconfig" 726 727source "arch/arm/mach-asm9260/Kconfig" 728 729source "arch/arm/mach-at91/Kconfig" 730 731source "arch/arm/mach-axxia/Kconfig" 732 733source "arch/arm/mach-bcm/Kconfig" 734 735source "arch/arm/mach-berlin/Kconfig" 736 737source "arch/arm/mach-clps711x/Kconfig" 738 739source "arch/arm/mach-cns3xxx/Kconfig" 740 741source "arch/arm/mach-davinci/Kconfig" 742 743source "arch/arm/mach-digicolor/Kconfig" 744 745source "arch/arm/mach-dove/Kconfig" 746 747source "arch/arm/mach-ep93xx/Kconfig" 748 749source "arch/arm/mach-footbridge/Kconfig" 750 751source "arch/arm/mach-gemini/Kconfig" 752 753source "arch/arm/mach-highbank/Kconfig" 754 755source "arch/arm/mach-hisi/Kconfig" 756 757source "arch/arm/mach-integrator/Kconfig" 758 759source "arch/arm/mach-iop32x/Kconfig" 760 761source "arch/arm/mach-iop33x/Kconfig" 762 763source "arch/arm/mach-iop13xx/Kconfig" 764 765source "arch/arm/mach-ixp4xx/Kconfig" 766 767source "arch/arm/mach-keystone/Kconfig" 768 769source "arch/arm/mach-ks8695/Kconfig" 770 771source "arch/arm/mach-meson/Kconfig" 772 773source "arch/arm/mach-moxart/Kconfig" 774 775source "arch/arm/mach-aspeed/Kconfig" 776 777source "arch/arm/mach-mv78xx0/Kconfig" 778 779source "arch/arm/mach-imx/Kconfig" 780 781source "arch/arm/mach-mediatek/Kconfig" 782 783source "arch/arm/mach-mxs/Kconfig" 784 785source "arch/arm/mach-netx/Kconfig" 786 787source "arch/arm/mach-nomadik/Kconfig" 788 789source "arch/arm/mach-nspire/Kconfig" 790 791source "arch/arm/plat-omap/Kconfig" 792 793source "arch/arm/mach-omap1/Kconfig" 794 795source "arch/arm/mach-omap2/Kconfig" 796 797source "arch/arm/mach-orion5x/Kconfig" 798 799source "arch/arm/mach-picoxcell/Kconfig" 800 801source "arch/arm/mach-pxa/Kconfig" 802source "arch/arm/plat-pxa/Kconfig" 803 804source "arch/arm/mach-mmp/Kconfig" 805 806source "arch/arm/mach-oxnas/Kconfig" 807 808source "arch/arm/mach-qcom/Kconfig" 809 810source "arch/arm/mach-realview/Kconfig" 811 812source "arch/arm/mach-rockchip/Kconfig" 813 814source "arch/arm/mach-sa1100/Kconfig" 815 816source "arch/arm/mach-socfpga/Kconfig" 817 818source "arch/arm/mach-spear/Kconfig" 819 820source "arch/arm/mach-sti/Kconfig" 821 822source "arch/arm/mach-s3c24xx/Kconfig" 823 824source "arch/arm/mach-s3c64xx/Kconfig" 825 826source "arch/arm/mach-s5pv210/Kconfig" 827 828source "arch/arm/mach-exynos/Kconfig" 829source "arch/arm/plat-samsung/Kconfig" 830 831source "arch/arm/mach-shmobile/Kconfig" 832 833source "arch/arm/mach-sunxi/Kconfig" 834 835source "arch/arm/mach-prima2/Kconfig" 836 837source "arch/arm/mach-tango/Kconfig" 838 839source "arch/arm/mach-tegra/Kconfig" 840 841source "arch/arm/mach-u300/Kconfig" 842 843source "arch/arm/mach-uniphier/Kconfig" 844 845source "arch/arm/mach-ux500/Kconfig" 846 847source "arch/arm/mach-versatile/Kconfig" 848 849source "arch/arm/mach-vexpress/Kconfig" 850source "arch/arm/plat-versatile/Kconfig" 851 852source "arch/arm/mach-vt8500/Kconfig" 853 854source "arch/arm/mach-w90x900/Kconfig" 855 856source "arch/arm/mach-zx/Kconfig" 857 858source "arch/arm/mach-zynq/Kconfig" 859 860# ARMv7-M architecture 861config ARCH_EFM32 862 bool "Energy Micro efm32" 863 depends on ARM_SINGLE_ARMV7M 864 select GPIOLIB 865 help 866 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 867 processors. 868 869config ARCH_LPC18XX 870 bool "NXP LPC18xx/LPC43xx" 871 depends on ARM_SINGLE_ARMV7M 872 select ARCH_HAS_RESET_CONTROLLER 873 select ARM_AMBA 874 select CLKSRC_LPC32XX 875 select PINCTRL 876 help 877 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 878 high performance microcontrollers. 879 880config ARCH_STM32 881 bool "STMicrolectronics STM32" 882 depends on ARM_SINGLE_ARMV7M 883 select ARCH_HAS_RESET_CONTROLLER 884 select ARMV7M_SYSTICK 885 select CLKSRC_STM32 886 select PINCTRL 887 select RESET_CONTROLLER 888 select STM32_EXTI 889 help 890 Support for STMicroelectronics STM32 processors. 891 892config MACH_STM32F429 893 bool "STMicrolectronics STM32F429" 894 depends on ARCH_STM32 895 default y 896 897config MACH_STM32F746 898 bool "STMicrolectronics STM32F746" 899 depends on ARCH_STM32 900 default y 901 902config ARCH_MPS2 903 bool "ARM MPS2 platform" 904 depends on ARM_SINGLE_ARMV7M 905 select ARM_AMBA 906 select CLKSRC_MPS2 907 help 908 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 909 with a range of available cores like Cortex-M3/M4/M7. 910 911 Please, note that depends which Application Note is used memory map 912 for the platform may vary, so adjustment of RAM base might be needed. 913 914# Definitions to make life easier 915config ARCH_ACORN 916 bool 917 918config PLAT_IOP 919 bool 920 select GENERIC_CLOCKEVENTS 921 922config PLAT_ORION 923 bool 924 select CLKSRC_MMIO 925 select COMMON_CLK 926 select GENERIC_IRQ_CHIP 927 select IRQ_DOMAIN 928 929config PLAT_ORION_LEGACY 930 bool 931 select PLAT_ORION 932 933config PLAT_PXA 934 bool 935 936config PLAT_VERSATILE 937 bool 938 939source "arch/arm/firmware/Kconfig" 940 941source arch/arm/mm/Kconfig 942 943config IWMMXT 944 bool "Enable iWMMXt support" 945 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 946 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 947 help 948 Enable support for iWMMXt context switching at run time if 949 running on a CPU that supports it. 950 951config MULTI_IRQ_HANDLER 952 bool 953 help 954 Allow each machine to specify it's own IRQ handler at run time. 955 956if !MMU 957source "arch/arm/Kconfig-nommu" 958endif 959 960config PJ4B_ERRATA_4742 961 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 962 depends on CPU_PJ4B && MACH_ARMADA_370 963 default y 964 help 965 When coming out of either a Wait for Interrupt (WFI) or a Wait for 966 Event (WFE) IDLE states, a specific timing sensitivity exists between 967 the retiring WFI/WFE instructions and the newly issued subsequent 968 instructions. This sensitivity can result in a CPU hang scenario. 969 Workaround: 970 The software must insert either a Data Synchronization Barrier (DSB) 971 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 972 instruction 973 974config ARM_ERRATA_326103 975 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 976 depends on CPU_V6 977 help 978 Executing a SWP instruction to read-only memory does not set bit 11 979 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 980 treat the access as a read, preventing a COW from occurring and 981 causing the faulting task to livelock. 982 983config ARM_ERRATA_411920 984 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 985 depends on CPU_V6 || CPU_V6K 986 help 987 Invalidation of the Instruction Cache operation can 988 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 989 It does not affect the MPCore. This option enables the ARM Ltd. 990 recommended workaround. 991 992config ARM_ERRATA_430973 993 bool "ARM errata: Stale prediction on replaced interworking branch" 994 depends on CPU_V7 995 help 996 This option enables the workaround for the 430973 Cortex-A8 997 r1p* erratum. If a code sequence containing an ARM/Thumb 998 interworking branch is replaced with another code sequence at the 999 same virtual address, whether due to self-modifying code or virtual 1000 to physical address re-mapping, Cortex-A8 does not recover from the 1001 stale interworking branch prediction. This results in Cortex-A8 1002 executing the new code sequence in the incorrect ARM or Thumb state. 1003 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1004 and also flushes the branch target cache at every context switch. 1005 Note that setting specific bits in the ACTLR register may not be 1006 available in non-secure mode. 1007 1008config ARM_ERRATA_458693 1009 bool "ARM errata: Processor deadlock when a false hazard is created" 1010 depends on CPU_V7 1011 depends on !ARCH_MULTIPLATFORM 1012 help 1013 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1014 erratum. For very specific sequences of memory operations, it is 1015 possible for a hazard condition intended for a cache line to instead 1016 be incorrectly associated with a different cache line. This false 1017 hazard might then cause a processor deadlock. The workaround enables 1018 the L1 caching of the NEON accesses and disables the PLD instruction 1019 in the ACTLR register. Note that setting specific bits in the ACTLR 1020 register may not be available in non-secure mode. 1021 1022config ARM_ERRATA_460075 1023 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1024 depends on CPU_V7 1025 depends on !ARCH_MULTIPLATFORM 1026 help 1027 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1028 erratum. Any asynchronous access to the L2 cache may encounter a 1029 situation in which recent store transactions to the L2 cache are lost 1030 and overwritten with stale memory contents from external memory. The 1031 workaround disables the write-allocate mode for the L2 cache via the 1032 ACTLR register. Note that setting specific bits in the ACTLR register 1033 may not be available in non-secure mode. 1034 1035config ARM_ERRATA_742230 1036 bool "ARM errata: DMB operation may be faulty" 1037 depends on CPU_V7 && SMP 1038 depends on !ARCH_MULTIPLATFORM 1039 help 1040 This option enables the workaround for the 742230 Cortex-A9 1041 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1042 between two write operations may not ensure the correct visibility 1043 ordering of the two writes. This workaround sets a specific bit in 1044 the diagnostic register of the Cortex-A9 which causes the DMB 1045 instruction to behave as a DSB, ensuring the correct behaviour of 1046 the two writes. 1047 1048config ARM_ERRATA_742231 1049 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1050 depends on CPU_V7 && SMP 1051 depends on !ARCH_MULTIPLATFORM 1052 help 1053 This option enables the workaround for the 742231 Cortex-A9 1054 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1055 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1056 accessing some data located in the same cache line, may get corrupted 1057 data due to bad handling of the address hazard when the line gets 1058 replaced from one of the CPUs at the same time as another CPU is 1059 accessing it. This workaround sets specific bits in the diagnostic 1060 register of the Cortex-A9 which reduces the linefill issuing 1061 capabilities of the processor. 1062 1063config ARM_ERRATA_643719 1064 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1065 depends on CPU_V7 && SMP 1066 default y 1067 help 1068 This option enables the workaround for the 643719 Cortex-A9 (prior to 1069 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1070 register returns zero when it should return one. The workaround 1071 corrects this value, ensuring cache maintenance operations which use 1072 it behave as intended and avoiding data corruption. 1073 1074config ARM_ERRATA_720789 1075 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1076 depends on CPU_V7 1077 help 1078 This option enables the workaround for the 720789 Cortex-A9 (prior to 1079 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1080 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1081 As a consequence of this erratum, some TLB entries which should be 1082 invalidated are not, resulting in an incoherency in the system page 1083 tables. The workaround changes the TLB flushing routines to invalidate 1084 entries regardless of the ASID. 1085 1086config ARM_ERRATA_743622 1087 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1088 depends on CPU_V7 1089 depends on !ARCH_MULTIPLATFORM 1090 help 1091 This option enables the workaround for the 743622 Cortex-A9 1092 (r2p*) erratum. Under very rare conditions, a faulty 1093 optimisation in the Cortex-A9 Store Buffer may lead to data 1094 corruption. This workaround sets a specific bit in the diagnostic 1095 register of the Cortex-A9 which disables the Store Buffer 1096 optimisation, preventing the defect from occurring. This has no 1097 visible impact on the overall performance or power consumption of the 1098 processor. 1099 1100config ARM_ERRATA_751472 1101 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1102 depends on CPU_V7 1103 depends on !ARCH_MULTIPLATFORM 1104 help 1105 This option enables the workaround for the 751472 Cortex-A9 (prior 1106 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1107 completion of a following broadcasted operation if the second 1108 operation is received by a CPU before the ICIALLUIS has completed, 1109 potentially leading to corrupted entries in the cache or TLB. 1110 1111config ARM_ERRATA_754322 1112 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1113 depends on CPU_V7 1114 help 1115 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1116 r3p*) erratum. A speculative memory access may cause a page table walk 1117 which starts prior to an ASID switch but completes afterwards. This 1118 can populate the micro-TLB with a stale entry which may be hit with 1119 the new ASID. This workaround places two dsb instructions in the mm 1120 switching code so that no page table walks can cross the ASID switch. 1121 1122config ARM_ERRATA_754327 1123 bool "ARM errata: no automatic Store Buffer drain" 1124 depends on CPU_V7 && SMP 1125 help 1126 This option enables the workaround for the 754327 Cortex-A9 (prior to 1127 r2p0) erratum. The Store Buffer does not have any automatic draining 1128 mechanism and therefore a livelock may occur if an external agent 1129 continuously polls a memory location waiting to observe an update. 1130 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1131 written polling loops from denying visibility of updates to memory. 1132 1133config ARM_ERRATA_364296 1134 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1135 depends on CPU_V6 1136 help 1137 This options enables the workaround for the 364296 ARM1136 1138 r0p2 erratum (possible cache data corruption with 1139 hit-under-miss enabled). It sets the undocumented bit 31 in 1140 the auxiliary control register and the FI bit in the control 1141 register, thus disabling hit-under-miss without putting the 1142 processor into full low interrupt latency mode. ARM11MPCore 1143 is not affected. 1144 1145config ARM_ERRATA_764369 1146 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1147 depends on CPU_V7 && SMP 1148 help 1149 This option enables the workaround for erratum 764369 1150 affecting Cortex-A9 MPCore with two or more processors (all 1151 current revisions). Under certain timing circumstances, a data 1152 cache line maintenance operation by MVA targeting an Inner 1153 Shareable memory region may fail to proceed up to either the 1154 Point of Coherency or to the Point of Unification of the 1155 system. This workaround adds a DSB instruction before the 1156 relevant cache maintenance functions and sets a specific bit 1157 in the diagnostic control register of the SCU. 1158 1159config ARM_ERRATA_775420 1160 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1161 depends on CPU_V7 1162 help 1163 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1164 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1165 operation aborts with MMU exception, it might cause the processor 1166 to deadlock. This workaround puts DSB before executing ISB if 1167 an abort may occur on cache maintenance. 1168 1169config ARM_ERRATA_798181 1170 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1171 depends on CPU_V7 && SMP 1172 help 1173 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1174 adequately shooting down all use of the old entries. This 1175 option enables the Linux kernel workaround for this erratum 1176 which sends an IPI to the CPUs that are running the same ASID 1177 as the one being invalidated. 1178 1179config ARM_ERRATA_773022 1180 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1181 depends on CPU_V7 1182 help 1183 This option enables the workaround for the 773022 Cortex-A15 1184 (up to r0p4) erratum. In certain rare sequences of code, the 1185 loop buffer may deliver incorrect instructions. This 1186 workaround disables the loop buffer to avoid the erratum. 1187 1188config ARM_ERRATA_818325_852422 1189 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1190 depends on CPU_V7 1191 help 1192 This option enables the workaround for: 1193 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1194 instruction might deadlock. Fixed in r0p1. 1195 - Cortex-A12 852422: Execution of a sequence of instructions might 1196 lead to either a data corruption or a CPU deadlock. Not fixed in 1197 any Cortex-A12 cores yet. 1198 This workaround for all both errata involves setting bit[12] of the 1199 Feature Register. This bit disables an optimisation applied to a 1200 sequence of 2 instructions that use opposing condition codes. 1201 1202config ARM_ERRATA_821420 1203 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1204 depends on CPU_V7 1205 help 1206 This option enables the workaround for the 821420 Cortex-A12 1207 (all revs) erratum. In very rare timing conditions, a sequence 1208 of VMOV to Core registers instructions, for which the second 1209 one is in the shadow of a branch or abort, can lead to a 1210 deadlock when the VMOV instructions are issued out-of-order. 1211 1212config ARM_ERRATA_825619 1213 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1214 depends on CPU_V7 1215 help 1216 This option enables the workaround for the 825619 Cortex-A12 1217 (all revs) erratum. Within rare timing constraints, executing a 1218 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1219 and Device/Strongly-Ordered loads and stores might cause deadlock 1220 1221config ARM_ERRATA_852421 1222 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1223 depends on CPU_V7 1224 help 1225 This option enables the workaround for the 852421 Cortex-A17 1226 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1227 execution of a DMB ST instruction might fail to properly order 1228 stores from GroupA and stores from GroupB. 1229 1230config ARM_ERRATA_852423 1231 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1232 depends on CPU_V7 1233 help 1234 This option enables the workaround for: 1235 - Cortex-A17 852423: Execution of a sequence of instructions might 1236 lead to either a data corruption or a CPU deadlock. Not fixed in 1237 any Cortex-A17 cores yet. 1238 This is identical to Cortex-A12 erratum 852422. It is a separate 1239 config option from the A12 erratum due to the way errata are checked 1240 for and handled. 1241 1242endmenu 1243 1244source "arch/arm/common/Kconfig" 1245 1246menu "Bus support" 1247 1248config ISA 1249 bool 1250 help 1251 Find out whether you have ISA slots on your motherboard. ISA is the 1252 name of a bus system, i.e. the way the CPU talks to the other stuff 1253 inside your box. Other bus systems are PCI, EISA, MicroChannel 1254 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1255 newer boards don't support it. If you have ISA, say Y, otherwise N. 1256 1257# Select ISA DMA controller support 1258config ISA_DMA 1259 bool 1260 select ISA_DMA_API 1261 1262# Select ISA DMA interface 1263config ISA_DMA_API 1264 bool 1265 1266config PCI 1267 bool "PCI support" if MIGHT_HAVE_PCI 1268 help 1269 Find out whether you have a PCI motherboard. PCI is the name of a 1270 bus system, i.e. the way the CPU talks to the other stuff inside 1271 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1272 VESA. If you have PCI, say Y, otherwise N. 1273 1274config PCI_DOMAINS 1275 bool 1276 depends on PCI 1277 1278config PCI_DOMAINS_GENERIC 1279 def_bool PCI_DOMAINS 1280 1281config PCI_NANOENGINE 1282 bool "BSE nanoEngine PCI support" 1283 depends on SA1100_NANOENGINE 1284 help 1285 Enable PCI on the BSE nanoEngine board. 1286 1287config PCI_SYSCALL 1288 def_bool PCI 1289 1290config PCI_HOST_ITE8152 1291 bool 1292 depends on PCI && MACH_ARMCORE 1293 default y 1294 select DMABOUNCE 1295 1296source "drivers/pci/Kconfig" 1297 1298source "drivers/pcmcia/Kconfig" 1299 1300endmenu 1301 1302menu "Kernel Features" 1303 1304config HAVE_SMP 1305 bool 1306 help 1307 This option should be selected by machines which have an SMP- 1308 capable CPU. 1309 1310 The only effect of this option is to make the SMP-related 1311 options available to the user for configuration. 1312 1313config SMP 1314 bool "Symmetric Multi-Processing" 1315 depends on CPU_V6K || CPU_V7 1316 depends on GENERIC_CLOCKEVENTS 1317 depends on HAVE_SMP 1318 depends on MMU || ARM_MPU 1319 select IRQ_WORK 1320 help 1321 This enables support for systems with more than one CPU. If you have 1322 a system with only one CPU, say N. If you have a system with more 1323 than one CPU, say Y. 1324 1325 If you say N here, the kernel will run on uni- and multiprocessor 1326 machines, but will use only one CPU of a multiprocessor machine. If 1327 you say Y here, the kernel will run on many, but not all, 1328 uniprocessor machines. On a uniprocessor machine, the kernel 1329 will run faster if you say N here. 1330 1331 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1332 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1333 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1334 1335 If you don't know what to do here, say N. 1336 1337config SMP_ON_UP 1338 bool "Allow booting SMP kernel on uniprocessor systems" 1339 depends on SMP && !XIP_KERNEL && MMU 1340 default y 1341 help 1342 SMP kernels contain instructions which fail on non-SMP processors. 1343 Enabling this option allows the kernel to modify itself to make 1344 these instructions safe. Disabling it allows about 1K of space 1345 savings. 1346 1347 If you don't know what to do here, say Y. 1348 1349config ARM_CPU_TOPOLOGY 1350 bool "Support cpu topology definition" 1351 depends on SMP && CPU_V7 1352 default y 1353 help 1354 Support ARM cpu topology definition. The MPIDR register defines 1355 affinity between processors which is then used to describe the cpu 1356 topology of an ARM System. 1357 1358config SCHED_MC 1359 bool "Multi-core scheduler support" 1360 depends on ARM_CPU_TOPOLOGY 1361 help 1362 Multi-core scheduler support improves the CPU scheduler's decision 1363 making when dealing with multi-core CPU chips at a cost of slightly 1364 increased overhead in some places. If unsure say N here. 1365 1366config SCHED_SMT 1367 bool "SMT scheduler support" 1368 depends on ARM_CPU_TOPOLOGY 1369 help 1370 Improves the CPU scheduler's decision making when dealing with 1371 MultiThreading at a cost of slightly increased overhead in some 1372 places. If unsure say N here. 1373 1374config HAVE_ARM_SCU 1375 bool 1376 help 1377 This option enables support for the ARM system coherency unit 1378 1379config HAVE_ARM_ARCH_TIMER 1380 bool "Architected timer support" 1381 depends on CPU_V7 1382 select ARM_ARCH_TIMER 1383 select GENERIC_CLOCKEVENTS 1384 help 1385 This option enables support for the ARM architected timer 1386 1387config HAVE_ARM_TWD 1388 bool 1389 select CLKSRC_OF if OF 1390 help 1391 This options enables support for the ARM timer and watchdog unit 1392 1393config MCPM 1394 bool "Multi-Cluster Power Management" 1395 depends on CPU_V7 && SMP 1396 help 1397 This option provides the common power management infrastructure 1398 for (multi-)cluster based systems, such as big.LITTLE based 1399 systems. 1400 1401config MCPM_QUAD_CLUSTER 1402 bool 1403 depends on MCPM 1404 help 1405 To avoid wasting resources unnecessarily, MCPM only supports up 1406 to 2 clusters by default. 1407 Platforms with 3 or 4 clusters that use MCPM must select this 1408 option to allow the additional clusters to be managed. 1409 1410config BIG_LITTLE 1411 bool "big.LITTLE support (Experimental)" 1412 depends on CPU_V7 && SMP 1413 select MCPM 1414 help 1415 This option enables support selections for the big.LITTLE 1416 system architecture. 1417 1418config BL_SWITCHER 1419 bool "big.LITTLE switcher support" 1420 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1421 select CPU_PM 1422 help 1423 The big.LITTLE "switcher" provides the core functionality to 1424 transparently handle transition between a cluster of A15's 1425 and a cluster of A7's in a big.LITTLE system. 1426 1427config BL_SWITCHER_DUMMY_IF 1428 tristate "Simple big.LITTLE switcher user interface" 1429 depends on BL_SWITCHER && DEBUG_KERNEL 1430 help 1431 This is a simple and dummy char dev interface to control 1432 the big.LITTLE switcher core code. It is meant for 1433 debugging purposes only. 1434 1435choice 1436 prompt "Memory split" 1437 depends on MMU 1438 default VMSPLIT_3G 1439 help 1440 Select the desired split between kernel and user memory. 1441 1442 If you are not absolutely sure what you are doing, leave this 1443 option alone! 1444 1445 config VMSPLIT_3G 1446 bool "3G/1G user/kernel split" 1447 config VMSPLIT_3G_OPT 1448 bool "3G/1G user/kernel split (for full 1G low memory)" 1449 config VMSPLIT_2G 1450 bool "2G/2G user/kernel split" 1451 config VMSPLIT_1G 1452 bool "1G/3G user/kernel split" 1453endchoice 1454 1455config PAGE_OFFSET 1456 hex 1457 default PHYS_OFFSET if !MMU 1458 default 0x40000000 if VMSPLIT_1G 1459 default 0x80000000 if VMSPLIT_2G 1460 default 0xB0000000 if VMSPLIT_3G_OPT 1461 default 0xC0000000 1462 1463config NR_CPUS 1464 int "Maximum number of CPUs (2-32)" 1465 range 2 32 1466 depends on SMP 1467 default "4" 1468 1469config HOTPLUG_CPU 1470 bool "Support for hot-pluggable CPUs" 1471 depends on SMP 1472 help 1473 Say Y here to experiment with turning CPUs off and on. CPUs 1474 can be controlled through /sys/devices/system/cpu. 1475 1476config ARM_PSCI 1477 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1478 depends on HAVE_ARM_SMCCC 1479 select ARM_PSCI_FW 1480 help 1481 Say Y here if you want Linux to communicate with system firmware 1482 implementing the PSCI specification for CPU-centric power 1483 management operations described in ARM document number ARM DEN 1484 0022A ("Power State Coordination Interface System Software on 1485 ARM processors"). 1486 1487# The GPIO number here must be sorted by descending number. In case of 1488# a multiplatform kernel, we just want the highest value required by the 1489# selected platforms. 1490config ARCH_NR_GPIO 1491 int 1492 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ 1493 ARCH_ZYNQ 1494 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1495 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1496 default 416 if ARCH_SUNXI 1497 default 392 if ARCH_U8500 1498 default 352 if ARCH_VT8500 1499 default 288 if ARCH_ROCKCHIP 1500 default 264 if MACH_H4700 1501 default 0 1502 help 1503 Maximum number of GPIOs in the system. 1504 1505 If unsure, leave the default value. 1506 1507source kernel/Kconfig.preempt 1508 1509config HZ_FIXED 1510 int 1511 default 200 if ARCH_EBSA110 1512 default 128 if SOC_AT91RM9200 1513 default 0 1514 1515choice 1516 depends on HZ_FIXED = 0 1517 prompt "Timer frequency" 1518 1519config HZ_100 1520 bool "100 Hz" 1521 1522config HZ_200 1523 bool "200 Hz" 1524 1525config HZ_250 1526 bool "250 Hz" 1527 1528config HZ_300 1529 bool "300 Hz" 1530 1531config HZ_500 1532 bool "500 Hz" 1533 1534config HZ_1000 1535 bool "1000 Hz" 1536 1537endchoice 1538 1539config HZ 1540 int 1541 default HZ_FIXED if HZ_FIXED != 0 1542 default 100 if HZ_100 1543 default 200 if HZ_200 1544 default 250 if HZ_250 1545 default 300 if HZ_300 1546 default 500 if HZ_500 1547 default 1000 1548 1549config SCHED_HRTICK 1550 def_bool HIGH_RES_TIMERS 1551 1552config THUMB2_KERNEL 1553 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1554 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1555 default y if CPU_THUMBONLY 1556 select AEABI 1557 select ARM_ASM_UNIFIED 1558 select ARM_UNWIND 1559 help 1560 By enabling this option, the kernel will be compiled in 1561 Thumb-2 mode. A compiler/assembler that understand the unified 1562 ARM-Thumb syntax is needed. 1563 1564 If unsure, say N. 1565 1566config THUMB2_AVOID_R_ARM_THM_JUMP11 1567 bool "Work around buggy Thumb-2 short branch relocations in gas" 1568 depends on THUMB2_KERNEL && MODULES 1569 default y 1570 help 1571 Various binutils versions can resolve Thumb-2 branches to 1572 locally-defined, preemptible global symbols as short-range "b.n" 1573 branch instructions. 1574 1575 This is a problem, because there's no guarantee the final 1576 destination of the symbol, or any candidate locations for a 1577 trampoline, are within range of the branch. For this reason, the 1578 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1579 relocation in modules at all, and it makes little sense to add 1580 support. 1581 1582 The symptom is that the kernel fails with an "unsupported 1583 relocation" error when loading some modules. 1584 1585 Until fixed tools are available, passing 1586 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1587 code which hits this problem, at the cost of a bit of extra runtime 1588 stack usage in some cases. 1589 1590 The problem is described in more detail at: 1591 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1592 1593 Only Thumb-2 kernels are affected. 1594 1595 Unless you are sure your tools don't have this problem, say Y. 1596 1597config ARM_ASM_UNIFIED 1598 bool 1599 1600config ARM_PATCH_IDIV 1601 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1602 depends on CPU_32v7 && !XIP_KERNEL 1603 default y 1604 help 1605 The ARM compiler inserts calls to __aeabi_idiv() and 1606 __aeabi_uidiv() when it needs to perform division on signed 1607 and unsigned integers. Some v7 CPUs have support for the sdiv 1608 and udiv instructions that can be used to implement those 1609 functions. 1610 1611 Enabling this option allows the kernel to modify itself to 1612 replace the first two instructions of these library functions 1613 with the sdiv or udiv plus "bx lr" instructions when the CPU 1614 it is running on supports them. Typically this will be faster 1615 and less power intensive than running the original library 1616 code to do integer division. 1617 1618config AEABI 1619 bool "Use the ARM EABI to compile the kernel" 1620 help 1621 This option allows for the kernel to be compiled using the latest 1622 ARM ABI (aka EABI). This is only useful if you are using a user 1623 space environment that is also compiled with EABI. 1624 1625 Since there are major incompatibilities between the legacy ABI and 1626 EABI, especially with regard to structure member alignment, this 1627 option also changes the kernel syscall calling convention to 1628 disambiguate both ABIs and allow for backward compatibility support 1629 (selected with CONFIG_OABI_COMPAT). 1630 1631 To use this you need GCC version 4.0.0 or later. 1632 1633config OABI_COMPAT 1634 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1635 depends on AEABI && !THUMB2_KERNEL 1636 help 1637 This option preserves the old syscall interface along with the 1638 new (ARM EABI) one. It also provides a compatibility layer to 1639 intercept syscalls that have structure arguments which layout 1640 in memory differs between the legacy ABI and the new ARM EABI 1641 (only for non "thumb" binaries). This option adds a tiny 1642 overhead to all syscalls and produces a slightly larger kernel. 1643 1644 The seccomp filter system will not be available when this is 1645 selected, since there is no way yet to sensibly distinguish 1646 between calling conventions during filtering. 1647 1648 If you know you'll be using only pure EABI user space then you 1649 can say N here. If this option is not selected and you attempt 1650 to execute a legacy ABI binary then the result will be 1651 UNPREDICTABLE (in fact it can be predicted that it won't work 1652 at all). If in doubt say N. 1653 1654config ARCH_HAS_HOLES_MEMORYMODEL 1655 bool 1656 1657config ARCH_SPARSEMEM_ENABLE 1658 bool 1659 1660config ARCH_SPARSEMEM_DEFAULT 1661 def_bool ARCH_SPARSEMEM_ENABLE 1662 1663config ARCH_SELECT_MEMORY_MODEL 1664 def_bool ARCH_SPARSEMEM_ENABLE 1665 1666config HAVE_ARCH_PFN_VALID 1667 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1668 1669config HAVE_GENERIC_RCU_GUP 1670 def_bool y 1671 depends on ARM_LPAE 1672 1673config HIGHMEM 1674 bool "High Memory Support" 1675 depends on MMU 1676 help 1677 The address space of ARM processors is only 4 Gigabytes large 1678 and it has to accommodate user address space, kernel address 1679 space as well as some memory mapped IO. That means that, if you 1680 have a large amount of physical memory and/or IO, not all of the 1681 memory can be "permanently mapped" by the kernel. The physical 1682 memory that is not permanently mapped is called "high memory". 1683 1684 Depending on the selected kernel/user memory split, minimum 1685 vmalloc space and actual amount of RAM, you may not need this 1686 option which should result in a slightly faster kernel. 1687 1688 If unsure, say n. 1689 1690config HIGHPTE 1691 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1692 depends on HIGHMEM 1693 default y 1694 help 1695 The VM uses one page of physical memory for each page table. 1696 For systems with a lot of processes, this can use a lot of 1697 precious low memory, eventually leading to low memory being 1698 consumed by page tables. Setting this option will allow 1699 user-space 2nd level page tables to reside in high memory. 1700 1701config CPU_SW_DOMAIN_PAN 1702 bool "Enable use of CPU domains to implement privileged no-access" 1703 depends on MMU && !ARM_LPAE 1704 default y 1705 help 1706 Increase kernel security by ensuring that normal kernel accesses 1707 are unable to access userspace addresses. This can help prevent 1708 use-after-free bugs becoming an exploitable privilege escalation 1709 by ensuring that magic values (such as LIST_POISON) will always 1710 fault when dereferenced. 1711 1712 CPUs with low-vector mappings use a best-efforts implementation. 1713 Their lower 1MB needs to remain accessible for the vectors, but 1714 the remainder of userspace will become appropriately inaccessible. 1715 1716config HW_PERF_EVENTS 1717 def_bool y 1718 depends on ARM_PMU 1719 1720config SYS_SUPPORTS_HUGETLBFS 1721 def_bool y 1722 depends on ARM_LPAE 1723 1724config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1725 def_bool y 1726 depends on ARM_LPAE 1727 1728config ARCH_WANT_GENERAL_HUGETLB 1729 def_bool y 1730 1731config ARM_MODULE_PLTS 1732 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1733 depends on MODULES 1734 help 1735 Allocate PLTs when loading modules so that jumps and calls whose 1736 targets are too far away for their relative offsets to be encoded 1737 in the instructions themselves can be bounced via veneers in the 1738 module's PLT. This allows modules to be allocated in the generic 1739 vmalloc area after the dedicated module memory area has been 1740 exhausted. The modules will use slightly more memory, but after 1741 rounding up to page size, the actual memory footprint is usually 1742 the same. 1743 1744 Say y if you are getting out of memory errors while loading modules 1745 1746source "mm/Kconfig" 1747 1748config FORCE_MAX_ZONEORDER 1749 int "Maximum zone order" 1750 default "12" if SOC_AM33XX 1751 default "9" if SA1111 || ARCH_EFM32 1752 default "11" 1753 help 1754 The kernel memory allocator divides physically contiguous memory 1755 blocks into "zones", where each zone is a power of two number of 1756 pages. This option selects the largest power of two that the kernel 1757 keeps in the memory allocator. If you need to allocate very large 1758 blocks of physically contiguous memory, then you may need to 1759 increase this value. 1760 1761 This config option is actually maximum order plus one. For example, 1762 a value of 11 means that the largest free memory block is 2^10 pages. 1763 1764config ALIGNMENT_TRAP 1765 bool 1766 depends on CPU_CP15_MMU 1767 default y if !ARCH_EBSA110 1768 select HAVE_PROC_CPU if PROC_FS 1769 help 1770 ARM processors cannot fetch/store information which is not 1771 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1772 address divisible by 4. On 32-bit ARM processors, these non-aligned 1773 fetch/store instructions will be emulated in software if you say 1774 here, which has a severe performance impact. This is necessary for 1775 correct operation of some network protocols. With an IP-only 1776 configuration it is safe to say N, otherwise say Y. 1777 1778config UACCESS_WITH_MEMCPY 1779 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1780 depends on MMU 1781 default y if CPU_FEROCEON 1782 help 1783 Implement faster copy_to_user and clear_user methods for CPU 1784 cores where a 8-word STM instruction give significantly higher 1785 memory write throughput than a sequence of individual 32bit stores. 1786 1787 A possible side effect is a slight increase in scheduling latency 1788 between threads sharing the same address space if they invoke 1789 such copy operations with large buffers. 1790 1791 However, if the CPU data cache is using a write-allocate mode, 1792 this option is unlikely to provide any performance gain. 1793 1794config SECCOMP 1795 bool 1796 prompt "Enable seccomp to safely compute untrusted bytecode" 1797 ---help--- 1798 This kernel feature is useful for number crunching applications 1799 that may need to compute untrusted bytecode during their 1800 execution. By using pipes or other transports made available to 1801 the process as file descriptors supporting the read/write 1802 syscalls, it's possible to isolate those applications in 1803 their own address space using seccomp. Once seccomp is 1804 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1805 and the task is only allowed to execute a few safe syscalls 1806 defined by each seccomp mode. 1807 1808config SWIOTLB 1809 def_bool y 1810 1811config IOMMU_HELPER 1812 def_bool SWIOTLB 1813 1814config PARAVIRT 1815 bool "Enable paravirtualization code" 1816 help 1817 This changes the kernel so it can modify itself when it is run 1818 under a hypervisor, potentially improving performance significantly 1819 over full virtualization. 1820 1821config PARAVIRT_TIME_ACCOUNTING 1822 bool "Paravirtual steal time accounting" 1823 select PARAVIRT 1824 default n 1825 help 1826 Select this option to enable fine granularity task steal time 1827 accounting. Time spent executing other tasks in parallel with 1828 the current vCPU is discounted from the vCPU power. To account for 1829 that, there can be a small performance impact. 1830 1831 If in doubt, say N here. 1832 1833config XEN_DOM0 1834 def_bool y 1835 depends on XEN 1836 1837config XEN 1838 bool "Xen guest support on ARM" 1839 depends on ARM && AEABI && OF 1840 depends on CPU_V7 && !CPU_V6 1841 depends on !GENERIC_ATOMIC64 1842 depends on MMU 1843 select ARCH_DMA_ADDR_T_64BIT 1844 select ARM_PSCI 1845 select SWIOTLB_XEN 1846 select PARAVIRT 1847 help 1848 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1849 1850endmenu 1851 1852menu "Boot options" 1853 1854config USE_OF 1855 bool "Flattened Device Tree support" 1856 select IRQ_DOMAIN 1857 select OF 1858 help 1859 Include support for flattened device tree machine descriptions. 1860 1861config ATAGS 1862 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1863 default y 1864 help 1865 This is the traditional way of passing data to the kernel at boot 1866 time. If you are solely relying on the flattened device tree (or 1867 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1868 to remove ATAGS support from your kernel binary. If unsure, 1869 leave this to y. 1870 1871config DEPRECATED_PARAM_STRUCT 1872 bool "Provide old way to pass kernel parameters" 1873 depends on ATAGS 1874 help 1875 This was deprecated in 2001 and announced to live on for 5 years. 1876 Some old boot loaders still use this way. 1877 1878# Compressed boot loader in ROM. Yes, we really want to ask about 1879# TEXT and BSS so we preserve their values in the config files. 1880config ZBOOT_ROM_TEXT 1881 hex "Compressed ROM boot loader base address" 1882 default "0" 1883 help 1884 The physical address at which the ROM-able zImage is to be 1885 placed in the target. Platforms which normally make use of 1886 ROM-able zImage formats normally set this to a suitable 1887 value in their defconfig file. 1888 1889 If ZBOOT_ROM is not enabled, this has no effect. 1890 1891config ZBOOT_ROM_BSS 1892 hex "Compressed ROM boot loader BSS address" 1893 default "0" 1894 help 1895 The base address of an area of read/write memory in the target 1896 for the ROM-able zImage which must be available while the 1897 decompressor is running. It must be large enough to hold the 1898 entire decompressed kernel plus an additional 128 KiB. 1899 Platforms which normally make use of ROM-able zImage formats 1900 normally set this to a suitable value in their defconfig file. 1901 1902 If ZBOOT_ROM is not enabled, this has no effect. 1903 1904config ZBOOT_ROM 1905 bool "Compressed boot loader in ROM/flash" 1906 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1907 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1908 help 1909 Say Y here if you intend to execute your compressed kernel image 1910 (zImage) directly from ROM or flash. If unsure, say N. 1911 1912config ARM_APPENDED_DTB 1913 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1914 depends on OF 1915 help 1916 With this option, the boot code will look for a device tree binary 1917 (DTB) appended to zImage 1918 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1919 1920 This is meant as a backward compatibility convenience for those 1921 systems with a bootloader that can't be upgraded to accommodate 1922 the documented boot protocol using a device tree. 1923 1924 Beware that there is very little in terms of protection against 1925 this option being confused by leftover garbage in memory that might 1926 look like a DTB header after a reboot if no actual DTB is appended 1927 to zImage. Do not leave this option active in a production kernel 1928 if you don't intend to always append a DTB. Proper passing of the 1929 location into r2 of a bootloader provided DTB is always preferable 1930 to this option. 1931 1932config ARM_ATAG_DTB_COMPAT 1933 bool "Supplement the appended DTB with traditional ATAG information" 1934 depends on ARM_APPENDED_DTB 1935 help 1936 Some old bootloaders can't be updated to a DTB capable one, yet 1937 they provide ATAGs with memory configuration, the ramdisk address, 1938 the kernel cmdline string, etc. Such information is dynamically 1939 provided by the bootloader and can't always be stored in a static 1940 DTB. To allow a device tree enabled kernel to be used with such 1941 bootloaders, this option allows zImage to extract the information 1942 from the ATAG list and store it at run time into the appended DTB. 1943 1944choice 1945 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1946 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1947 1948config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1949 bool "Use bootloader kernel arguments if available" 1950 help 1951 Uses the command-line options passed by the boot loader instead of 1952 the device tree bootargs property. If the boot loader doesn't provide 1953 any, the device tree bootargs property will be used. 1954 1955config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1956 bool "Extend with bootloader kernel arguments" 1957 help 1958 The command-line arguments provided by the boot loader will be 1959 appended to the the device tree bootargs property. 1960 1961endchoice 1962 1963config CMDLINE 1964 string "Default kernel command string" 1965 default "" 1966 help 1967 On some architectures (EBSA110 and CATS), there is currently no way 1968 for the boot loader to pass arguments to the kernel. For these 1969 architectures, you should supply some command-line options at build 1970 time by entering them here. As a minimum, you should specify the 1971 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1972 1973choice 1974 prompt "Kernel command line type" if CMDLINE != "" 1975 default CMDLINE_FROM_BOOTLOADER 1976 depends on ATAGS 1977 1978config CMDLINE_FROM_BOOTLOADER 1979 bool "Use bootloader kernel arguments if available" 1980 help 1981 Uses the command-line options passed by the boot loader. If 1982 the boot loader doesn't provide any, the default kernel command 1983 string provided in CMDLINE will be used. 1984 1985config CMDLINE_EXTEND 1986 bool "Extend bootloader kernel arguments" 1987 help 1988 The command-line arguments provided by the boot loader will be 1989 appended to the default kernel command string. 1990 1991config CMDLINE_FORCE 1992 bool "Always use the default kernel command string" 1993 help 1994 Always use the default kernel command string, even if the boot 1995 loader passes other arguments to the kernel. 1996 This is useful if you cannot or don't want to change the 1997 command-line options your boot loader passes to the kernel. 1998endchoice 1999 2000config XIP_KERNEL 2001 bool "Kernel Execute-In-Place from ROM" 2002 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 2003 help 2004 Execute-In-Place allows the kernel to run from non-volatile storage 2005 directly addressable by the CPU, such as NOR flash. This saves RAM 2006 space since the text section of the kernel is not loaded from flash 2007 to RAM. Read-write sections, such as the data section and stack, 2008 are still copied to RAM. The XIP kernel is not compressed since 2009 it has to run directly from flash, so it will take more space to 2010 store it. The flash address used to link the kernel object files, 2011 and for storing it, is configuration dependent. Therefore, if you 2012 say Y here, you must know the proper physical address where to 2013 store the kernel image depending on your own flash memory usage. 2014 2015 Also note that the make target becomes "make xipImage" rather than 2016 "make zImage" or "make Image". The final kernel binary to put in 2017 ROM memory will be arch/arm/boot/xipImage. 2018 2019 If unsure, say N. 2020 2021config XIP_PHYS_ADDR 2022 hex "XIP Kernel Physical Location" 2023 depends on XIP_KERNEL 2024 default "0x00080000" 2025 help 2026 This is the physical address in your flash memory the kernel will 2027 be linked for and stored to. This address is dependent on your 2028 own flash usage. 2029 2030config KEXEC 2031 bool "Kexec system call (EXPERIMENTAL)" 2032 depends on (!SMP || PM_SLEEP_SMP) 2033 depends on !CPU_V7M 2034 select KEXEC_CORE 2035 help 2036 kexec is a system call that implements the ability to shutdown your 2037 current kernel, and to start another kernel. It is like a reboot 2038 but it is independent of the system firmware. And like a reboot 2039 you can start any kernel with it, not just Linux. 2040 2041 It is an ongoing process to be certain the hardware in a machine 2042 is properly shutdown, so do not be surprised if this code does not 2043 initially work for you. 2044 2045config ATAGS_PROC 2046 bool "Export atags in procfs" 2047 depends on ATAGS && KEXEC 2048 default y 2049 help 2050 Should the atags used to boot the kernel be exported in an "atags" 2051 file in procfs. Useful with kexec. 2052 2053config CRASH_DUMP 2054 bool "Build kdump crash kernel (EXPERIMENTAL)" 2055 help 2056 Generate crash dump after being started by kexec. This should 2057 be normally only set in special crash dump kernels which are 2058 loaded in the main kernel with kexec-tools into a specially 2059 reserved region and then later executed after a crash by 2060 kdump/kexec. The crash dump kernel must be compiled to a 2061 memory address not used by the main kernel 2062 2063 For more details see Documentation/kdump/kdump.txt 2064 2065config AUTO_ZRELADDR 2066 bool "Auto calculation of the decompressed kernel image address" 2067 help 2068 ZRELADDR is the physical address where the decompressed kernel 2069 image will be placed. If AUTO_ZRELADDR is selected, the address 2070 will be determined at run-time by masking the current IP with 2071 0xf8000000. This assumes the zImage being placed in the first 128MB 2072 from start of memory. 2073 2074config EFI_STUB 2075 bool 2076 2077config EFI 2078 bool "UEFI runtime support" 2079 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2080 select UCS2_STRING 2081 select EFI_PARAMS_FROM_FDT 2082 select EFI_STUB 2083 select EFI_ARMSTUB 2084 select EFI_RUNTIME_WRAPPERS 2085 ---help--- 2086 This option provides support for runtime services provided 2087 by UEFI firmware (such as non-volatile variables, realtime 2088 clock, and platform reset). A UEFI stub is also provided to 2089 allow the kernel to be booted as an EFI application. This 2090 is only useful for kernels that may run on systems that have 2091 UEFI firmware. 2092 2093endmenu 2094 2095menu "CPU Power Management" 2096 2097source "drivers/cpufreq/Kconfig" 2098 2099source "drivers/cpuidle/Kconfig" 2100 2101endmenu 2102 2103menu "Floating point emulation" 2104 2105comment "At least one emulation must be selected" 2106 2107config FPE_NWFPE 2108 bool "NWFPE math emulation" 2109 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2110 ---help--- 2111 Say Y to include the NWFPE floating point emulator in the kernel. 2112 This is necessary to run most binaries. Linux does not currently 2113 support floating point hardware so you need to say Y here even if 2114 your machine has an FPA or floating point co-processor podule. 2115 2116 You may say N here if you are going to load the Acorn FPEmulator 2117 early in the bootup. 2118 2119config FPE_NWFPE_XP 2120 bool "Support extended precision" 2121 depends on FPE_NWFPE 2122 help 2123 Say Y to include 80-bit support in the kernel floating-point 2124 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2125 Note that gcc does not generate 80-bit operations by default, 2126 so in most cases this option only enlarges the size of the 2127 floating point emulator without any good reason. 2128 2129 You almost surely want to say N here. 2130 2131config FPE_FASTFPE 2132 bool "FastFPE math emulation (EXPERIMENTAL)" 2133 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2134 ---help--- 2135 Say Y here to include the FAST floating point emulator in the kernel. 2136 This is an experimental much faster emulator which now also has full 2137 precision for the mantissa. It does not support any exceptions. 2138 It is very simple, and approximately 3-6 times faster than NWFPE. 2139 2140 It should be sufficient for most programs. It may be not suitable 2141 for scientific calculations, but you have to check this for yourself. 2142 If you do not feel you need a faster FP emulation you should better 2143 choose NWFPE. 2144 2145config VFP 2146 bool "VFP-format floating point maths" 2147 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2148 help 2149 Say Y to include VFP support code in the kernel. This is needed 2150 if your hardware includes a VFP unit. 2151 2152 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2153 release notes and additional status information. 2154 2155 Say N if your target does not have VFP hardware. 2156 2157config VFPv3 2158 bool 2159 depends on VFP 2160 default y if CPU_V7 2161 2162config NEON 2163 bool "Advanced SIMD (NEON) Extension support" 2164 depends on VFPv3 && CPU_V7 2165 help 2166 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2167 Extension. 2168 2169config KERNEL_MODE_NEON 2170 bool "Support for NEON in kernel mode" 2171 depends on NEON && AEABI 2172 help 2173 Say Y to include support for NEON in kernel mode. 2174 2175endmenu 2176 2177menu "Userspace binary formats" 2178 2179source "fs/Kconfig.binfmt" 2180 2181endmenu 2182 2183menu "Power management options" 2184 2185source "kernel/power/Kconfig" 2186 2187config ARCH_SUSPEND_POSSIBLE 2188 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2189 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2190 def_bool y 2191 2192config ARM_CPU_SUSPEND 2193 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2194 depends on ARCH_SUSPEND_POSSIBLE 2195 2196config ARCH_HIBERNATION_POSSIBLE 2197 bool 2198 depends on MMU 2199 default y if ARCH_SUSPEND_POSSIBLE 2200 2201endmenu 2202 2203source "net/Kconfig" 2204 2205source "drivers/Kconfig" 2206 2207source "drivers/firmware/Kconfig" 2208 2209source "fs/Kconfig" 2210 2211source "arch/arm/Kconfig.debug" 2212 2213source "security/Kconfig" 2214 2215source "crypto/Kconfig" 2216if CRYPTO 2217source "arch/arm/crypto/Kconfig" 2218endif 2219 2220source "lib/Kconfig" 2221 2222source "arch/arm/kvm/Kconfig" 2223