xref: /openbmc/linux/arch/arm/Kconfig (revision e91c2518)
1# SPDX-License-Identifier: GPL-2.0
2config ARM
3	bool
4	default y
5	select ARCH_CLOCKSOURCE_DATA
6	select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID
7	select ARCH_HAS_DEBUG_VIRTUAL
8	select ARCH_HAS_DEVMEM_IS_ALLOWED
9	select ARCH_HAS_ELF_RANDOMIZE
10	select ARCH_HAS_SET_MEMORY
11	select ARCH_HAS_PHYS_TO_DMA
12	select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
13	select ARCH_HAS_STRICT_MODULE_RWX if MMU
14	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
15	select ARCH_HAVE_CUSTOM_GPIO_H
16	select ARCH_HAS_GCOV_PROFILE_ALL
17	select ARCH_MIGHT_HAVE_PC_PARPORT
18	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
19	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
20	select ARCH_SUPPORTS_ATOMIC_RMW
21	select ARCH_USE_BUILTIN_BSWAP
22	select ARCH_USE_CMPXCHG_LOCKREF
23	select ARCH_WANT_IPC_PARSE_VERSION
24	select BUILDTIME_EXTABLE_SORT if MMU
25	select CLONE_BACKWARDS
26	select CPU_PM if (SUSPEND || CPU_IDLE)
27	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
28	select DMA_DIRECT_OPS if !MMU
29	select EDAC_SUPPORT
30	select EDAC_ATOMIC_SCRUB
31	select GENERIC_ALLOCATOR
32	select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
33	select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
34	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
35	select GENERIC_CPU_AUTOPROBE
36	select GENERIC_EARLY_IOREMAP
37	select GENERIC_IDLE_POLL_SETUP
38	select GENERIC_IRQ_PROBE
39	select GENERIC_IRQ_SHOW
40	select GENERIC_IRQ_SHOW_LEVEL
41	select GENERIC_PCI_IOMAP
42	select GENERIC_SCHED_CLOCK
43	select GENERIC_SMP_IDLE_THREAD
44	select GENERIC_STRNCPY_FROM_USER
45	select GENERIC_STRNLEN_USER
46	select HANDLE_DOMAIN_IRQ
47	select HARDIRQS_SW_RESEND
48	select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
49	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
50	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
51	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
52	select HAVE_ARCH_MMAP_RND_BITS if MMU
53	select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
54	select HAVE_ARCH_TRACEHOOK
55	select HAVE_ARM_SMCCC if CPU_V7
56	select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
57	select HAVE_CC_STACKPROTECTOR
58	select HAVE_CONTEXT_TRACKING
59	select HAVE_C_RECORDMCOUNT
60	select HAVE_DEBUG_KMEMLEAK
61	select HAVE_DMA_API_DEBUG
62	select HAVE_DMA_CONTIGUOUS if MMU
63	select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
64	select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
65	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
66	select HAVE_EXIT_THREAD
67	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
68	select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
69	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
70	select HAVE_GCC_PLUGINS
71	select HAVE_GENERIC_DMA_COHERENT
72	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
73	select HAVE_IDE if PCI || ISA || PCMCIA
74	select HAVE_IRQ_TIME_ACCOUNTING
75	select HAVE_KERNEL_GZIP
76	select HAVE_KERNEL_LZ4
77	select HAVE_KERNEL_LZMA
78	select HAVE_KERNEL_LZO
79	select HAVE_KERNEL_XZ
80	select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
81	select HAVE_KRETPROBES if (HAVE_KPROBES)
82	select HAVE_MEMBLOCK
83	select HAVE_MOD_ARCH_SPECIFIC
84	select HAVE_NMI
85	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
86	select HAVE_OPTPROBES if !THUMB2_KERNEL
87	select HAVE_PERF_EVENTS
88	select HAVE_PERF_REGS
89	select HAVE_PERF_USER_STACK_DUMP
90	select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
91	select HAVE_REGS_AND_STACK_ACCESS_API
92	select HAVE_SYSCALL_TRACEPOINTS
93	select HAVE_UID16
94	select HAVE_VIRT_CPU_ACCOUNTING_GEN
95	select IRQ_FORCED_THREADING
96	select MODULES_USE_ELF_REL
97	select NO_BOOTMEM
98	select OF_EARLY_FLATTREE if OF
99	select OF_RESERVED_MEM if OF
100	select OLD_SIGACTION
101	select OLD_SIGSUSPEND3
102	select PERF_USE_VMALLOC
103	select RTC_LIB
104	select SYS_SUPPORTS_APM_EMULATION
105	# Above selects are sorted alphabetically; please add new ones
106	# according to that.  Thanks.
107	help
108	  The ARM series is a line of low-power-consumption RISC chip designs
109	  licensed by ARM Ltd and targeted at embedded applications and
110	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
111	  manufactured, but legacy ARM-based PC hardware remains popular in
112	  Europe.  There is an ARM Linux project with a web page at
113	  <http://www.arm.linux.org.uk/>.
114
115config ARM_HAS_SG_CHAIN
116	select ARCH_HAS_SG_CHAIN
117	bool
118
119config NEED_SG_DMA_LENGTH
120	bool
121
122config ARM_DMA_USE_IOMMU
123	bool
124	select ARM_HAS_SG_CHAIN
125	select NEED_SG_DMA_LENGTH
126
127if ARM_DMA_USE_IOMMU
128
129config ARM_DMA_IOMMU_ALIGNMENT
130	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
131	range 4 9
132	default 8
133	help
134	  DMA mapping framework by default aligns all buffers to the smallest
135	  PAGE_SIZE order which is greater than or equal to the requested buffer
136	  size. This works well for buffers up to a few hundreds kilobytes, but
137	  for larger buffers it just a waste of address space. Drivers which has
138	  relatively small addressing window (like 64Mib) might run out of
139	  virtual space with just a few allocations.
140
141	  With this parameter you can specify the maximum PAGE_SIZE order for
142	  DMA IOMMU buffers. Larger buffers will be aligned only to this
143	  specified order. The order is expressed as a power of two multiplied
144	  by the PAGE_SIZE.
145
146endif
147
148config MIGHT_HAVE_PCI
149	bool
150
151config SYS_SUPPORTS_APM_EMULATION
152	bool
153
154config HAVE_TCM
155	bool
156	select GENERIC_ALLOCATOR
157
158config HAVE_PROC_CPU
159	bool
160
161config NO_IOPORT_MAP
162	bool
163
164config EISA
165	bool
166	---help---
167	  The Extended Industry Standard Architecture (EISA) bus was
168	  developed as an open alternative to the IBM MicroChannel bus.
169
170	  The EISA bus provided some of the features of the IBM MicroChannel
171	  bus while maintaining backward compatibility with cards made for
172	  the older ISA bus.  The EISA bus saw limited use between 1988 and
173	  1995 when it was made obsolete by the PCI bus.
174
175	  Say Y here if you are building a kernel for an EISA-based machine.
176
177	  Otherwise, say N.
178
179config SBUS
180	bool
181
182config STACKTRACE_SUPPORT
183	bool
184	default y
185
186config LOCKDEP_SUPPORT
187	bool
188	default y
189
190config TRACE_IRQFLAGS_SUPPORT
191	bool
192	default !CPU_V7M
193
194config RWSEM_XCHGADD_ALGORITHM
195	bool
196	default y
197
198config ARCH_HAS_ILOG2_U32
199	bool
200
201config ARCH_HAS_ILOG2_U64
202	bool
203
204config ARCH_HAS_BANDGAP
205	bool
206
207config FIX_EARLYCON_MEM
208	def_bool y if MMU
209
210config GENERIC_HWEIGHT
211	bool
212	default y
213
214config GENERIC_CALIBRATE_DELAY
215	bool
216	default y
217
218config ARCH_MAY_HAVE_PC_FDC
219	bool
220
221config ZONE_DMA
222	bool
223
224config NEED_DMA_MAP_STATE
225       def_bool y
226
227config ARCH_SUPPORTS_UPROBES
228	def_bool y
229
230config ARCH_HAS_DMA_SET_COHERENT_MASK
231	bool
232
233config GENERIC_ISA_DMA
234	bool
235
236config FIQ
237	bool
238
239config NEED_RET_TO_USER
240	bool
241
242config ARCH_MTD_XIP
243	bool
244
245config ARM_PATCH_PHYS_VIRT
246	bool "Patch physical to virtual translations at runtime" if EMBEDDED
247	default y
248	depends on !XIP_KERNEL && MMU
249	help
250	  Patch phys-to-virt and virt-to-phys translation functions at
251	  boot and module load time according to the position of the
252	  kernel in system memory.
253
254	  This can only be used with non-XIP MMU kernels where the base
255	  of physical memory is at a 16MB boundary.
256
257	  Only disable this option if you know that you do not require
258	  this feature (eg, building a kernel for a single machine) and
259	  you need to shrink the kernel to the minimal size.
260
261config NEED_MACH_IO_H
262	bool
263	help
264	  Select this when mach/io.h is required to provide special
265	  definitions for this platform.  The need for mach/io.h should
266	  be avoided when possible.
267
268config NEED_MACH_MEMORY_H
269	bool
270	help
271	  Select this when mach/memory.h is required to provide special
272	  definitions for this platform.  The need for mach/memory.h should
273	  be avoided when possible.
274
275config PHYS_OFFSET
276	hex "Physical address of main memory" if MMU
277	depends on !ARM_PATCH_PHYS_VIRT
278	default DRAM_BASE if !MMU
279	default 0x00000000 if ARCH_EBSA110 || \
280			ARCH_FOOTBRIDGE || \
281			ARCH_INTEGRATOR || \
282			ARCH_IOP13XX || \
283			ARCH_KS8695 || \
284			ARCH_REALVIEW
285	default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
286	default 0x20000000 if ARCH_S5PV210
287	default 0xc0000000 if ARCH_SA1100
288	help
289	  Please provide the physical address corresponding to the
290	  location of main memory in your system.
291
292config GENERIC_BUG
293	def_bool y
294	depends on BUG
295
296config PGTABLE_LEVELS
297	int
298	default 3 if ARM_LPAE
299	default 2
300
301source "init/Kconfig"
302
303source "kernel/Kconfig.freezer"
304
305menu "System Type"
306
307config MMU
308	bool "MMU-based Paged Memory Management Support"
309	default y
310	help
311	  Select if you want MMU-based virtualised addressing space
312	  support by paged memory management. If unsure, say 'Y'.
313
314config ARCH_MMAP_RND_BITS_MIN
315	default 8
316
317config ARCH_MMAP_RND_BITS_MAX
318	default 14 if PAGE_OFFSET=0x40000000
319	default 15 if PAGE_OFFSET=0x80000000
320	default 16
321
322#
323# The "ARM system type" choice list is ordered alphabetically by option
324# text.  Please add new entries in the option alphabetic order.
325#
326choice
327	prompt "ARM system type"
328	default ARM_SINGLE_ARMV7M if !MMU
329	default ARCH_MULTIPLATFORM if MMU
330
331config ARCH_MULTIPLATFORM
332	bool "Allow multiple platforms to be selected"
333	depends on MMU
334	select ARM_HAS_SG_CHAIN
335	select ARM_PATCH_PHYS_VIRT
336	select AUTO_ZRELADDR
337	select TIMER_OF
338	select COMMON_CLK
339	select GENERIC_CLOCKEVENTS
340	select MIGHT_HAVE_PCI
341	select MULTI_IRQ_HANDLER
342	select PCI_DOMAINS if PCI
343	select SPARSE_IRQ
344	select USE_OF
345
346config ARM_SINGLE_ARMV7M
347	bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
348	depends on !MMU
349	select ARM_NVIC
350	select AUTO_ZRELADDR
351	select TIMER_OF
352	select COMMON_CLK
353	select CPU_V7M
354	select GENERIC_CLOCKEVENTS
355	select NO_IOPORT_MAP
356	select SPARSE_IRQ
357	select USE_OF
358
359config ARCH_EBSA110
360	bool "EBSA-110"
361	select ARCH_USES_GETTIMEOFFSET
362	select CPU_SA110
363	select ISA
364	select NEED_MACH_IO_H
365	select NEED_MACH_MEMORY_H
366	select NO_IOPORT_MAP
367	help
368	  This is an evaluation board for the StrongARM processor available
369	  from Digital. It has limited hardware on-board, including an
370	  Ethernet interface, two PCMCIA sockets, two serial ports and a
371	  parallel port.
372
373config ARCH_EP93XX
374	bool "EP93xx-based"
375	select ARCH_SPARSEMEM_ENABLE
376	select ARM_AMBA
377	imply ARM_PATCH_PHYS_VIRT
378	select ARM_VIC
379	select AUTO_ZRELADDR
380	select CLKDEV_LOOKUP
381	select CLKSRC_MMIO
382	select CPU_ARM920T
383	select GENERIC_CLOCKEVENTS
384	select GPIOLIB
385	help
386	  This enables support for the Cirrus EP93xx series of CPUs.
387
388config ARCH_FOOTBRIDGE
389	bool "FootBridge"
390	select CPU_SA110
391	select FOOTBRIDGE
392	select GENERIC_CLOCKEVENTS
393	select HAVE_IDE
394	select NEED_MACH_IO_H if !MMU
395	select NEED_MACH_MEMORY_H
396	help
397	  Support for systems based on the DC21285 companion chip
398	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
399
400config ARCH_NETX
401	bool "Hilscher NetX based"
402	select ARM_VIC
403	select CLKSRC_MMIO
404	select CPU_ARM926T
405	select GENERIC_CLOCKEVENTS
406	help
407	  This enables support for systems based on the Hilscher NetX Soc
408
409config ARCH_IOP13XX
410	bool "IOP13xx-based"
411	depends on MMU
412	select CPU_XSC3
413	select NEED_MACH_MEMORY_H
414	select NEED_RET_TO_USER
415	select PCI
416	select PLAT_IOP
417	select VMSPLIT_1G
418	select SPARSE_IRQ
419	help
420	  Support for Intel's IOP13XX (XScale) family of processors.
421
422config ARCH_IOP32X
423	bool "IOP32x-based"
424	depends on MMU
425	select CPU_XSCALE
426	select GPIO_IOP
427	select GPIOLIB
428	select NEED_RET_TO_USER
429	select PCI
430	select PLAT_IOP
431	help
432	  Support for Intel's 80219 and IOP32X (XScale) family of
433	  processors.
434
435config ARCH_IOP33X
436	bool "IOP33x-based"
437	depends on MMU
438	select CPU_XSCALE
439	select GPIO_IOP
440	select GPIOLIB
441	select NEED_RET_TO_USER
442	select PCI
443	select PLAT_IOP
444	help
445	  Support for Intel's IOP33X (XScale) family of processors.
446
447config ARCH_IXP4XX
448	bool "IXP4xx-based"
449	depends on MMU
450	select ARCH_HAS_DMA_SET_COHERENT_MASK
451	select ARCH_SUPPORTS_BIG_ENDIAN
452	select CLKSRC_MMIO
453	select CPU_XSCALE
454	select DMABOUNCE if PCI
455	select GENERIC_CLOCKEVENTS
456	select GPIOLIB
457	select MIGHT_HAVE_PCI
458	select NEED_MACH_IO_H
459	select USB_EHCI_BIG_ENDIAN_DESC
460	select USB_EHCI_BIG_ENDIAN_MMIO
461	help
462	  Support for Intel's IXP4XX (XScale) family of processors.
463
464config ARCH_DOVE
465	bool "Marvell Dove"
466	select CPU_PJ4
467	select GENERIC_CLOCKEVENTS
468	select GPIOLIB
469	select MIGHT_HAVE_PCI
470	select MULTI_IRQ_HANDLER
471	select MVEBU_MBUS
472	select PINCTRL
473	select PINCTRL_DOVE
474	select PLAT_ORION_LEGACY
475	select SPARSE_IRQ
476	select PM_GENERIC_DOMAINS if PM
477	help
478	  Support for the Marvell Dove SoC 88AP510
479
480config ARCH_KS8695
481	bool "Micrel/Kendin KS8695"
482	select CLKSRC_MMIO
483	select CPU_ARM922T
484	select GENERIC_CLOCKEVENTS
485	select GPIOLIB
486	select NEED_MACH_MEMORY_H
487	help
488	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
489	  System-on-Chip devices.
490
491config ARCH_W90X900
492	bool "Nuvoton W90X900 CPU"
493	select CLKDEV_LOOKUP
494	select CLKSRC_MMIO
495	select CPU_ARM926T
496	select GENERIC_CLOCKEVENTS
497	select GPIOLIB
498	help
499	  Support for Nuvoton (Winbond logic dept.) ARM9 processor,
500	  At present, the w90x900 has been renamed nuc900, regarding
501	  the ARM series product line, you can login the following
502	  link address to know more.
503
504	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
505		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
506
507config ARCH_LPC32XX
508	bool "NXP LPC32XX"
509	select ARM_AMBA
510	select CLKDEV_LOOKUP
511	select CLKSRC_LPC32XX
512	select COMMON_CLK
513	select CPU_ARM926T
514	select GENERIC_CLOCKEVENTS
515	select GPIOLIB
516	select MULTI_IRQ_HANDLER
517	select SPARSE_IRQ
518	select USE_OF
519	help
520	  Support for the NXP LPC32XX family of processors
521
522config ARCH_PXA
523	bool "PXA2xx/PXA3xx-based"
524	depends on MMU
525	select ARCH_MTD_XIP
526	select ARM_CPU_SUSPEND if PM
527	select AUTO_ZRELADDR
528	select COMMON_CLK
529	select CLKDEV_LOOKUP
530	select CLKSRC_PXA
531	select CLKSRC_MMIO
532	select TIMER_OF
533	select CPU_XSCALE if !CPU_XSC3
534	select GENERIC_CLOCKEVENTS
535	select GPIO_PXA
536	select GPIOLIB
537	select HAVE_IDE
538	select IRQ_DOMAIN
539	select MULTI_IRQ_HANDLER
540	select PLAT_PXA
541	select SPARSE_IRQ
542	help
543	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
544
545config ARCH_RPC
546	bool "RiscPC"
547	depends on MMU
548	select ARCH_ACORN
549	select ARCH_MAY_HAVE_PC_FDC
550	select ARCH_SPARSEMEM_ENABLE
551	select ARCH_USES_GETTIMEOFFSET
552	select CPU_SA110
553	select FIQ
554	select HAVE_IDE
555	select HAVE_PATA_PLATFORM
556	select ISA_DMA_API
557	select NEED_MACH_IO_H
558	select NEED_MACH_MEMORY_H
559	select NO_IOPORT_MAP
560	help
561	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
562	  CD-ROM interface, serial and parallel port, and the floppy drive.
563
564config ARCH_SA1100
565	bool "SA1100-based"
566	select ARCH_MTD_XIP
567	select ARCH_SPARSEMEM_ENABLE
568	select CLKDEV_LOOKUP
569	select CLKSRC_MMIO
570	select CLKSRC_PXA
571	select TIMER_OF if OF
572	select CPU_FREQ
573	select CPU_SA1100
574	select GENERIC_CLOCKEVENTS
575	select GPIOLIB
576	select HAVE_IDE
577	select IRQ_DOMAIN
578	select ISA
579	select MULTI_IRQ_HANDLER
580	select NEED_MACH_MEMORY_H
581	select SPARSE_IRQ
582	help
583	  Support for StrongARM 11x0 based boards.
584
585config ARCH_S3C24XX
586	bool "Samsung S3C24XX SoCs"
587	select ATAGS
588	select CLKDEV_LOOKUP
589	select CLKSRC_SAMSUNG_PWM
590	select GENERIC_CLOCKEVENTS
591	select GPIO_SAMSUNG
592	select GPIOLIB
593	select HAVE_S3C2410_I2C if I2C
594	select HAVE_S3C2410_WATCHDOG if WATCHDOG
595	select HAVE_S3C_RTC if RTC_CLASS
596	select MULTI_IRQ_HANDLER
597	select NEED_MACH_IO_H
598	select SAMSUNG_ATAGS
599	help
600	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
601	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
602	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
603	  Samsung SMDK2410 development board (and derivatives).
604
605config ARCH_DAVINCI
606	bool "TI DaVinci"
607	select ARCH_HAS_HOLES_MEMORYMODEL
608	select CLKDEV_LOOKUP
609	select CPU_ARM926T
610	select GENERIC_ALLOCATOR
611	select GENERIC_CLOCKEVENTS
612	select GENERIC_IRQ_CHIP
613	select GPIOLIB
614	select HAVE_IDE
615	select USE_OF
616	select ZONE_DMA
617	help
618	  Support for TI's DaVinci platform.
619
620config ARCH_OMAP1
621	bool "TI OMAP1"
622	depends on MMU
623	select ARCH_HAS_HOLES_MEMORYMODEL
624	select ARCH_OMAP
625	select CLKDEV_LOOKUP
626	select CLKSRC_MMIO
627	select GENERIC_CLOCKEVENTS
628	select GENERIC_IRQ_CHIP
629	select GPIOLIB
630	select HAVE_IDE
631	select IRQ_DOMAIN
632	select MULTI_IRQ_HANDLER
633	select NEED_MACH_IO_H if PCCARD
634	select NEED_MACH_MEMORY_H
635	select SPARSE_IRQ
636	help
637	  Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
638
639endchoice
640
641menu "Multiple platform selection"
642	depends on ARCH_MULTIPLATFORM
643
644comment "CPU Core family selection"
645
646config ARCH_MULTI_V4
647	bool "ARMv4 based platforms (FA526)"
648	depends on !ARCH_MULTI_V6_V7
649	select ARCH_MULTI_V4_V5
650	select CPU_FA526
651
652config ARCH_MULTI_V4T
653	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
654	depends on !ARCH_MULTI_V6_V7
655	select ARCH_MULTI_V4_V5
656	select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
657		CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
658		CPU_ARM925T || CPU_ARM940T)
659
660config ARCH_MULTI_V5
661	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
662	depends on !ARCH_MULTI_V6_V7
663	select ARCH_MULTI_V4_V5
664	select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
665		CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
666		CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
667
668config ARCH_MULTI_V4_V5
669	bool
670
671config ARCH_MULTI_V6
672	bool "ARMv6 based platforms (ARM11)"
673	select ARCH_MULTI_V6_V7
674	select CPU_V6K
675
676config ARCH_MULTI_V7
677	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
678	default y
679	select ARCH_MULTI_V6_V7
680	select CPU_V7
681	select HAVE_SMP
682
683config ARCH_MULTI_V6_V7
684	bool
685	select MIGHT_HAVE_CACHE_L2X0
686
687config ARCH_MULTI_CPU_AUTO
688	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
689	select ARCH_MULTI_V5
690
691endmenu
692
693config ARCH_VIRT
694	bool "Dummy Virtual Machine"
695	depends on ARCH_MULTI_V7
696	select ARM_AMBA
697	select ARM_GIC
698	select ARM_GIC_V2M if PCI
699	select ARM_GIC_V3
700	select ARM_GIC_V3_ITS if PCI
701	select ARM_PSCI
702	select HAVE_ARM_ARCH_TIMER
703
704#
705# This is sorted alphabetically by mach-* pathname.  However, plat-*
706# Kconfigs may be included either alphabetically (according to the
707# plat- suffix) or along side the corresponding mach-* source.
708#
709source "arch/arm/mach-mvebu/Kconfig"
710
711source "arch/arm/mach-actions/Kconfig"
712
713source "arch/arm/mach-alpine/Kconfig"
714
715source "arch/arm/mach-artpec/Kconfig"
716
717source "arch/arm/mach-asm9260/Kconfig"
718
719source "arch/arm/mach-at91/Kconfig"
720
721source "arch/arm/mach-axxia/Kconfig"
722
723source "arch/arm/mach-bcm/Kconfig"
724
725source "arch/arm/mach-berlin/Kconfig"
726
727source "arch/arm/mach-clps711x/Kconfig"
728
729source "arch/arm/mach-cns3xxx/Kconfig"
730
731source "arch/arm/mach-davinci/Kconfig"
732
733source "arch/arm/mach-digicolor/Kconfig"
734
735source "arch/arm/mach-dove/Kconfig"
736
737source "arch/arm/mach-ep93xx/Kconfig"
738
739source "arch/arm/mach-footbridge/Kconfig"
740
741source "arch/arm/mach-gemini/Kconfig"
742
743source "arch/arm/mach-highbank/Kconfig"
744
745source "arch/arm/mach-hisi/Kconfig"
746
747source "arch/arm/mach-integrator/Kconfig"
748
749source "arch/arm/mach-iop32x/Kconfig"
750
751source "arch/arm/mach-iop33x/Kconfig"
752
753source "arch/arm/mach-iop13xx/Kconfig"
754
755source "arch/arm/mach-ixp4xx/Kconfig"
756
757source "arch/arm/mach-keystone/Kconfig"
758
759source "arch/arm/mach-ks8695/Kconfig"
760
761source "arch/arm/mach-meson/Kconfig"
762
763source "arch/arm/mach-moxart/Kconfig"
764
765source "arch/arm/mach-aspeed/Kconfig"
766
767source "arch/arm/mach-mv78xx0/Kconfig"
768
769source "arch/arm/mach-imx/Kconfig"
770
771source "arch/arm/mach-mediatek/Kconfig"
772
773source "arch/arm/mach-mxs/Kconfig"
774
775source "arch/arm/mach-netx/Kconfig"
776
777source "arch/arm/mach-nomadik/Kconfig"
778
779source "arch/arm/mach-nspire/Kconfig"
780
781source "arch/arm/plat-omap/Kconfig"
782
783source "arch/arm/mach-omap1/Kconfig"
784
785source "arch/arm/mach-omap2/Kconfig"
786
787source "arch/arm/mach-orion5x/Kconfig"
788
789source "arch/arm/mach-picoxcell/Kconfig"
790
791source "arch/arm/mach-pxa/Kconfig"
792source "arch/arm/plat-pxa/Kconfig"
793
794source "arch/arm/mach-mmp/Kconfig"
795
796source "arch/arm/mach-oxnas/Kconfig"
797
798source "arch/arm/mach-qcom/Kconfig"
799
800source "arch/arm/mach-realview/Kconfig"
801
802source "arch/arm/mach-rockchip/Kconfig"
803
804source "arch/arm/mach-sa1100/Kconfig"
805
806source "arch/arm/mach-socfpga/Kconfig"
807
808source "arch/arm/mach-spear/Kconfig"
809
810source "arch/arm/mach-sti/Kconfig"
811
812source "arch/arm/mach-stm32/Kconfig"
813
814source "arch/arm/mach-s3c24xx/Kconfig"
815
816source "arch/arm/mach-s3c64xx/Kconfig"
817
818source "arch/arm/mach-s5pv210/Kconfig"
819
820source "arch/arm/mach-exynos/Kconfig"
821source "arch/arm/plat-samsung/Kconfig"
822
823source "arch/arm/mach-shmobile/Kconfig"
824
825source "arch/arm/mach-sunxi/Kconfig"
826
827source "arch/arm/mach-prima2/Kconfig"
828
829source "arch/arm/mach-tango/Kconfig"
830
831source "arch/arm/mach-tegra/Kconfig"
832
833source "arch/arm/mach-u300/Kconfig"
834
835source "arch/arm/mach-uniphier/Kconfig"
836
837source "arch/arm/mach-ux500/Kconfig"
838
839source "arch/arm/mach-versatile/Kconfig"
840
841source "arch/arm/mach-vexpress/Kconfig"
842source "arch/arm/plat-versatile/Kconfig"
843
844source "arch/arm/mach-vt8500/Kconfig"
845
846source "arch/arm/mach-w90x900/Kconfig"
847
848source "arch/arm/mach-zx/Kconfig"
849
850source "arch/arm/mach-zynq/Kconfig"
851
852# ARMv7-M architecture
853config ARCH_EFM32
854	bool "Energy Micro efm32"
855	depends on ARM_SINGLE_ARMV7M
856	select GPIOLIB
857	help
858	  Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
859	  processors.
860
861config ARCH_LPC18XX
862	bool "NXP LPC18xx/LPC43xx"
863	depends on ARM_SINGLE_ARMV7M
864	select ARCH_HAS_RESET_CONTROLLER
865	select ARM_AMBA
866	select CLKSRC_LPC32XX
867	select PINCTRL
868	help
869	  Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
870	  high performance microcontrollers.
871
872config ARCH_MPS2
873	bool "ARM MPS2 platform"
874	depends on ARM_SINGLE_ARMV7M
875	select ARM_AMBA
876	select CLKSRC_MPS2
877	help
878	  Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
879	  with a range of available cores like Cortex-M3/M4/M7.
880
881	  Please, note that depends which Application Note is used memory map
882	  for the platform may vary, so adjustment of RAM base might be needed.
883
884# Definitions to make life easier
885config ARCH_ACORN
886	bool
887
888config PLAT_IOP
889	bool
890	select GENERIC_CLOCKEVENTS
891
892config PLAT_ORION
893	bool
894	select CLKSRC_MMIO
895	select COMMON_CLK
896	select GENERIC_IRQ_CHIP
897	select IRQ_DOMAIN
898
899config PLAT_ORION_LEGACY
900	bool
901	select PLAT_ORION
902
903config PLAT_PXA
904	bool
905
906config PLAT_VERSATILE
907	bool
908
909source "arch/arm/firmware/Kconfig"
910
911source arch/arm/mm/Kconfig
912
913config IWMMXT
914	bool "Enable iWMMXt support"
915	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
916	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
917	help
918	  Enable support for iWMMXt context switching at run time if
919	  running on a CPU that supports it.
920
921config MULTI_IRQ_HANDLER
922	bool
923	help
924	  Allow each machine to specify it's own IRQ handler at run time.
925
926if !MMU
927source "arch/arm/Kconfig-nommu"
928endif
929
930config PJ4B_ERRATA_4742
931	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
932	depends on CPU_PJ4B && MACH_ARMADA_370
933	default y
934	help
935	  When coming out of either a Wait for Interrupt (WFI) or a Wait for
936	  Event (WFE) IDLE states, a specific timing sensitivity exists between
937	  the retiring WFI/WFE instructions and the newly issued subsequent
938	  instructions.  This sensitivity can result in a CPU hang scenario.
939	  Workaround:
940	  The software must insert either a Data Synchronization Barrier (DSB)
941	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE
942	  instruction
943
944config ARM_ERRATA_326103
945	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
946	depends on CPU_V6
947	help
948	  Executing a SWP instruction to read-only memory does not set bit 11
949	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
950	  treat the access as a read, preventing a COW from occurring and
951	  causing the faulting task to livelock.
952
953config ARM_ERRATA_411920
954	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
955	depends on CPU_V6 || CPU_V6K
956	help
957	  Invalidation of the Instruction Cache operation can
958	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
959	  It does not affect the MPCore. This option enables the ARM Ltd.
960	  recommended workaround.
961
962config ARM_ERRATA_430973
963	bool "ARM errata: Stale prediction on replaced interworking branch"
964	depends on CPU_V7
965	help
966	  This option enables the workaround for the 430973 Cortex-A8
967	  r1p* erratum. If a code sequence containing an ARM/Thumb
968	  interworking branch is replaced with another code sequence at the
969	  same virtual address, whether due to self-modifying code or virtual
970	  to physical address re-mapping, Cortex-A8 does not recover from the
971	  stale interworking branch prediction. This results in Cortex-A8
972	  executing the new code sequence in the incorrect ARM or Thumb state.
973	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
974	  and also flushes the branch target cache at every context switch.
975	  Note that setting specific bits in the ACTLR register may not be
976	  available in non-secure mode.
977
978config ARM_ERRATA_458693
979	bool "ARM errata: Processor deadlock when a false hazard is created"
980	depends on CPU_V7
981	depends on !ARCH_MULTIPLATFORM
982	help
983	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
984	  erratum. For very specific sequences of memory operations, it is
985	  possible for a hazard condition intended for a cache line to instead
986	  be incorrectly associated with a different cache line. This false
987	  hazard might then cause a processor deadlock. The workaround enables
988	  the L1 caching of the NEON accesses and disables the PLD instruction
989	  in the ACTLR register. Note that setting specific bits in the ACTLR
990	  register may not be available in non-secure mode.
991
992config ARM_ERRATA_460075
993	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
994	depends on CPU_V7
995	depends on !ARCH_MULTIPLATFORM
996	help
997	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
998	  erratum. Any asynchronous access to the L2 cache may encounter a
999	  situation in which recent store transactions to the L2 cache are lost
1000	  and overwritten with stale memory contents from external memory. The
1001	  workaround disables the write-allocate mode for the L2 cache via the
1002	  ACTLR register. Note that setting specific bits in the ACTLR register
1003	  may not be available in non-secure mode.
1004
1005config ARM_ERRATA_742230
1006	bool "ARM errata: DMB operation may be faulty"
1007	depends on CPU_V7 && SMP
1008	depends on !ARCH_MULTIPLATFORM
1009	help
1010	  This option enables the workaround for the 742230 Cortex-A9
1011	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1012	  between two write operations may not ensure the correct visibility
1013	  ordering of the two writes. This workaround sets a specific bit in
1014	  the diagnostic register of the Cortex-A9 which causes the DMB
1015	  instruction to behave as a DSB, ensuring the correct behaviour of
1016	  the two writes.
1017
1018config ARM_ERRATA_742231
1019	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1020	depends on CPU_V7 && SMP
1021	depends on !ARCH_MULTIPLATFORM
1022	help
1023	  This option enables the workaround for the 742231 Cortex-A9
1024	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
1025	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1026	  accessing some data located in the same cache line, may get corrupted
1027	  data due to bad handling of the address hazard when the line gets
1028	  replaced from one of the CPUs at the same time as another CPU is
1029	  accessing it. This workaround sets specific bits in the diagnostic
1030	  register of the Cortex-A9 which reduces the linefill issuing
1031	  capabilities of the processor.
1032
1033config ARM_ERRATA_643719
1034	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1035	depends on CPU_V7 && SMP
1036	default y
1037	help
1038	  This option enables the workaround for the 643719 Cortex-A9 (prior to
1039	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1040	  register returns zero when it should return one. The workaround
1041	  corrects this value, ensuring cache maintenance operations which use
1042	  it behave as intended and avoiding data corruption.
1043
1044config ARM_ERRATA_720789
1045	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1046	depends on CPU_V7
1047	help
1048	  This option enables the workaround for the 720789 Cortex-A9 (prior to
1049	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1050	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1051	  As a consequence of this erratum, some TLB entries which should be
1052	  invalidated are not, resulting in an incoherency in the system page
1053	  tables. The workaround changes the TLB flushing routines to invalidate
1054	  entries regardless of the ASID.
1055
1056config ARM_ERRATA_743622
1057	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1058	depends on CPU_V7
1059	depends on !ARCH_MULTIPLATFORM
1060	help
1061	  This option enables the workaround for the 743622 Cortex-A9
1062	  (r2p*) erratum. Under very rare conditions, a faulty
1063	  optimisation in the Cortex-A9 Store Buffer may lead to data
1064	  corruption. This workaround sets a specific bit in the diagnostic
1065	  register of the Cortex-A9 which disables the Store Buffer
1066	  optimisation, preventing the defect from occurring. This has no
1067	  visible impact on the overall performance or power consumption of the
1068	  processor.
1069
1070config ARM_ERRATA_751472
1071	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1072	depends on CPU_V7
1073	depends on !ARCH_MULTIPLATFORM
1074	help
1075	  This option enables the workaround for the 751472 Cortex-A9 (prior
1076	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1077	  completion of a following broadcasted operation if the second
1078	  operation is received by a CPU before the ICIALLUIS has completed,
1079	  potentially leading to corrupted entries in the cache or TLB.
1080
1081config ARM_ERRATA_754322
1082	bool "ARM errata: possible faulty MMU translations following an ASID switch"
1083	depends on CPU_V7
1084	help
1085	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1086	  r3p*) erratum. A speculative memory access may cause a page table walk
1087	  which starts prior to an ASID switch but completes afterwards. This
1088	  can populate the micro-TLB with a stale entry which may be hit with
1089	  the new ASID. This workaround places two dsb instructions in the mm
1090	  switching code so that no page table walks can cross the ASID switch.
1091
1092config ARM_ERRATA_754327
1093	bool "ARM errata: no automatic Store Buffer drain"
1094	depends on CPU_V7 && SMP
1095	help
1096	  This option enables the workaround for the 754327 Cortex-A9 (prior to
1097	  r2p0) erratum. The Store Buffer does not have any automatic draining
1098	  mechanism and therefore a livelock may occur if an external agent
1099	  continuously polls a memory location waiting to observe an update.
1100	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
1101	  written polling loops from denying visibility of updates to memory.
1102
1103config ARM_ERRATA_364296
1104	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1105	depends on CPU_V6
1106	help
1107	  This options enables the workaround for the 364296 ARM1136
1108	  r0p2 erratum (possible cache data corruption with
1109	  hit-under-miss enabled). It sets the undocumented bit 31 in
1110	  the auxiliary control register and the FI bit in the control
1111	  register, thus disabling hit-under-miss without putting the
1112	  processor into full low interrupt latency mode. ARM11MPCore
1113	  is not affected.
1114
1115config ARM_ERRATA_764369
1116	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1117	depends on CPU_V7 && SMP
1118	help
1119	  This option enables the workaround for erratum 764369
1120	  affecting Cortex-A9 MPCore with two or more processors (all
1121	  current revisions). Under certain timing circumstances, a data
1122	  cache line maintenance operation by MVA targeting an Inner
1123	  Shareable memory region may fail to proceed up to either the
1124	  Point of Coherency or to the Point of Unification of the
1125	  system. This workaround adds a DSB instruction before the
1126	  relevant cache maintenance functions and sets a specific bit
1127	  in the diagnostic control register of the SCU.
1128
1129config ARM_ERRATA_775420
1130       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1131       depends on CPU_V7
1132       help
1133	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1134	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1135	 operation aborts with MMU exception, it might cause the processor
1136	 to deadlock. This workaround puts DSB before executing ISB if
1137	 an abort may occur on cache maintenance.
1138
1139config ARM_ERRATA_798181
1140	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1141	depends on CPU_V7 && SMP
1142	help
1143	  On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1144	  adequately shooting down all use of the old entries. This
1145	  option enables the Linux kernel workaround for this erratum
1146	  which sends an IPI to the CPUs that are running the same ASID
1147	  as the one being invalidated.
1148
1149config ARM_ERRATA_773022
1150	bool "ARM errata: incorrect instructions may be executed from loop buffer"
1151	depends on CPU_V7
1152	help
1153	  This option enables the workaround for the 773022 Cortex-A15
1154	  (up to r0p4) erratum. In certain rare sequences of code, the
1155	  loop buffer may deliver incorrect instructions. This
1156	  workaround disables the loop buffer to avoid the erratum.
1157
1158config ARM_ERRATA_818325_852422
1159	bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1160	depends on CPU_V7
1161	help
1162	  This option enables the workaround for:
1163	  - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1164	    instruction might deadlock.  Fixed in r0p1.
1165	  - Cortex-A12 852422: Execution of a sequence of instructions might
1166	    lead to either a data corruption or a CPU deadlock.  Not fixed in
1167	    any Cortex-A12 cores yet.
1168	  This workaround for all both errata involves setting bit[12] of the
1169	  Feature Register. This bit disables an optimisation applied to a
1170	  sequence of 2 instructions that use opposing condition codes.
1171
1172config ARM_ERRATA_821420
1173	bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1174	depends on CPU_V7
1175	help
1176	  This option enables the workaround for the 821420 Cortex-A12
1177	  (all revs) erratum. In very rare timing conditions, a sequence
1178	  of VMOV to Core registers instructions, for which the second
1179	  one is in the shadow of a branch or abort, can lead to a
1180	  deadlock when the VMOV instructions are issued out-of-order.
1181
1182config ARM_ERRATA_825619
1183	bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1184	depends on CPU_V7
1185	help
1186	  This option enables the workaround for the 825619 Cortex-A12
1187	  (all revs) erratum. Within rare timing constraints, executing a
1188	  DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1189	  and Device/Strongly-Ordered loads and stores might cause deadlock
1190
1191config ARM_ERRATA_852421
1192	bool "ARM errata: A17: DMB ST might fail to create order between stores"
1193	depends on CPU_V7
1194	help
1195	  This option enables the workaround for the 852421 Cortex-A17
1196	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1197	  execution of a DMB ST instruction might fail to properly order
1198	  stores from GroupA and stores from GroupB.
1199
1200config ARM_ERRATA_852423
1201	bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1202	depends on CPU_V7
1203	help
1204	  This option enables the workaround for:
1205	  - Cortex-A17 852423: Execution of a sequence of instructions might
1206	    lead to either a data corruption or a CPU deadlock.  Not fixed in
1207	    any Cortex-A17 cores yet.
1208	  This is identical to Cortex-A12 erratum 852422.  It is a separate
1209	  config option from the A12 erratum due to the way errata are checked
1210	  for and handled.
1211
1212endmenu
1213
1214source "arch/arm/common/Kconfig"
1215
1216menu "Bus support"
1217
1218config ISA
1219	bool
1220	help
1221	  Find out whether you have ISA slots on your motherboard.  ISA is the
1222	  name of a bus system, i.e. the way the CPU talks to the other stuff
1223	  inside your box.  Other bus systems are PCI, EISA, MicroChannel
1224	  (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1225	  newer boards don't support it.  If you have ISA, say Y, otherwise N.
1226
1227# Select ISA DMA controller support
1228config ISA_DMA
1229	bool
1230	select ISA_DMA_API
1231
1232# Select ISA DMA interface
1233config ISA_DMA_API
1234	bool
1235
1236config PCI
1237	bool "PCI support" if MIGHT_HAVE_PCI
1238	help
1239	  Find out whether you have a PCI motherboard. PCI is the name of a
1240	  bus system, i.e. the way the CPU talks to the other stuff inside
1241	  your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1242	  VESA. If you have PCI, say Y, otherwise N.
1243
1244config PCI_DOMAINS
1245	bool
1246	depends on PCI
1247
1248config PCI_DOMAINS_GENERIC
1249	def_bool PCI_DOMAINS
1250
1251config PCI_NANOENGINE
1252	bool "BSE nanoEngine PCI support"
1253	depends on SA1100_NANOENGINE
1254	help
1255	  Enable PCI on the BSE nanoEngine board.
1256
1257config PCI_SYSCALL
1258	def_bool PCI
1259
1260config PCI_HOST_ITE8152
1261	bool
1262	depends on PCI && MACH_ARMCORE
1263	default y
1264	select DMABOUNCE
1265
1266source "drivers/pci/Kconfig"
1267
1268source "drivers/pcmcia/Kconfig"
1269
1270endmenu
1271
1272menu "Kernel Features"
1273
1274config HAVE_SMP
1275	bool
1276	help
1277	  This option should be selected by machines which have an SMP-
1278	  capable CPU.
1279
1280	  The only effect of this option is to make the SMP-related
1281	  options available to the user for configuration.
1282
1283config SMP
1284	bool "Symmetric Multi-Processing"
1285	depends on CPU_V6K || CPU_V7
1286	depends on GENERIC_CLOCKEVENTS
1287	depends on HAVE_SMP
1288	depends on MMU || ARM_MPU
1289	select IRQ_WORK
1290	help
1291	  This enables support for systems with more than one CPU. If you have
1292	  a system with only one CPU, say N. If you have a system with more
1293	  than one CPU, say Y.
1294
1295	  If you say N here, the kernel will run on uni- and multiprocessor
1296	  machines, but will use only one CPU of a multiprocessor machine. If
1297	  you say Y here, the kernel will run on many, but not all,
1298	  uniprocessor machines. On a uniprocessor machine, the kernel
1299	  will run faster if you say N here.
1300
1301	  See also <file:Documentation/x86/i386/IO-APIC.txt>,
1302	  <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1303	  <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1304
1305	  If you don't know what to do here, say N.
1306
1307config SMP_ON_UP
1308	bool "Allow booting SMP kernel on uniprocessor systems"
1309	depends on SMP && !XIP_KERNEL && MMU
1310	default y
1311	help
1312	  SMP kernels contain instructions which fail on non-SMP processors.
1313	  Enabling this option allows the kernel to modify itself to make
1314	  these instructions safe.  Disabling it allows about 1K of space
1315	  savings.
1316
1317	  If you don't know what to do here, say Y.
1318
1319config ARM_CPU_TOPOLOGY
1320	bool "Support cpu topology definition"
1321	depends on SMP && CPU_V7
1322	default y
1323	help
1324	  Support ARM cpu topology definition. The MPIDR register defines
1325	  affinity between processors which is then used to describe the cpu
1326	  topology of an ARM System.
1327
1328config SCHED_MC
1329	bool "Multi-core scheduler support"
1330	depends on ARM_CPU_TOPOLOGY
1331	help
1332	  Multi-core scheduler support improves the CPU scheduler's decision
1333	  making when dealing with multi-core CPU chips at a cost of slightly
1334	  increased overhead in some places. If unsure say N here.
1335
1336config SCHED_SMT
1337	bool "SMT scheduler support"
1338	depends on ARM_CPU_TOPOLOGY
1339	help
1340	  Improves the CPU scheduler's decision making when dealing with
1341	  MultiThreading at a cost of slightly increased overhead in some
1342	  places. If unsure say N here.
1343
1344config HAVE_ARM_SCU
1345	bool
1346	help
1347	  This option enables support for the ARM system coherency unit
1348
1349config HAVE_ARM_ARCH_TIMER
1350	bool "Architected timer support"
1351	depends on CPU_V7
1352	select ARM_ARCH_TIMER
1353	select GENERIC_CLOCKEVENTS
1354	help
1355	  This option enables support for the ARM architected timer
1356
1357config HAVE_ARM_TWD
1358	bool
1359	select TIMER_OF if OF
1360	help
1361	  This options enables support for the ARM timer and watchdog unit
1362
1363config MCPM
1364	bool "Multi-Cluster Power Management"
1365	depends on CPU_V7 && SMP
1366	help
1367	  This option provides the common power management infrastructure
1368	  for (multi-)cluster based systems, such as big.LITTLE based
1369	  systems.
1370
1371config MCPM_QUAD_CLUSTER
1372	bool
1373	depends on MCPM
1374	help
1375	  To avoid wasting resources unnecessarily, MCPM only supports up
1376	  to 2 clusters by default.
1377	  Platforms with 3 or 4 clusters that use MCPM must select this
1378	  option to allow the additional clusters to be managed.
1379
1380config BIG_LITTLE
1381	bool "big.LITTLE support (Experimental)"
1382	depends on CPU_V7 && SMP
1383	select MCPM
1384	help
1385	  This option enables support selections for the big.LITTLE
1386	  system architecture.
1387
1388config BL_SWITCHER
1389	bool "big.LITTLE switcher support"
1390	depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1391	select CPU_PM
1392	help
1393	  The big.LITTLE "switcher" provides the core functionality to
1394	  transparently handle transition between a cluster of A15's
1395	  and a cluster of A7's in a big.LITTLE system.
1396
1397config BL_SWITCHER_DUMMY_IF
1398	tristate "Simple big.LITTLE switcher user interface"
1399	depends on BL_SWITCHER && DEBUG_KERNEL
1400	help
1401	  This is a simple and dummy char dev interface to control
1402	  the big.LITTLE switcher core code.  It is meant for
1403	  debugging purposes only.
1404
1405choice
1406	prompt "Memory split"
1407	depends on MMU
1408	default VMSPLIT_3G
1409	help
1410	  Select the desired split between kernel and user memory.
1411
1412	  If you are not absolutely sure what you are doing, leave this
1413	  option alone!
1414
1415	config VMSPLIT_3G
1416		bool "3G/1G user/kernel split"
1417	config VMSPLIT_3G_OPT
1418		depends on !ARM_LPAE
1419		bool "3G/1G user/kernel split (for full 1G low memory)"
1420	config VMSPLIT_2G
1421		bool "2G/2G user/kernel split"
1422	config VMSPLIT_1G
1423		bool "1G/3G user/kernel split"
1424endchoice
1425
1426config PAGE_OFFSET
1427	hex
1428	default PHYS_OFFSET if !MMU
1429	default 0x40000000 if VMSPLIT_1G
1430	default 0x80000000 if VMSPLIT_2G
1431	default 0xB0000000 if VMSPLIT_3G_OPT
1432	default 0xC0000000
1433
1434config NR_CPUS
1435	int "Maximum number of CPUs (2-32)"
1436	range 2 32
1437	depends on SMP
1438	default "4"
1439
1440config HOTPLUG_CPU
1441	bool "Support for hot-pluggable CPUs"
1442	depends on SMP
1443	help
1444	  Say Y here to experiment with turning CPUs off and on.  CPUs
1445	  can be controlled through /sys/devices/system/cpu.
1446
1447config ARM_PSCI
1448	bool "Support for the ARM Power State Coordination Interface (PSCI)"
1449	depends on HAVE_ARM_SMCCC
1450	select ARM_PSCI_FW
1451	help
1452	  Say Y here if you want Linux to communicate with system firmware
1453	  implementing the PSCI specification for CPU-centric power
1454	  management operations described in ARM document number ARM DEN
1455	  0022A ("Power State Coordination Interface System Software on
1456	  ARM processors").
1457
1458# The GPIO number here must be sorted by descending number. In case of
1459# a multiplatform kernel, we just want the highest value required by the
1460# selected platforms.
1461config ARCH_NR_GPIO
1462	int
1463	default 2048 if ARCH_SOCFPGA
1464	default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1465		ARCH_ZYNQ
1466	default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1467		SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1468	default 416 if ARCH_SUNXI
1469	default 392 if ARCH_U8500
1470	default 352 if ARCH_VT8500
1471	default 288 if ARCH_ROCKCHIP
1472	default 264 if MACH_H4700
1473	default 0
1474	help
1475	  Maximum number of GPIOs in the system.
1476
1477	  If unsure, leave the default value.
1478
1479source kernel/Kconfig.preempt
1480
1481config HZ_FIXED
1482	int
1483	default 200 if ARCH_EBSA110
1484	default 128 if SOC_AT91RM9200
1485	default 0
1486
1487choice
1488	depends on HZ_FIXED = 0
1489	prompt "Timer frequency"
1490
1491config HZ_100
1492	bool "100 Hz"
1493
1494config HZ_200
1495	bool "200 Hz"
1496
1497config HZ_250
1498	bool "250 Hz"
1499
1500config HZ_300
1501	bool "300 Hz"
1502
1503config HZ_500
1504	bool "500 Hz"
1505
1506config HZ_1000
1507	bool "1000 Hz"
1508
1509endchoice
1510
1511config HZ
1512	int
1513	default HZ_FIXED if HZ_FIXED != 0
1514	default 100 if HZ_100
1515	default 200 if HZ_200
1516	default 250 if HZ_250
1517	default 300 if HZ_300
1518	default 500 if HZ_500
1519	default 1000
1520
1521config SCHED_HRTICK
1522	def_bool HIGH_RES_TIMERS
1523
1524config THUMB2_KERNEL
1525	bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1526	depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1527	default y if CPU_THUMBONLY
1528	select ARM_ASM_UNIFIED
1529	select ARM_UNWIND
1530	help
1531	  By enabling this option, the kernel will be compiled in
1532	  Thumb-2 mode. A compiler/assembler that understand the unified
1533	  ARM-Thumb syntax is needed.
1534
1535	  If unsure, say N.
1536
1537config THUMB2_AVOID_R_ARM_THM_JUMP11
1538	bool "Work around buggy Thumb-2 short branch relocations in gas"
1539	depends on THUMB2_KERNEL && MODULES
1540	default y
1541	help
1542	  Various binutils versions can resolve Thumb-2 branches to
1543	  locally-defined, preemptible global symbols as short-range "b.n"
1544	  branch instructions.
1545
1546	  This is a problem, because there's no guarantee the final
1547	  destination of the symbol, or any candidate locations for a
1548	  trampoline, are within range of the branch.  For this reason, the
1549	  kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1550	  relocation in modules at all, and it makes little sense to add
1551	  support.
1552
1553	  The symptom is that the kernel fails with an "unsupported
1554	  relocation" error when loading some modules.
1555
1556	  Until fixed tools are available, passing
1557	  -fno-optimize-sibling-calls to gcc should prevent gcc generating
1558	  code which hits this problem, at the cost of a bit of extra runtime
1559	  stack usage in some cases.
1560
1561	  The problem is described in more detail at:
1562	      https://bugs.launchpad.net/binutils-linaro/+bug/725126
1563
1564	  Only Thumb-2 kernels are affected.
1565
1566	  Unless you are sure your tools don't have this problem, say Y.
1567
1568config ARM_ASM_UNIFIED
1569	bool
1570
1571config ARM_PATCH_IDIV
1572	bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1573	depends on CPU_32v7 && !XIP_KERNEL
1574	default y
1575	help
1576	  The ARM compiler inserts calls to __aeabi_idiv() and
1577	  __aeabi_uidiv() when it needs to perform division on signed
1578	  and unsigned integers. Some v7 CPUs have support for the sdiv
1579	  and udiv instructions that can be used to implement those
1580	  functions.
1581
1582	  Enabling this option allows the kernel to modify itself to
1583	  replace the first two instructions of these library functions
1584	  with the sdiv or udiv plus "bx lr" instructions when the CPU
1585	  it is running on supports them. Typically this will be faster
1586	  and less power intensive than running the original library
1587	  code to do integer division.
1588
1589config AEABI
1590	bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1591	default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1592	help
1593	  This option allows for the kernel to be compiled using the latest
1594	  ARM ABI (aka EABI).  This is only useful if you are using a user
1595	  space environment that is also compiled with EABI.
1596
1597	  Since there are major incompatibilities between the legacy ABI and
1598	  EABI, especially with regard to structure member alignment, this
1599	  option also changes the kernel syscall calling convention to
1600	  disambiguate both ABIs and allow for backward compatibility support
1601	  (selected with CONFIG_OABI_COMPAT).
1602
1603	  To use this you need GCC version 4.0.0 or later.
1604
1605config OABI_COMPAT
1606	bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1607	depends on AEABI && !THUMB2_KERNEL
1608	help
1609	  This option preserves the old syscall interface along with the
1610	  new (ARM EABI) one. It also provides a compatibility layer to
1611	  intercept syscalls that have structure arguments which layout
1612	  in memory differs between the legacy ABI and the new ARM EABI
1613	  (only for non "thumb" binaries). This option adds a tiny
1614	  overhead to all syscalls and produces a slightly larger kernel.
1615
1616	  The seccomp filter system will not be available when this is
1617	  selected, since there is no way yet to sensibly distinguish
1618	  between calling conventions during filtering.
1619
1620	  If you know you'll be using only pure EABI user space then you
1621	  can say N here. If this option is not selected and you attempt
1622	  to execute a legacy ABI binary then the result will be
1623	  UNPREDICTABLE (in fact it can be predicted that it won't work
1624	  at all). If in doubt say N.
1625
1626config ARCH_HAS_HOLES_MEMORYMODEL
1627	bool
1628
1629config ARCH_SPARSEMEM_ENABLE
1630	bool
1631
1632config ARCH_SPARSEMEM_DEFAULT
1633	def_bool ARCH_SPARSEMEM_ENABLE
1634
1635config ARCH_SELECT_MEMORY_MODEL
1636	def_bool ARCH_SPARSEMEM_ENABLE
1637
1638config HAVE_ARCH_PFN_VALID
1639	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1640
1641config HAVE_GENERIC_GUP
1642	def_bool y
1643	depends on ARM_LPAE
1644
1645config HIGHMEM
1646	bool "High Memory Support"
1647	depends on MMU
1648	help
1649	  The address space of ARM processors is only 4 Gigabytes large
1650	  and it has to accommodate user address space, kernel address
1651	  space as well as some memory mapped IO. That means that, if you
1652	  have a large amount of physical memory and/or IO, not all of the
1653	  memory can be "permanently mapped" by the kernel. The physical
1654	  memory that is not permanently mapped is called "high memory".
1655
1656	  Depending on the selected kernel/user memory split, minimum
1657	  vmalloc space and actual amount of RAM, you may not need this
1658	  option which should result in a slightly faster kernel.
1659
1660	  If unsure, say n.
1661
1662config HIGHPTE
1663	bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1664	depends on HIGHMEM
1665	default y
1666	help
1667	  The VM uses one page of physical memory for each page table.
1668	  For systems with a lot of processes, this can use a lot of
1669	  precious low memory, eventually leading to low memory being
1670	  consumed by page tables.  Setting this option will allow
1671	  user-space 2nd level page tables to reside in high memory.
1672
1673config CPU_SW_DOMAIN_PAN
1674	bool "Enable use of CPU domains to implement privileged no-access"
1675	depends on MMU && !ARM_LPAE
1676	default y
1677	help
1678	  Increase kernel security by ensuring that normal kernel accesses
1679	  are unable to access userspace addresses.  This can help prevent
1680	  use-after-free bugs becoming an exploitable privilege escalation
1681	  by ensuring that magic values (such as LIST_POISON) will always
1682	  fault when dereferenced.
1683
1684	  CPUs with low-vector mappings use a best-efforts implementation.
1685	  Their lower 1MB needs to remain accessible for the vectors, but
1686	  the remainder of userspace will become appropriately inaccessible.
1687
1688config HW_PERF_EVENTS
1689	def_bool y
1690	depends on ARM_PMU
1691
1692config SYS_SUPPORTS_HUGETLBFS
1693       def_bool y
1694       depends on ARM_LPAE
1695
1696config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1697       def_bool y
1698       depends on ARM_LPAE
1699
1700config ARCH_WANT_GENERAL_HUGETLB
1701	def_bool y
1702
1703config ARM_MODULE_PLTS
1704	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1705	depends on MODULES
1706	help
1707	  Allocate PLTs when loading modules so that jumps and calls whose
1708	  targets are too far away for their relative offsets to be encoded
1709	  in the instructions themselves can be bounced via veneers in the
1710	  module's PLT. This allows modules to be allocated in the generic
1711	  vmalloc area after the dedicated module memory area has been
1712	  exhausted. The modules will use slightly more memory, but after
1713	  rounding up to page size, the actual memory footprint is usually
1714	  the same.
1715
1716	  Say y if you are getting out of memory errors while loading modules
1717
1718source "mm/Kconfig"
1719
1720config FORCE_MAX_ZONEORDER
1721	int "Maximum zone order"
1722	default "12" if SOC_AM33XX
1723	default "9" if SA1111 || ARCH_EFM32
1724	default "11"
1725	help
1726	  The kernel memory allocator divides physically contiguous memory
1727	  blocks into "zones", where each zone is a power of two number of
1728	  pages.  This option selects the largest power of two that the kernel
1729	  keeps in the memory allocator.  If you need to allocate very large
1730	  blocks of physically contiguous memory, then you may need to
1731	  increase this value.
1732
1733	  This config option is actually maximum order plus one. For example,
1734	  a value of 11 means that the largest free memory block is 2^10 pages.
1735
1736config ALIGNMENT_TRAP
1737	bool
1738	depends on CPU_CP15_MMU
1739	default y if !ARCH_EBSA110
1740	select HAVE_PROC_CPU if PROC_FS
1741	help
1742	  ARM processors cannot fetch/store information which is not
1743	  naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1744	  address divisible by 4. On 32-bit ARM processors, these non-aligned
1745	  fetch/store instructions will be emulated in software if you say
1746	  here, which has a severe performance impact. This is necessary for
1747	  correct operation of some network protocols. With an IP-only
1748	  configuration it is safe to say N, otherwise say Y.
1749
1750config UACCESS_WITH_MEMCPY
1751	bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1752	depends on MMU
1753	default y if CPU_FEROCEON
1754	help
1755	  Implement faster copy_to_user and clear_user methods for CPU
1756	  cores where a 8-word STM instruction give significantly higher
1757	  memory write throughput than a sequence of individual 32bit stores.
1758
1759	  A possible side effect is a slight increase in scheduling latency
1760	  between threads sharing the same address space if they invoke
1761	  such copy operations with large buffers.
1762
1763	  However, if the CPU data cache is using a write-allocate mode,
1764	  this option is unlikely to provide any performance gain.
1765
1766config SECCOMP
1767	bool
1768	prompt "Enable seccomp to safely compute untrusted bytecode"
1769	---help---
1770	  This kernel feature is useful for number crunching applications
1771	  that may need to compute untrusted bytecode during their
1772	  execution. By using pipes or other transports made available to
1773	  the process as file descriptors supporting the read/write
1774	  syscalls, it's possible to isolate those applications in
1775	  their own address space using seccomp. Once seccomp is
1776	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1777	  and the task is only allowed to execute a few safe syscalls
1778	  defined by each seccomp mode.
1779
1780config SWIOTLB
1781	def_bool y
1782
1783config IOMMU_HELPER
1784	def_bool SWIOTLB
1785
1786config PARAVIRT
1787	bool "Enable paravirtualization code"
1788	help
1789	  This changes the kernel so it can modify itself when it is run
1790	  under a hypervisor, potentially improving performance significantly
1791	  over full virtualization.
1792
1793config PARAVIRT_TIME_ACCOUNTING
1794	bool "Paravirtual steal time accounting"
1795	select PARAVIRT
1796	default n
1797	help
1798	  Select this option to enable fine granularity task steal time
1799	  accounting. Time spent executing other tasks in parallel with
1800	  the current vCPU is discounted from the vCPU power. To account for
1801	  that, there can be a small performance impact.
1802
1803	  If in doubt, say N here.
1804
1805config XEN_DOM0
1806	def_bool y
1807	depends on XEN
1808
1809config XEN
1810	bool "Xen guest support on ARM"
1811	depends on ARM && AEABI && OF
1812	depends on CPU_V7 && !CPU_V6
1813	depends on !GENERIC_ATOMIC64
1814	depends on MMU
1815	select ARCH_DMA_ADDR_T_64BIT
1816	select ARM_PSCI
1817	select SWIOTLB_XEN
1818	select PARAVIRT
1819	help
1820	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1821
1822endmenu
1823
1824menu "Boot options"
1825
1826config USE_OF
1827	bool "Flattened Device Tree support"
1828	select IRQ_DOMAIN
1829	select OF
1830	help
1831	  Include support for flattened device tree machine descriptions.
1832
1833config ATAGS
1834	bool "Support for the traditional ATAGS boot data passing" if USE_OF
1835	default y
1836	help
1837	  This is the traditional way of passing data to the kernel at boot
1838	  time. If you are solely relying on the flattened device tree (or
1839	  the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1840	  to remove ATAGS support from your kernel binary.  If unsure,
1841	  leave this to y.
1842
1843config DEPRECATED_PARAM_STRUCT
1844	bool "Provide old way to pass kernel parameters"
1845	depends on ATAGS
1846	help
1847	  This was deprecated in 2001 and announced to live on for 5 years.
1848	  Some old boot loaders still use this way.
1849
1850# Compressed boot loader in ROM.  Yes, we really want to ask about
1851# TEXT and BSS so we preserve their values in the config files.
1852config ZBOOT_ROM_TEXT
1853	hex "Compressed ROM boot loader base address"
1854	default "0"
1855	help
1856	  The physical address at which the ROM-able zImage is to be
1857	  placed in the target.  Platforms which normally make use of
1858	  ROM-able zImage formats normally set this to a suitable
1859	  value in their defconfig file.
1860
1861	  If ZBOOT_ROM is not enabled, this has no effect.
1862
1863config ZBOOT_ROM_BSS
1864	hex "Compressed ROM boot loader BSS address"
1865	default "0"
1866	help
1867	  The base address of an area of read/write memory in the target
1868	  for the ROM-able zImage which must be available while the
1869	  decompressor is running. It must be large enough to hold the
1870	  entire decompressed kernel plus an additional 128 KiB.
1871	  Platforms which normally make use of ROM-able zImage formats
1872	  normally set this to a suitable value in their defconfig file.
1873
1874	  If ZBOOT_ROM is not enabled, this has no effect.
1875
1876config ZBOOT_ROM
1877	bool "Compressed boot loader in ROM/flash"
1878	depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1879	depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1880	help
1881	  Say Y here if you intend to execute your compressed kernel image
1882	  (zImage) directly from ROM or flash.  If unsure, say N.
1883
1884config ARM_APPENDED_DTB
1885	bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1886	depends on OF
1887	help
1888	  With this option, the boot code will look for a device tree binary
1889	  (DTB) appended to zImage
1890	  (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1891
1892	  This is meant as a backward compatibility convenience for those
1893	  systems with a bootloader that can't be upgraded to accommodate
1894	  the documented boot protocol using a device tree.
1895
1896	  Beware that there is very little in terms of protection against
1897	  this option being confused by leftover garbage in memory that might
1898	  look like a DTB header after a reboot if no actual DTB is appended
1899	  to zImage.  Do not leave this option active in a production kernel
1900	  if you don't intend to always append a DTB.  Proper passing of the
1901	  location into r2 of a bootloader provided DTB is always preferable
1902	  to this option.
1903
1904config ARM_ATAG_DTB_COMPAT
1905	bool "Supplement the appended DTB with traditional ATAG information"
1906	depends on ARM_APPENDED_DTB
1907	help
1908	  Some old bootloaders can't be updated to a DTB capable one, yet
1909	  they provide ATAGs with memory configuration, the ramdisk address,
1910	  the kernel cmdline string, etc.  Such information is dynamically
1911	  provided by the bootloader and can't always be stored in a static
1912	  DTB.  To allow a device tree enabled kernel to be used with such
1913	  bootloaders, this option allows zImage to extract the information
1914	  from the ATAG list and store it at run time into the appended DTB.
1915
1916choice
1917	prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1918	default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1919
1920config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1921	bool "Use bootloader kernel arguments if available"
1922	help
1923	  Uses the command-line options passed by the boot loader instead of
1924	  the device tree bootargs property. If the boot loader doesn't provide
1925	  any, the device tree bootargs property will be used.
1926
1927config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1928	bool "Extend with bootloader kernel arguments"
1929	help
1930	  The command-line arguments provided by the boot loader will be
1931	  appended to the the device tree bootargs property.
1932
1933endchoice
1934
1935config CMDLINE
1936	string "Default kernel command string"
1937	default ""
1938	help
1939	  On some architectures (EBSA110 and CATS), there is currently no way
1940	  for the boot loader to pass arguments to the kernel. For these
1941	  architectures, you should supply some command-line options at build
1942	  time by entering them here. As a minimum, you should specify the
1943	  memory size and the root device (e.g., mem=64M root=/dev/nfs).
1944
1945choice
1946	prompt "Kernel command line type" if CMDLINE != ""
1947	default CMDLINE_FROM_BOOTLOADER
1948	depends on ATAGS
1949
1950config CMDLINE_FROM_BOOTLOADER
1951	bool "Use bootloader kernel arguments if available"
1952	help
1953	  Uses the command-line options passed by the boot loader. If
1954	  the boot loader doesn't provide any, the default kernel command
1955	  string provided in CMDLINE will be used.
1956
1957config CMDLINE_EXTEND
1958	bool "Extend bootloader kernel arguments"
1959	help
1960	  The command-line arguments provided by the boot loader will be
1961	  appended to the default kernel command string.
1962
1963config CMDLINE_FORCE
1964	bool "Always use the default kernel command string"
1965	help
1966	  Always use the default kernel command string, even if the boot
1967	  loader passes other arguments to the kernel.
1968	  This is useful if you cannot or don't want to change the
1969	  command-line options your boot loader passes to the kernel.
1970endchoice
1971
1972config XIP_KERNEL
1973	bool "Kernel Execute-In-Place from ROM"
1974	depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1975	help
1976	  Execute-In-Place allows the kernel to run from non-volatile storage
1977	  directly addressable by the CPU, such as NOR flash. This saves RAM
1978	  space since the text section of the kernel is not loaded from flash
1979	  to RAM.  Read-write sections, such as the data section and stack,
1980	  are still copied to RAM.  The XIP kernel is not compressed since
1981	  it has to run directly from flash, so it will take more space to
1982	  store it.  The flash address used to link the kernel object files,
1983	  and for storing it, is configuration dependent. Therefore, if you
1984	  say Y here, you must know the proper physical address where to
1985	  store the kernel image depending on your own flash memory usage.
1986
1987	  Also note that the make target becomes "make xipImage" rather than
1988	  "make zImage" or "make Image".  The final kernel binary to put in
1989	  ROM memory will be arch/arm/boot/xipImage.
1990
1991	  If unsure, say N.
1992
1993config XIP_PHYS_ADDR
1994	hex "XIP Kernel Physical Location"
1995	depends on XIP_KERNEL
1996	default "0x00080000"
1997	help
1998	  This is the physical address in your flash memory the kernel will
1999	  be linked for and stored to.  This address is dependent on your
2000	  own flash usage.
2001
2002config XIP_DEFLATED_DATA
2003	bool "Store kernel .data section compressed in ROM"
2004	depends on XIP_KERNEL
2005	select ZLIB_INFLATE
2006	help
2007	  Before the kernel is actually executed, its .data section has to be
2008	  copied to RAM from ROM. This option allows for storing that data
2009	  in compressed form and decompressed to RAM rather than merely being
2010	  copied, saving some precious ROM space. A possible drawback is a
2011	  slightly longer boot delay.
2012
2013config KEXEC
2014	bool "Kexec system call (EXPERIMENTAL)"
2015	depends on (!SMP || PM_SLEEP_SMP)
2016	depends on !CPU_V7M
2017	select KEXEC_CORE
2018	help
2019	  kexec is a system call that implements the ability to shutdown your
2020	  current kernel, and to start another kernel.  It is like a reboot
2021	  but it is independent of the system firmware.   And like a reboot
2022	  you can start any kernel with it, not just Linux.
2023
2024	  It is an ongoing process to be certain the hardware in a machine
2025	  is properly shutdown, so do not be surprised if this code does not
2026	  initially work for you.
2027
2028config ATAGS_PROC
2029	bool "Export atags in procfs"
2030	depends on ATAGS && KEXEC
2031	default y
2032	help
2033	  Should the atags used to boot the kernel be exported in an "atags"
2034	  file in procfs. Useful with kexec.
2035
2036config CRASH_DUMP
2037	bool "Build kdump crash kernel (EXPERIMENTAL)"
2038	help
2039	  Generate crash dump after being started by kexec. This should
2040	  be normally only set in special crash dump kernels which are
2041	  loaded in the main kernel with kexec-tools into a specially
2042	  reserved region and then later executed after a crash by
2043	  kdump/kexec. The crash dump kernel must be compiled to a
2044	  memory address not used by the main kernel
2045
2046	  For more details see Documentation/kdump/kdump.txt
2047
2048config AUTO_ZRELADDR
2049	bool "Auto calculation of the decompressed kernel image address"
2050	help
2051	  ZRELADDR is the physical address where the decompressed kernel
2052	  image will be placed. If AUTO_ZRELADDR is selected, the address
2053	  will be determined at run-time by masking the current IP with
2054	  0xf8000000. This assumes the zImage being placed in the first 128MB
2055	  from start of memory.
2056
2057config EFI_STUB
2058	bool
2059
2060config EFI
2061	bool "UEFI runtime support"
2062	depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2063	select UCS2_STRING
2064	select EFI_PARAMS_FROM_FDT
2065	select EFI_STUB
2066	select EFI_ARMSTUB
2067	select EFI_RUNTIME_WRAPPERS
2068	---help---
2069	  This option provides support for runtime services provided
2070	  by UEFI firmware (such as non-volatile variables, realtime
2071	  clock, and platform reset). A UEFI stub is also provided to
2072	  allow the kernel to be booted as an EFI application. This
2073	  is only useful for kernels that may run on systems that have
2074	  UEFI firmware.
2075
2076config DMI
2077	bool "Enable support for SMBIOS (DMI) tables"
2078	depends on EFI
2079	default y
2080	help
2081	  This enables SMBIOS/DMI feature for systems.
2082
2083	  This option is only useful on systems that have UEFI firmware.
2084	  However, even with this option, the resultant kernel should
2085	  continue to boot on existing non-UEFI platforms.
2086
2087	  NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2088	  i.e., the the practice of identifying the platform via DMI to
2089	  decide whether certain workarounds for buggy hardware and/or
2090	  firmware need to be enabled. This would require the DMI subsystem
2091	  to be enabled much earlier than we do on ARM, which is non-trivial.
2092
2093endmenu
2094
2095menu "CPU Power Management"
2096
2097source "drivers/cpufreq/Kconfig"
2098
2099source "drivers/cpuidle/Kconfig"
2100
2101endmenu
2102
2103menu "Floating point emulation"
2104
2105comment "At least one emulation must be selected"
2106
2107config FPE_NWFPE
2108	bool "NWFPE math emulation"
2109	depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2110	---help---
2111	  Say Y to include the NWFPE floating point emulator in the kernel.
2112	  This is necessary to run most binaries. Linux does not currently
2113	  support floating point hardware so you need to say Y here even if
2114	  your machine has an FPA or floating point co-processor podule.
2115
2116	  You may say N here if you are going to load the Acorn FPEmulator
2117	  early in the bootup.
2118
2119config FPE_NWFPE_XP
2120	bool "Support extended precision"
2121	depends on FPE_NWFPE
2122	help
2123	  Say Y to include 80-bit support in the kernel floating-point
2124	  emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2125	  Note that gcc does not generate 80-bit operations by default,
2126	  so in most cases this option only enlarges the size of the
2127	  floating point emulator without any good reason.
2128
2129	  You almost surely want to say N here.
2130
2131config FPE_FASTFPE
2132	bool "FastFPE math emulation (EXPERIMENTAL)"
2133	depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2134	---help---
2135	  Say Y here to include the FAST floating point emulator in the kernel.
2136	  This is an experimental much faster emulator which now also has full
2137	  precision for the mantissa.  It does not support any exceptions.
2138	  It is very simple, and approximately 3-6 times faster than NWFPE.
2139
2140	  It should be sufficient for most programs.  It may be not suitable
2141	  for scientific calculations, but you have to check this for yourself.
2142	  If you do not feel you need a faster FP emulation you should better
2143	  choose NWFPE.
2144
2145config VFP
2146	bool "VFP-format floating point maths"
2147	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2148	help
2149	  Say Y to include VFP support code in the kernel. This is needed
2150	  if your hardware includes a VFP unit.
2151
2152	  Please see <file:Documentation/arm/VFP/release-notes.txt> for
2153	  release notes and additional status information.
2154
2155	  Say N if your target does not have VFP hardware.
2156
2157config VFPv3
2158	bool
2159	depends on VFP
2160	default y if CPU_V7
2161
2162config NEON
2163	bool "Advanced SIMD (NEON) Extension support"
2164	depends on VFPv3 && CPU_V7
2165	help
2166	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2167	  Extension.
2168
2169config KERNEL_MODE_NEON
2170	bool "Support for NEON in kernel mode"
2171	depends on NEON && AEABI
2172	help
2173	  Say Y to include support for NEON in kernel mode.
2174
2175endmenu
2176
2177menu "Userspace binary formats"
2178
2179source "fs/Kconfig.binfmt"
2180
2181endmenu
2182
2183menu "Power management options"
2184
2185source "kernel/power/Kconfig"
2186
2187config ARCH_SUSPEND_POSSIBLE
2188	depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2189		CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2190	def_bool y
2191
2192config ARM_CPU_SUSPEND
2193	def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2194	depends on ARCH_SUSPEND_POSSIBLE
2195
2196config ARCH_HIBERNATION_POSSIBLE
2197	bool
2198	depends on MMU
2199	default y if ARCH_SUSPEND_POSSIBLE
2200
2201endmenu
2202
2203source "net/Kconfig"
2204
2205source "drivers/Kconfig"
2206
2207source "drivers/firmware/Kconfig"
2208
2209source "fs/Kconfig"
2210
2211source "arch/arm/Kconfig.debug"
2212
2213source "security/Kconfig"
2214
2215source "crypto/Kconfig"
2216if CRYPTO
2217source "arch/arm/crypto/Kconfig"
2218endif
2219
2220source "lib/Kconfig"
2221
2222source "arch/arm/kvm/Kconfig"
2223