1config ARM 2 bool 3 default y 4 select ARCH_CLOCKSOURCE_DATA 5 select ARCH_HAS_DEVMEM_IS_ALLOWED 6 select ARCH_HAS_ELF_RANDOMIZE 7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 8 select ARCH_HAVE_CUSTOM_GPIO_H 9 select ARCH_HAS_GCOV_PROFILE_ALL 10 select ARCH_MIGHT_HAVE_PC_PARPORT 11 select ARCH_SUPPORTS_ATOMIC_RMW 12 select ARCH_USE_BUILTIN_BSWAP 13 select ARCH_USE_CMPXCHG_LOCKREF 14 select ARCH_WANT_IPC_PARSE_VERSION 15 select BUILDTIME_EXTABLE_SORT if MMU 16 select CLONE_BACKWARDS 17 select CPU_PM if (SUSPEND || CPU_IDLE) 18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 19 select EDAC_SUPPORT 20 select EDAC_ATOMIC_SCRUB 21 select GENERIC_ALLOCATOR 22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 24 select GENERIC_EARLY_IOREMAP 25 select GENERIC_IDLE_POLL_SETUP 26 select GENERIC_IRQ_PROBE 27 select GENERIC_IRQ_SHOW 28 select GENERIC_IRQ_SHOW_LEVEL 29 select GENERIC_PCI_IOMAP 30 select GENERIC_SCHED_CLOCK 31 select GENERIC_SMP_IDLE_THREAD 32 select GENERIC_STRNCPY_FROM_USER 33 select GENERIC_STRNLEN_USER 34 select HANDLE_DOMAIN_IRQ 35 select HARDIRQS_SW_RESEND 36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 38 select HAVE_ARCH_HARDENED_USERCOPY 39 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 40 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 41 select HAVE_ARCH_MMAP_RND_BITS if MMU 42 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 43 select HAVE_ARCH_TRACEHOOK 44 select HAVE_ARM_SMCCC if CPU_V7 45 select HAVE_CBPF_JIT 46 select HAVE_CC_STACKPROTECTOR 47 select HAVE_CONTEXT_TRACKING 48 select HAVE_C_RECORDMCOUNT 49 select HAVE_DEBUG_KMEMLEAK 50 select HAVE_DMA_API_DEBUG 51 select HAVE_DMA_CONTIGUOUS if MMU 52 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU 53 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 54 select HAVE_EXIT_THREAD 55 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 56 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 57 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 58 select HAVE_GCC_PLUGINS 59 select HAVE_GENERIC_DMA_COHERENT 60 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 61 select HAVE_IDE if PCI || ISA || PCMCIA 62 select HAVE_IRQ_TIME_ACCOUNTING 63 select HAVE_KERNEL_GZIP 64 select HAVE_KERNEL_LZ4 65 select HAVE_KERNEL_LZMA 66 select HAVE_KERNEL_LZO 67 select HAVE_KERNEL_XZ 68 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 69 select HAVE_KRETPROBES if (HAVE_KPROBES) 70 select HAVE_MEMBLOCK 71 select HAVE_MOD_ARCH_SPECIFIC 72 select HAVE_NMI 73 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 74 select HAVE_OPTPROBES if !THUMB2_KERNEL 75 select HAVE_PERF_EVENTS 76 select HAVE_PERF_REGS 77 select HAVE_PERF_USER_STACK_DUMP 78 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 79 select HAVE_REGS_AND_STACK_ACCESS_API 80 select HAVE_SYSCALL_TRACEPOINTS 81 select HAVE_UID16 82 select HAVE_VIRT_CPU_ACCOUNTING_GEN 83 select IRQ_FORCED_THREADING 84 select MODULES_USE_ELF_REL 85 select NO_BOOTMEM 86 select OF_EARLY_FLATTREE if OF 87 select OF_RESERVED_MEM if OF 88 select OLD_SIGACTION 89 select OLD_SIGSUSPEND3 90 select PERF_USE_VMALLOC 91 select RTC_LIB 92 select SYS_SUPPORTS_APM_EMULATION 93 # Above selects are sorted alphabetically; please add new ones 94 # according to that. Thanks. 95 help 96 The ARM series is a line of low-power-consumption RISC chip designs 97 licensed by ARM Ltd and targeted at embedded applications and 98 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 99 manufactured, but legacy ARM-based PC hardware remains popular in 100 Europe. There is an ARM Linux project with a web page at 101 <http://www.arm.linux.org.uk/>. 102 103config ARM_HAS_SG_CHAIN 104 select ARCH_HAS_SG_CHAIN 105 bool 106 107config NEED_SG_DMA_LENGTH 108 bool 109 110config ARM_DMA_USE_IOMMU 111 bool 112 select ARM_HAS_SG_CHAIN 113 select NEED_SG_DMA_LENGTH 114 115if ARM_DMA_USE_IOMMU 116 117config ARM_DMA_IOMMU_ALIGNMENT 118 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 119 range 4 9 120 default 8 121 help 122 DMA mapping framework by default aligns all buffers to the smallest 123 PAGE_SIZE order which is greater than or equal to the requested buffer 124 size. This works well for buffers up to a few hundreds kilobytes, but 125 for larger buffers it just a waste of address space. Drivers which has 126 relatively small addressing window (like 64Mib) might run out of 127 virtual space with just a few allocations. 128 129 With this parameter you can specify the maximum PAGE_SIZE order for 130 DMA IOMMU buffers. Larger buffers will be aligned only to this 131 specified order. The order is expressed as a power of two multiplied 132 by the PAGE_SIZE. 133 134endif 135 136config MIGHT_HAVE_PCI 137 bool 138 139config SYS_SUPPORTS_APM_EMULATION 140 bool 141 142config HAVE_TCM 143 bool 144 select GENERIC_ALLOCATOR 145 146config HAVE_PROC_CPU 147 bool 148 149config NO_IOPORT_MAP 150 bool 151 152config EISA 153 bool 154 ---help--- 155 The Extended Industry Standard Architecture (EISA) bus was 156 developed as an open alternative to the IBM MicroChannel bus. 157 158 The EISA bus provided some of the features of the IBM MicroChannel 159 bus while maintaining backward compatibility with cards made for 160 the older ISA bus. The EISA bus saw limited use between 1988 and 161 1995 when it was made obsolete by the PCI bus. 162 163 Say Y here if you are building a kernel for an EISA-based machine. 164 165 Otherwise, say N. 166 167config SBUS 168 bool 169 170config STACKTRACE_SUPPORT 171 bool 172 default y 173 174config LOCKDEP_SUPPORT 175 bool 176 default y 177 178config TRACE_IRQFLAGS_SUPPORT 179 bool 180 default !CPU_V7M 181 182config RWSEM_XCHGADD_ALGORITHM 183 bool 184 default y 185 186config ARCH_HAS_ILOG2_U32 187 bool 188 189config ARCH_HAS_ILOG2_U64 190 bool 191 192config ARCH_HAS_BANDGAP 193 bool 194 195config FIX_EARLYCON_MEM 196 def_bool y if MMU 197 198config GENERIC_HWEIGHT 199 bool 200 default y 201 202config GENERIC_CALIBRATE_DELAY 203 bool 204 default y 205 206config ARCH_MAY_HAVE_PC_FDC 207 bool 208 209config ZONE_DMA 210 bool 211 212config NEED_DMA_MAP_STATE 213 def_bool y 214 215config ARCH_SUPPORTS_UPROBES 216 def_bool y 217 218config ARCH_HAS_DMA_SET_COHERENT_MASK 219 bool 220 221config GENERIC_ISA_DMA 222 bool 223 224config FIQ 225 bool 226 227config NEED_RET_TO_USER 228 bool 229 230config ARCH_MTD_XIP 231 bool 232 233config VECTORS_BASE 234 hex 235 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 236 default DRAM_BASE if REMAP_VECTORS_TO_RAM 237 default 0x00000000 238 help 239 The base address of exception vectors. This must be two pages 240 in size. 241 242config ARM_PATCH_PHYS_VIRT 243 bool "Patch physical to virtual translations at runtime" if EMBEDDED 244 default y 245 depends on !XIP_KERNEL && MMU 246 help 247 Patch phys-to-virt and virt-to-phys translation functions at 248 boot and module load time according to the position of the 249 kernel in system memory. 250 251 This can only be used with non-XIP MMU kernels where the base 252 of physical memory is at a 16MB boundary. 253 254 Only disable this option if you know that you do not require 255 this feature (eg, building a kernel for a single machine) and 256 you need to shrink the kernel to the minimal size. 257 258config NEED_MACH_IO_H 259 bool 260 help 261 Select this when mach/io.h is required to provide special 262 definitions for this platform. The need for mach/io.h should 263 be avoided when possible. 264 265config NEED_MACH_MEMORY_H 266 bool 267 help 268 Select this when mach/memory.h is required to provide special 269 definitions for this platform. The need for mach/memory.h should 270 be avoided when possible. 271 272config PHYS_OFFSET 273 hex "Physical address of main memory" if MMU 274 depends on !ARM_PATCH_PHYS_VIRT 275 default DRAM_BASE if !MMU 276 default 0x00000000 if ARCH_EBSA110 || \ 277 ARCH_FOOTBRIDGE || \ 278 ARCH_INTEGRATOR || \ 279 ARCH_IOP13XX || \ 280 ARCH_KS8695 || \ 281 ARCH_REALVIEW 282 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 283 default 0x20000000 if ARCH_S5PV210 284 default 0xc0000000 if ARCH_SA1100 285 help 286 Please provide the physical address corresponding to the 287 location of main memory in your system. 288 289config GENERIC_BUG 290 def_bool y 291 depends on BUG 292 293config PGTABLE_LEVELS 294 int 295 default 3 if ARM_LPAE 296 default 2 297 298source "init/Kconfig" 299 300source "kernel/Kconfig.freezer" 301 302menu "System Type" 303 304config MMU 305 bool "MMU-based Paged Memory Management Support" 306 default y 307 help 308 Select if you want MMU-based virtualised addressing space 309 support by paged memory management. If unsure, say 'Y'. 310 311config ARCH_MMAP_RND_BITS_MIN 312 default 8 313 314config ARCH_MMAP_RND_BITS_MAX 315 default 14 if PAGE_OFFSET=0x40000000 316 default 15 if PAGE_OFFSET=0x80000000 317 default 16 318 319# 320# The "ARM system type" choice list is ordered alphabetically by option 321# text. Please add new entries in the option alphabetic order. 322# 323choice 324 prompt "ARM system type" 325 default ARM_SINGLE_ARMV7M if !MMU 326 default ARCH_MULTIPLATFORM if MMU 327 328config ARCH_MULTIPLATFORM 329 bool "Allow multiple platforms to be selected" 330 depends on MMU 331 select ARM_HAS_SG_CHAIN 332 select ARM_PATCH_PHYS_VIRT 333 select AUTO_ZRELADDR 334 select CLKSRC_OF 335 select COMMON_CLK 336 select GENERIC_CLOCKEVENTS 337 select MIGHT_HAVE_PCI 338 select MULTI_IRQ_HANDLER 339 select PCI_DOMAINS if PCI 340 select SPARSE_IRQ 341 select USE_OF 342 343config ARM_SINGLE_ARMV7M 344 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 345 depends on !MMU 346 select ARM_NVIC 347 select AUTO_ZRELADDR 348 select CLKSRC_OF 349 select COMMON_CLK 350 select CPU_V7M 351 select GENERIC_CLOCKEVENTS 352 select NO_IOPORT_MAP 353 select SPARSE_IRQ 354 select USE_OF 355 356config ARCH_GEMINI 357 bool "Cortina Systems Gemini" 358 select CLKSRC_MMIO 359 select CPU_FA526 360 select GENERIC_CLOCKEVENTS 361 select GPIOLIB 362 help 363 Support for the Cortina Systems Gemini family SoCs 364 365config ARCH_EBSA110 366 bool "EBSA-110" 367 select ARCH_USES_GETTIMEOFFSET 368 select CPU_SA110 369 select ISA 370 select NEED_MACH_IO_H 371 select NEED_MACH_MEMORY_H 372 select NO_IOPORT_MAP 373 help 374 This is an evaluation board for the StrongARM processor available 375 from Digital. It has limited hardware on-board, including an 376 Ethernet interface, two PCMCIA sockets, two serial ports and a 377 parallel port. 378 379config ARCH_EP93XX 380 bool "EP93xx-based" 381 select ARCH_HAS_HOLES_MEMORYMODEL 382 select ARM_AMBA 383 select ARM_PATCH_PHYS_VIRT 384 select ARM_VIC 385 select AUTO_ZRELADDR 386 select CLKDEV_LOOKUP 387 select CLKSRC_MMIO 388 select CPU_ARM920T 389 select GENERIC_CLOCKEVENTS 390 select GPIOLIB 391 help 392 This enables support for the Cirrus EP93xx series of CPUs. 393 394config ARCH_FOOTBRIDGE 395 bool "FootBridge" 396 select CPU_SA110 397 select FOOTBRIDGE 398 select GENERIC_CLOCKEVENTS 399 select HAVE_IDE 400 select NEED_MACH_IO_H if !MMU 401 select NEED_MACH_MEMORY_H 402 help 403 Support for systems based on the DC21285 companion chip 404 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 405 406config ARCH_NETX 407 bool "Hilscher NetX based" 408 select ARM_VIC 409 select CLKSRC_MMIO 410 select CPU_ARM926T 411 select GENERIC_CLOCKEVENTS 412 help 413 This enables support for systems based on the Hilscher NetX Soc 414 415config ARCH_IOP13XX 416 bool "IOP13xx-based" 417 depends on MMU 418 select CPU_XSC3 419 select NEED_MACH_MEMORY_H 420 select NEED_RET_TO_USER 421 select PCI 422 select PLAT_IOP 423 select VMSPLIT_1G 424 select SPARSE_IRQ 425 help 426 Support for Intel's IOP13XX (XScale) family of processors. 427 428config ARCH_IOP32X 429 bool "IOP32x-based" 430 depends on MMU 431 select CPU_XSCALE 432 select GPIO_IOP 433 select GPIOLIB 434 select NEED_RET_TO_USER 435 select PCI 436 select PLAT_IOP 437 help 438 Support for Intel's 80219 and IOP32X (XScale) family of 439 processors. 440 441config ARCH_IOP33X 442 bool "IOP33x-based" 443 depends on MMU 444 select CPU_XSCALE 445 select GPIO_IOP 446 select GPIOLIB 447 select NEED_RET_TO_USER 448 select PCI 449 select PLAT_IOP 450 help 451 Support for Intel's IOP33X (XScale) family of processors. 452 453config ARCH_IXP4XX 454 bool "IXP4xx-based" 455 depends on MMU 456 select ARCH_HAS_DMA_SET_COHERENT_MASK 457 select ARCH_SUPPORTS_BIG_ENDIAN 458 select CLKSRC_MMIO 459 select CPU_XSCALE 460 select DMABOUNCE if PCI 461 select GENERIC_CLOCKEVENTS 462 select GPIOLIB 463 select MIGHT_HAVE_PCI 464 select NEED_MACH_IO_H 465 select USB_EHCI_BIG_ENDIAN_DESC 466 select USB_EHCI_BIG_ENDIAN_MMIO 467 help 468 Support for Intel's IXP4XX (XScale) family of processors. 469 470config ARCH_DOVE 471 bool "Marvell Dove" 472 select CPU_PJ4 473 select GENERIC_CLOCKEVENTS 474 select GPIOLIB 475 select MIGHT_HAVE_PCI 476 select MULTI_IRQ_HANDLER 477 select MVEBU_MBUS 478 select PINCTRL 479 select PINCTRL_DOVE 480 select PLAT_ORION_LEGACY 481 select SPARSE_IRQ 482 select PM_GENERIC_DOMAINS if PM 483 help 484 Support for the Marvell Dove SoC 88AP510 485 486config ARCH_KS8695 487 bool "Micrel/Kendin KS8695" 488 select CLKSRC_MMIO 489 select CPU_ARM922T 490 select GENERIC_CLOCKEVENTS 491 select GPIOLIB 492 select NEED_MACH_MEMORY_H 493 help 494 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 495 System-on-Chip devices. 496 497config ARCH_W90X900 498 bool "Nuvoton W90X900 CPU" 499 select CLKDEV_LOOKUP 500 select CLKSRC_MMIO 501 select CPU_ARM926T 502 select GENERIC_CLOCKEVENTS 503 select GPIOLIB 504 help 505 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 506 At present, the w90x900 has been renamed nuc900, regarding 507 the ARM series product line, you can login the following 508 link address to know more. 509 510 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 511 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 512 513config ARCH_LPC32XX 514 bool "NXP LPC32XX" 515 select ARM_AMBA 516 select CLKDEV_LOOKUP 517 select CLKSRC_LPC32XX 518 select COMMON_CLK 519 select CPU_ARM926T 520 select GENERIC_CLOCKEVENTS 521 select GPIOLIB 522 select MULTI_IRQ_HANDLER 523 select SPARSE_IRQ 524 select USE_OF 525 help 526 Support for the NXP LPC32XX family of processors 527 528config ARCH_PXA 529 bool "PXA2xx/PXA3xx-based" 530 depends on MMU 531 select ARCH_MTD_XIP 532 select ARM_CPU_SUSPEND if PM 533 select AUTO_ZRELADDR 534 select COMMON_CLK 535 select CLKDEV_LOOKUP 536 select CLKSRC_PXA 537 select CLKSRC_MMIO 538 select CLKSRC_OF 539 select CPU_XSCALE if !CPU_XSC3 540 select GENERIC_CLOCKEVENTS 541 select GPIO_PXA 542 select GPIOLIB 543 select HAVE_IDE 544 select IRQ_DOMAIN 545 select MULTI_IRQ_HANDLER 546 select PLAT_PXA 547 select SPARSE_IRQ 548 help 549 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 550 551config ARCH_RPC 552 bool "RiscPC" 553 depends on MMU 554 select ARCH_ACORN 555 select ARCH_MAY_HAVE_PC_FDC 556 select ARCH_SPARSEMEM_ENABLE 557 select ARCH_USES_GETTIMEOFFSET 558 select CPU_SA110 559 select FIQ 560 select HAVE_IDE 561 select HAVE_PATA_PLATFORM 562 select ISA_DMA_API 563 select NEED_MACH_IO_H 564 select NEED_MACH_MEMORY_H 565 select NO_IOPORT_MAP 566 help 567 On the Acorn Risc-PC, Linux can support the internal IDE disk and 568 CD-ROM interface, serial and parallel port, and the floppy drive. 569 570config ARCH_SA1100 571 bool "SA1100-based" 572 select ARCH_MTD_XIP 573 select ARCH_SPARSEMEM_ENABLE 574 select CLKDEV_LOOKUP 575 select CLKSRC_MMIO 576 select CLKSRC_PXA 577 select CLKSRC_OF if OF 578 select CPU_FREQ 579 select CPU_SA1100 580 select GENERIC_CLOCKEVENTS 581 select GPIOLIB 582 select HAVE_IDE 583 select IRQ_DOMAIN 584 select ISA 585 select MULTI_IRQ_HANDLER 586 select NEED_MACH_MEMORY_H 587 select SPARSE_IRQ 588 help 589 Support for StrongARM 11x0 based boards. 590 591config ARCH_S3C24XX 592 bool "Samsung S3C24XX SoCs" 593 select ATAGS 594 select CLKDEV_LOOKUP 595 select CLKSRC_SAMSUNG_PWM 596 select GENERIC_CLOCKEVENTS 597 select GPIO_SAMSUNG 598 select GPIOLIB 599 select HAVE_S3C2410_I2C if I2C 600 select HAVE_S3C2410_WATCHDOG if WATCHDOG 601 select HAVE_S3C_RTC if RTC_CLASS 602 select MULTI_IRQ_HANDLER 603 select NEED_MACH_IO_H 604 select SAMSUNG_ATAGS 605 help 606 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 607 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 608 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 609 Samsung SMDK2410 development board (and derivatives). 610 611config ARCH_DAVINCI 612 bool "TI DaVinci" 613 select ARCH_HAS_HOLES_MEMORYMODEL 614 select CLKDEV_LOOKUP 615 select CPU_ARM926T 616 select GENERIC_ALLOCATOR 617 select GENERIC_CLOCKEVENTS 618 select GENERIC_IRQ_CHIP 619 select GPIOLIB 620 select HAVE_IDE 621 select USE_OF 622 select ZONE_DMA 623 help 624 Support for TI's DaVinci platform. 625 626config ARCH_OMAP1 627 bool "TI OMAP1" 628 depends on MMU 629 select ARCH_HAS_HOLES_MEMORYMODEL 630 select ARCH_OMAP 631 select CLKDEV_LOOKUP 632 select CLKSRC_MMIO 633 select GENERIC_CLOCKEVENTS 634 select GENERIC_IRQ_CHIP 635 select GPIOLIB 636 select HAVE_IDE 637 select IRQ_DOMAIN 638 select MULTI_IRQ_HANDLER 639 select NEED_MACH_IO_H if PCCARD 640 select NEED_MACH_MEMORY_H 641 select SPARSE_IRQ 642 help 643 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 644 645endchoice 646 647menu "Multiple platform selection" 648 depends on ARCH_MULTIPLATFORM 649 650comment "CPU Core family selection" 651 652config ARCH_MULTI_V4 653 bool "ARMv4 based platforms (FA526)" 654 depends on !ARCH_MULTI_V6_V7 655 select ARCH_MULTI_V4_V5 656 select CPU_FA526 657 658config ARCH_MULTI_V4T 659 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 660 depends on !ARCH_MULTI_V6_V7 661 select ARCH_MULTI_V4_V5 662 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 663 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 664 CPU_ARM925T || CPU_ARM940T) 665 666config ARCH_MULTI_V5 667 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 668 depends on !ARCH_MULTI_V6_V7 669 select ARCH_MULTI_V4_V5 670 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 671 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 672 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 673 674config ARCH_MULTI_V4_V5 675 bool 676 677config ARCH_MULTI_V6 678 bool "ARMv6 based platforms (ARM11)" 679 select ARCH_MULTI_V6_V7 680 select CPU_V6K 681 682config ARCH_MULTI_V7 683 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 684 default y 685 select ARCH_MULTI_V6_V7 686 select CPU_V7 687 select HAVE_SMP 688 689config ARCH_MULTI_V6_V7 690 bool 691 select MIGHT_HAVE_CACHE_L2X0 692 693config ARCH_MULTI_CPU_AUTO 694 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 695 select ARCH_MULTI_V5 696 697endmenu 698 699config ARCH_VIRT 700 bool "Dummy Virtual Machine" 701 depends on ARCH_MULTI_V7 702 select ARM_AMBA 703 select ARM_GIC 704 select ARM_GIC_V2M if PCI 705 select ARM_GIC_V3 706 select ARM_GIC_V3_ITS if PCI 707 select ARM_PSCI 708 select HAVE_ARM_ARCH_TIMER 709 710# 711# This is sorted alphabetically by mach-* pathname. However, plat-* 712# Kconfigs may be included either alphabetically (according to the 713# plat- suffix) or along side the corresponding mach-* source. 714# 715source "arch/arm/mach-mvebu/Kconfig" 716 717source "arch/arm/mach-alpine/Kconfig" 718 719source "arch/arm/mach-artpec/Kconfig" 720 721source "arch/arm/mach-asm9260/Kconfig" 722 723source "arch/arm/mach-at91/Kconfig" 724 725source "arch/arm/mach-axxia/Kconfig" 726 727source "arch/arm/mach-bcm/Kconfig" 728 729source "arch/arm/mach-berlin/Kconfig" 730 731source "arch/arm/mach-clps711x/Kconfig" 732 733source "arch/arm/mach-cns3xxx/Kconfig" 734 735source "arch/arm/mach-davinci/Kconfig" 736 737source "arch/arm/mach-digicolor/Kconfig" 738 739source "arch/arm/mach-dove/Kconfig" 740 741source "arch/arm/mach-ep93xx/Kconfig" 742 743source "arch/arm/mach-footbridge/Kconfig" 744 745source "arch/arm/mach-gemini/Kconfig" 746 747source "arch/arm/mach-highbank/Kconfig" 748 749source "arch/arm/mach-hisi/Kconfig" 750 751source "arch/arm/mach-integrator/Kconfig" 752 753source "arch/arm/mach-iop32x/Kconfig" 754 755source "arch/arm/mach-iop33x/Kconfig" 756 757source "arch/arm/mach-iop13xx/Kconfig" 758 759source "arch/arm/mach-ixp4xx/Kconfig" 760 761source "arch/arm/mach-keystone/Kconfig" 762 763source "arch/arm/mach-ks8695/Kconfig" 764 765source "arch/arm/mach-meson/Kconfig" 766 767source "arch/arm/mach-moxart/Kconfig" 768 769source "arch/arm/mach-aspeed/Kconfig" 770 771source "arch/arm/mach-mv78xx0/Kconfig" 772 773source "arch/arm/mach-imx/Kconfig" 774 775source "arch/arm/mach-mediatek/Kconfig" 776 777source "arch/arm/mach-mxs/Kconfig" 778 779source "arch/arm/mach-netx/Kconfig" 780 781source "arch/arm/mach-nomadik/Kconfig" 782 783source "arch/arm/mach-nspire/Kconfig" 784 785source "arch/arm/plat-omap/Kconfig" 786 787source "arch/arm/mach-omap1/Kconfig" 788 789source "arch/arm/mach-omap2/Kconfig" 790 791source "arch/arm/mach-orion5x/Kconfig" 792 793source "arch/arm/mach-picoxcell/Kconfig" 794 795source "arch/arm/mach-pxa/Kconfig" 796source "arch/arm/plat-pxa/Kconfig" 797 798source "arch/arm/mach-mmp/Kconfig" 799 800source "arch/arm/mach-oxnas/Kconfig" 801 802source "arch/arm/mach-qcom/Kconfig" 803 804source "arch/arm/mach-realview/Kconfig" 805 806source "arch/arm/mach-rockchip/Kconfig" 807 808source "arch/arm/mach-sa1100/Kconfig" 809 810source "arch/arm/mach-socfpga/Kconfig" 811 812source "arch/arm/mach-spear/Kconfig" 813 814source "arch/arm/mach-sti/Kconfig" 815 816source "arch/arm/mach-s3c24xx/Kconfig" 817 818source "arch/arm/mach-s3c64xx/Kconfig" 819 820source "arch/arm/mach-s5pv210/Kconfig" 821 822source "arch/arm/mach-exynos/Kconfig" 823source "arch/arm/plat-samsung/Kconfig" 824 825source "arch/arm/mach-shmobile/Kconfig" 826 827source "arch/arm/mach-sunxi/Kconfig" 828 829source "arch/arm/mach-prima2/Kconfig" 830 831source "arch/arm/mach-tango/Kconfig" 832 833source "arch/arm/mach-tegra/Kconfig" 834 835source "arch/arm/mach-u300/Kconfig" 836 837source "arch/arm/mach-uniphier/Kconfig" 838 839source "arch/arm/mach-ux500/Kconfig" 840 841source "arch/arm/mach-versatile/Kconfig" 842 843source "arch/arm/mach-vexpress/Kconfig" 844source "arch/arm/plat-versatile/Kconfig" 845 846source "arch/arm/mach-vt8500/Kconfig" 847 848source "arch/arm/mach-w90x900/Kconfig" 849 850source "arch/arm/mach-zx/Kconfig" 851 852source "arch/arm/mach-zynq/Kconfig" 853 854# ARMv7-M architecture 855config ARCH_EFM32 856 bool "Energy Micro efm32" 857 depends on ARM_SINGLE_ARMV7M 858 select GPIOLIB 859 help 860 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 861 processors. 862 863config ARCH_LPC18XX 864 bool "NXP LPC18xx/LPC43xx" 865 depends on ARM_SINGLE_ARMV7M 866 select ARCH_HAS_RESET_CONTROLLER 867 select ARM_AMBA 868 select CLKSRC_LPC32XX 869 select PINCTRL 870 help 871 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 872 high performance microcontrollers. 873 874config ARCH_STM32 875 bool "STMicrolectronics STM32" 876 depends on ARM_SINGLE_ARMV7M 877 select ARCH_HAS_RESET_CONTROLLER 878 select ARMV7M_SYSTICK 879 select CLKSRC_STM32 880 select PINCTRL 881 select RESET_CONTROLLER 882 select STM32_EXTI 883 help 884 Support for STMicroelectronics STM32 processors. 885 886config MACH_STM32F429 887 bool "STMicrolectronics STM32F429" 888 depends on ARCH_STM32 889 default y 890 891config MACH_STM32F746 892 bool "STMicrolectronics STM32F746" 893 depends on ARCH_STM32 894 default y 895 896config ARCH_MPS2 897 bool "ARM MPS2 platform" 898 depends on ARM_SINGLE_ARMV7M 899 select ARM_AMBA 900 select CLKSRC_MPS2 901 help 902 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 903 with a range of available cores like Cortex-M3/M4/M7. 904 905 Please, note that depends which Application Note is used memory map 906 for the platform may vary, so adjustment of RAM base might be needed. 907 908# Definitions to make life easier 909config ARCH_ACORN 910 bool 911 912config PLAT_IOP 913 bool 914 select GENERIC_CLOCKEVENTS 915 916config PLAT_ORION 917 bool 918 select CLKSRC_MMIO 919 select COMMON_CLK 920 select GENERIC_IRQ_CHIP 921 select IRQ_DOMAIN 922 923config PLAT_ORION_LEGACY 924 bool 925 select PLAT_ORION 926 927config PLAT_PXA 928 bool 929 930config PLAT_VERSATILE 931 bool 932 933source "arch/arm/firmware/Kconfig" 934 935source arch/arm/mm/Kconfig 936 937config IWMMXT 938 bool "Enable iWMMXt support" 939 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 940 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 941 help 942 Enable support for iWMMXt context switching at run time if 943 running on a CPU that supports it. 944 945config MULTI_IRQ_HANDLER 946 bool 947 help 948 Allow each machine to specify it's own IRQ handler at run time. 949 950if !MMU 951source "arch/arm/Kconfig-nommu" 952endif 953 954config PJ4B_ERRATA_4742 955 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 956 depends on CPU_PJ4B && MACH_ARMADA_370 957 default y 958 help 959 When coming out of either a Wait for Interrupt (WFI) or a Wait for 960 Event (WFE) IDLE states, a specific timing sensitivity exists between 961 the retiring WFI/WFE instructions and the newly issued subsequent 962 instructions. This sensitivity can result in a CPU hang scenario. 963 Workaround: 964 The software must insert either a Data Synchronization Barrier (DSB) 965 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 966 instruction 967 968config ARM_ERRATA_326103 969 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 970 depends on CPU_V6 971 help 972 Executing a SWP instruction to read-only memory does not set bit 11 973 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 974 treat the access as a read, preventing a COW from occurring and 975 causing the faulting task to livelock. 976 977config ARM_ERRATA_411920 978 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 979 depends on CPU_V6 || CPU_V6K 980 help 981 Invalidation of the Instruction Cache operation can 982 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 983 It does not affect the MPCore. This option enables the ARM Ltd. 984 recommended workaround. 985 986config ARM_ERRATA_430973 987 bool "ARM errata: Stale prediction on replaced interworking branch" 988 depends on CPU_V7 989 help 990 This option enables the workaround for the 430973 Cortex-A8 991 r1p* erratum. If a code sequence containing an ARM/Thumb 992 interworking branch is replaced with another code sequence at the 993 same virtual address, whether due to self-modifying code or virtual 994 to physical address re-mapping, Cortex-A8 does not recover from the 995 stale interworking branch prediction. This results in Cortex-A8 996 executing the new code sequence in the incorrect ARM or Thumb state. 997 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 998 and also flushes the branch target cache at every context switch. 999 Note that setting specific bits in the ACTLR register may not be 1000 available in non-secure mode. 1001 1002config ARM_ERRATA_458693 1003 bool "ARM errata: Processor deadlock when a false hazard is created" 1004 depends on CPU_V7 1005 depends on !ARCH_MULTIPLATFORM 1006 help 1007 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1008 erratum. For very specific sequences of memory operations, it is 1009 possible for a hazard condition intended for a cache line to instead 1010 be incorrectly associated with a different cache line. This false 1011 hazard might then cause a processor deadlock. The workaround enables 1012 the L1 caching of the NEON accesses and disables the PLD instruction 1013 in the ACTLR register. Note that setting specific bits in the ACTLR 1014 register may not be available in non-secure mode. 1015 1016config ARM_ERRATA_460075 1017 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1018 depends on CPU_V7 1019 depends on !ARCH_MULTIPLATFORM 1020 help 1021 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1022 erratum. Any asynchronous access to the L2 cache may encounter a 1023 situation in which recent store transactions to the L2 cache are lost 1024 and overwritten with stale memory contents from external memory. The 1025 workaround disables the write-allocate mode for the L2 cache via the 1026 ACTLR register. Note that setting specific bits in the ACTLR register 1027 may not be available in non-secure mode. 1028 1029config ARM_ERRATA_742230 1030 bool "ARM errata: DMB operation may be faulty" 1031 depends on CPU_V7 && SMP 1032 depends on !ARCH_MULTIPLATFORM 1033 help 1034 This option enables the workaround for the 742230 Cortex-A9 1035 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1036 between two write operations may not ensure the correct visibility 1037 ordering of the two writes. This workaround sets a specific bit in 1038 the diagnostic register of the Cortex-A9 which causes the DMB 1039 instruction to behave as a DSB, ensuring the correct behaviour of 1040 the two writes. 1041 1042config ARM_ERRATA_742231 1043 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1044 depends on CPU_V7 && SMP 1045 depends on !ARCH_MULTIPLATFORM 1046 help 1047 This option enables the workaround for the 742231 Cortex-A9 1048 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1049 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1050 accessing some data located in the same cache line, may get corrupted 1051 data due to bad handling of the address hazard when the line gets 1052 replaced from one of the CPUs at the same time as another CPU is 1053 accessing it. This workaround sets specific bits in the diagnostic 1054 register of the Cortex-A9 which reduces the linefill issuing 1055 capabilities of the processor. 1056 1057config ARM_ERRATA_643719 1058 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1059 depends on CPU_V7 && SMP 1060 default y 1061 help 1062 This option enables the workaround for the 643719 Cortex-A9 (prior to 1063 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1064 register returns zero when it should return one. The workaround 1065 corrects this value, ensuring cache maintenance operations which use 1066 it behave as intended and avoiding data corruption. 1067 1068config ARM_ERRATA_720789 1069 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1070 depends on CPU_V7 1071 help 1072 This option enables the workaround for the 720789 Cortex-A9 (prior to 1073 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1074 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1075 As a consequence of this erratum, some TLB entries which should be 1076 invalidated are not, resulting in an incoherency in the system page 1077 tables. The workaround changes the TLB flushing routines to invalidate 1078 entries regardless of the ASID. 1079 1080config ARM_ERRATA_743622 1081 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1082 depends on CPU_V7 1083 depends on !ARCH_MULTIPLATFORM 1084 help 1085 This option enables the workaround for the 743622 Cortex-A9 1086 (r2p*) erratum. Under very rare conditions, a faulty 1087 optimisation in the Cortex-A9 Store Buffer may lead to data 1088 corruption. This workaround sets a specific bit in the diagnostic 1089 register of the Cortex-A9 which disables the Store Buffer 1090 optimisation, preventing the defect from occurring. This has no 1091 visible impact on the overall performance or power consumption of the 1092 processor. 1093 1094config ARM_ERRATA_751472 1095 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1096 depends on CPU_V7 1097 depends on !ARCH_MULTIPLATFORM 1098 help 1099 This option enables the workaround for the 751472 Cortex-A9 (prior 1100 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1101 completion of a following broadcasted operation if the second 1102 operation is received by a CPU before the ICIALLUIS has completed, 1103 potentially leading to corrupted entries in the cache or TLB. 1104 1105config ARM_ERRATA_754322 1106 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1107 depends on CPU_V7 1108 help 1109 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1110 r3p*) erratum. A speculative memory access may cause a page table walk 1111 which starts prior to an ASID switch but completes afterwards. This 1112 can populate the micro-TLB with a stale entry which may be hit with 1113 the new ASID. This workaround places two dsb instructions in the mm 1114 switching code so that no page table walks can cross the ASID switch. 1115 1116config ARM_ERRATA_754327 1117 bool "ARM errata: no automatic Store Buffer drain" 1118 depends on CPU_V7 && SMP 1119 help 1120 This option enables the workaround for the 754327 Cortex-A9 (prior to 1121 r2p0) erratum. The Store Buffer does not have any automatic draining 1122 mechanism and therefore a livelock may occur if an external agent 1123 continuously polls a memory location waiting to observe an update. 1124 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1125 written polling loops from denying visibility of updates to memory. 1126 1127config ARM_ERRATA_364296 1128 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1129 depends on CPU_V6 1130 help 1131 This options enables the workaround for the 364296 ARM1136 1132 r0p2 erratum (possible cache data corruption with 1133 hit-under-miss enabled). It sets the undocumented bit 31 in 1134 the auxiliary control register and the FI bit in the control 1135 register, thus disabling hit-under-miss without putting the 1136 processor into full low interrupt latency mode. ARM11MPCore 1137 is not affected. 1138 1139config ARM_ERRATA_764369 1140 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1141 depends on CPU_V7 && SMP 1142 help 1143 This option enables the workaround for erratum 764369 1144 affecting Cortex-A9 MPCore with two or more processors (all 1145 current revisions). Under certain timing circumstances, a data 1146 cache line maintenance operation by MVA targeting an Inner 1147 Shareable memory region may fail to proceed up to either the 1148 Point of Coherency or to the Point of Unification of the 1149 system. This workaround adds a DSB instruction before the 1150 relevant cache maintenance functions and sets a specific bit 1151 in the diagnostic control register of the SCU. 1152 1153config ARM_ERRATA_775420 1154 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1155 depends on CPU_V7 1156 help 1157 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1158 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1159 operation aborts with MMU exception, it might cause the processor 1160 to deadlock. This workaround puts DSB before executing ISB if 1161 an abort may occur on cache maintenance. 1162 1163config ARM_ERRATA_798181 1164 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1165 depends on CPU_V7 && SMP 1166 help 1167 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1168 adequately shooting down all use of the old entries. This 1169 option enables the Linux kernel workaround for this erratum 1170 which sends an IPI to the CPUs that are running the same ASID 1171 as the one being invalidated. 1172 1173config ARM_ERRATA_773022 1174 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1175 depends on CPU_V7 1176 help 1177 This option enables the workaround for the 773022 Cortex-A15 1178 (up to r0p4) erratum. In certain rare sequences of code, the 1179 loop buffer may deliver incorrect instructions. This 1180 workaround disables the loop buffer to avoid the erratum. 1181 1182config ARM_ERRATA_818325_852422 1183 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1184 depends on CPU_V7 1185 help 1186 This option enables the workaround for: 1187 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1188 instruction might deadlock. Fixed in r0p1. 1189 - Cortex-A12 852422: Execution of a sequence of instructions might 1190 lead to either a data corruption or a CPU deadlock. Not fixed in 1191 any Cortex-A12 cores yet. 1192 This workaround for all both errata involves setting bit[12] of the 1193 Feature Register. This bit disables an optimisation applied to a 1194 sequence of 2 instructions that use opposing condition codes. 1195 1196config ARM_ERRATA_821420 1197 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1198 depends on CPU_V7 1199 help 1200 This option enables the workaround for the 821420 Cortex-A12 1201 (all revs) erratum. In very rare timing conditions, a sequence 1202 of VMOV to Core registers instructions, for which the second 1203 one is in the shadow of a branch or abort, can lead to a 1204 deadlock when the VMOV instructions are issued out-of-order. 1205 1206config ARM_ERRATA_825619 1207 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1208 depends on CPU_V7 1209 help 1210 This option enables the workaround for the 825619 Cortex-A12 1211 (all revs) erratum. Within rare timing constraints, executing a 1212 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1213 and Device/Strongly-Ordered loads and stores might cause deadlock 1214 1215config ARM_ERRATA_852421 1216 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1217 depends on CPU_V7 1218 help 1219 This option enables the workaround for the 852421 Cortex-A17 1220 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1221 execution of a DMB ST instruction might fail to properly order 1222 stores from GroupA and stores from GroupB. 1223 1224config ARM_ERRATA_852423 1225 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1226 depends on CPU_V7 1227 help 1228 This option enables the workaround for: 1229 - Cortex-A17 852423: Execution of a sequence of instructions might 1230 lead to either a data corruption or a CPU deadlock. Not fixed in 1231 any Cortex-A17 cores yet. 1232 This is identical to Cortex-A12 erratum 852422. It is a separate 1233 config option from the A12 erratum due to the way errata are checked 1234 for and handled. 1235 1236endmenu 1237 1238source "arch/arm/common/Kconfig" 1239 1240menu "Bus support" 1241 1242config ISA 1243 bool 1244 help 1245 Find out whether you have ISA slots on your motherboard. ISA is the 1246 name of a bus system, i.e. the way the CPU talks to the other stuff 1247 inside your box. Other bus systems are PCI, EISA, MicroChannel 1248 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1249 newer boards don't support it. If you have ISA, say Y, otherwise N. 1250 1251# Select ISA DMA controller support 1252config ISA_DMA 1253 bool 1254 select ISA_DMA_API 1255 1256# Select ISA DMA interface 1257config ISA_DMA_API 1258 bool 1259 1260config PCI 1261 bool "PCI support" if MIGHT_HAVE_PCI 1262 help 1263 Find out whether you have a PCI motherboard. PCI is the name of a 1264 bus system, i.e. the way the CPU talks to the other stuff inside 1265 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1266 VESA. If you have PCI, say Y, otherwise N. 1267 1268config PCI_DOMAINS 1269 bool 1270 depends on PCI 1271 1272config PCI_DOMAINS_GENERIC 1273 def_bool PCI_DOMAINS 1274 1275config PCI_NANOENGINE 1276 bool "BSE nanoEngine PCI support" 1277 depends on SA1100_NANOENGINE 1278 help 1279 Enable PCI on the BSE nanoEngine board. 1280 1281config PCI_SYSCALL 1282 def_bool PCI 1283 1284config PCI_HOST_ITE8152 1285 bool 1286 depends on PCI && MACH_ARMCORE 1287 default y 1288 select DMABOUNCE 1289 1290source "drivers/pci/Kconfig" 1291 1292source "drivers/pcmcia/Kconfig" 1293 1294endmenu 1295 1296menu "Kernel Features" 1297 1298config HAVE_SMP 1299 bool 1300 help 1301 This option should be selected by machines which have an SMP- 1302 capable CPU. 1303 1304 The only effect of this option is to make the SMP-related 1305 options available to the user for configuration. 1306 1307config SMP 1308 bool "Symmetric Multi-Processing" 1309 depends on CPU_V6K || CPU_V7 1310 depends on GENERIC_CLOCKEVENTS 1311 depends on HAVE_SMP 1312 depends on MMU || ARM_MPU 1313 select IRQ_WORK 1314 help 1315 This enables support for systems with more than one CPU. If you have 1316 a system with only one CPU, say N. If you have a system with more 1317 than one CPU, say Y. 1318 1319 If you say N here, the kernel will run on uni- and multiprocessor 1320 machines, but will use only one CPU of a multiprocessor machine. If 1321 you say Y here, the kernel will run on many, but not all, 1322 uniprocessor machines. On a uniprocessor machine, the kernel 1323 will run faster if you say N here. 1324 1325 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1326 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1327 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1328 1329 If you don't know what to do here, say N. 1330 1331config SMP_ON_UP 1332 bool "Allow booting SMP kernel on uniprocessor systems" 1333 depends on SMP && !XIP_KERNEL && MMU 1334 default y 1335 help 1336 SMP kernels contain instructions which fail on non-SMP processors. 1337 Enabling this option allows the kernel to modify itself to make 1338 these instructions safe. Disabling it allows about 1K of space 1339 savings. 1340 1341 If you don't know what to do here, say Y. 1342 1343config ARM_CPU_TOPOLOGY 1344 bool "Support cpu topology definition" 1345 depends on SMP && CPU_V7 1346 default y 1347 help 1348 Support ARM cpu topology definition. The MPIDR register defines 1349 affinity between processors which is then used to describe the cpu 1350 topology of an ARM System. 1351 1352config SCHED_MC 1353 bool "Multi-core scheduler support" 1354 depends on ARM_CPU_TOPOLOGY 1355 help 1356 Multi-core scheduler support improves the CPU scheduler's decision 1357 making when dealing with multi-core CPU chips at a cost of slightly 1358 increased overhead in some places. If unsure say N here. 1359 1360config SCHED_SMT 1361 bool "SMT scheduler support" 1362 depends on ARM_CPU_TOPOLOGY 1363 help 1364 Improves the CPU scheduler's decision making when dealing with 1365 MultiThreading at a cost of slightly increased overhead in some 1366 places. If unsure say N here. 1367 1368config HAVE_ARM_SCU 1369 bool 1370 help 1371 This option enables support for the ARM system coherency unit 1372 1373config HAVE_ARM_ARCH_TIMER 1374 bool "Architected timer support" 1375 depends on CPU_V7 1376 select ARM_ARCH_TIMER 1377 select GENERIC_CLOCKEVENTS 1378 help 1379 This option enables support for the ARM architected timer 1380 1381config HAVE_ARM_TWD 1382 bool 1383 select CLKSRC_OF if OF 1384 help 1385 This options enables support for the ARM timer and watchdog unit 1386 1387config MCPM 1388 bool "Multi-Cluster Power Management" 1389 depends on CPU_V7 && SMP 1390 help 1391 This option provides the common power management infrastructure 1392 for (multi-)cluster based systems, such as big.LITTLE based 1393 systems. 1394 1395config MCPM_QUAD_CLUSTER 1396 bool 1397 depends on MCPM 1398 help 1399 To avoid wasting resources unnecessarily, MCPM only supports up 1400 to 2 clusters by default. 1401 Platforms with 3 or 4 clusters that use MCPM must select this 1402 option to allow the additional clusters to be managed. 1403 1404config BIG_LITTLE 1405 bool "big.LITTLE support (Experimental)" 1406 depends on CPU_V7 && SMP 1407 select MCPM 1408 help 1409 This option enables support selections for the big.LITTLE 1410 system architecture. 1411 1412config BL_SWITCHER 1413 bool "big.LITTLE switcher support" 1414 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1415 select CPU_PM 1416 help 1417 The big.LITTLE "switcher" provides the core functionality to 1418 transparently handle transition between a cluster of A15's 1419 and a cluster of A7's in a big.LITTLE system. 1420 1421config BL_SWITCHER_DUMMY_IF 1422 tristate "Simple big.LITTLE switcher user interface" 1423 depends on BL_SWITCHER && DEBUG_KERNEL 1424 help 1425 This is a simple and dummy char dev interface to control 1426 the big.LITTLE switcher core code. It is meant for 1427 debugging purposes only. 1428 1429choice 1430 prompt "Memory split" 1431 depends on MMU 1432 default VMSPLIT_3G 1433 help 1434 Select the desired split between kernel and user memory. 1435 1436 If you are not absolutely sure what you are doing, leave this 1437 option alone! 1438 1439 config VMSPLIT_3G 1440 bool "3G/1G user/kernel split" 1441 config VMSPLIT_3G_OPT 1442 bool "3G/1G user/kernel split (for full 1G low memory)" 1443 config VMSPLIT_2G 1444 bool "2G/2G user/kernel split" 1445 config VMSPLIT_1G 1446 bool "1G/3G user/kernel split" 1447endchoice 1448 1449config PAGE_OFFSET 1450 hex 1451 default PHYS_OFFSET if !MMU 1452 default 0x40000000 if VMSPLIT_1G 1453 default 0x80000000 if VMSPLIT_2G 1454 default 0xB0000000 if VMSPLIT_3G_OPT 1455 default 0xC0000000 1456 1457config NR_CPUS 1458 int "Maximum number of CPUs (2-32)" 1459 range 2 32 1460 depends on SMP 1461 default "4" 1462 1463config HOTPLUG_CPU 1464 bool "Support for hot-pluggable CPUs" 1465 depends on SMP 1466 help 1467 Say Y here to experiment with turning CPUs off and on. CPUs 1468 can be controlled through /sys/devices/system/cpu. 1469 1470config ARM_PSCI 1471 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1472 depends on HAVE_ARM_SMCCC 1473 select ARM_PSCI_FW 1474 help 1475 Say Y here if you want Linux to communicate with system firmware 1476 implementing the PSCI specification for CPU-centric power 1477 management operations described in ARM document number ARM DEN 1478 0022A ("Power State Coordination Interface System Software on 1479 ARM processors"). 1480 1481# The GPIO number here must be sorted by descending number. In case of 1482# a multiplatform kernel, we just want the highest value required by the 1483# selected platforms. 1484config ARCH_NR_GPIO 1485 int 1486 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ 1487 ARCH_ZYNQ 1488 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1489 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1490 default 416 if ARCH_SUNXI 1491 default 392 if ARCH_U8500 1492 default 352 if ARCH_VT8500 1493 default 288 if ARCH_ROCKCHIP 1494 default 264 if MACH_H4700 1495 default 0 1496 help 1497 Maximum number of GPIOs in the system. 1498 1499 If unsure, leave the default value. 1500 1501source kernel/Kconfig.preempt 1502 1503config HZ_FIXED 1504 int 1505 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ 1506 ARCH_S5PV210 || ARCH_EXYNOS4 1507 default 128 if SOC_AT91RM9200 1508 default 0 1509 1510choice 1511 depends on HZ_FIXED = 0 1512 prompt "Timer frequency" 1513 1514config HZ_100 1515 bool "100 Hz" 1516 1517config HZ_200 1518 bool "200 Hz" 1519 1520config HZ_250 1521 bool "250 Hz" 1522 1523config HZ_300 1524 bool "300 Hz" 1525 1526config HZ_500 1527 bool "500 Hz" 1528 1529config HZ_1000 1530 bool "1000 Hz" 1531 1532endchoice 1533 1534config HZ 1535 int 1536 default HZ_FIXED if HZ_FIXED != 0 1537 default 100 if HZ_100 1538 default 200 if HZ_200 1539 default 250 if HZ_250 1540 default 300 if HZ_300 1541 default 500 if HZ_500 1542 default 1000 1543 1544config SCHED_HRTICK 1545 def_bool HIGH_RES_TIMERS 1546 1547config THUMB2_KERNEL 1548 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1549 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1550 default y if CPU_THUMBONLY 1551 select AEABI 1552 select ARM_ASM_UNIFIED 1553 select ARM_UNWIND 1554 help 1555 By enabling this option, the kernel will be compiled in 1556 Thumb-2 mode. A compiler/assembler that understand the unified 1557 ARM-Thumb syntax is needed. 1558 1559 If unsure, say N. 1560 1561config THUMB2_AVOID_R_ARM_THM_JUMP11 1562 bool "Work around buggy Thumb-2 short branch relocations in gas" 1563 depends on THUMB2_KERNEL && MODULES 1564 default y 1565 help 1566 Various binutils versions can resolve Thumb-2 branches to 1567 locally-defined, preemptible global symbols as short-range "b.n" 1568 branch instructions. 1569 1570 This is a problem, because there's no guarantee the final 1571 destination of the symbol, or any candidate locations for a 1572 trampoline, are within range of the branch. For this reason, the 1573 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1574 relocation in modules at all, and it makes little sense to add 1575 support. 1576 1577 The symptom is that the kernel fails with an "unsupported 1578 relocation" error when loading some modules. 1579 1580 Until fixed tools are available, passing 1581 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1582 code which hits this problem, at the cost of a bit of extra runtime 1583 stack usage in some cases. 1584 1585 The problem is described in more detail at: 1586 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1587 1588 Only Thumb-2 kernels are affected. 1589 1590 Unless you are sure your tools don't have this problem, say Y. 1591 1592config ARM_ASM_UNIFIED 1593 bool 1594 1595config ARM_PATCH_IDIV 1596 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1597 depends on CPU_32v7 && !XIP_KERNEL 1598 default y 1599 help 1600 The ARM compiler inserts calls to __aeabi_idiv() and 1601 __aeabi_uidiv() when it needs to perform division on signed 1602 and unsigned integers. Some v7 CPUs have support for the sdiv 1603 and udiv instructions that can be used to implement those 1604 functions. 1605 1606 Enabling this option allows the kernel to modify itself to 1607 replace the first two instructions of these library functions 1608 with the sdiv or udiv plus "bx lr" instructions when the CPU 1609 it is running on supports them. Typically this will be faster 1610 and less power intensive than running the original library 1611 code to do integer division. 1612 1613config AEABI 1614 bool "Use the ARM EABI to compile the kernel" 1615 help 1616 This option allows for the kernel to be compiled using the latest 1617 ARM ABI (aka EABI). This is only useful if you are using a user 1618 space environment that is also compiled with EABI. 1619 1620 Since there are major incompatibilities between the legacy ABI and 1621 EABI, especially with regard to structure member alignment, this 1622 option also changes the kernel syscall calling convention to 1623 disambiguate both ABIs and allow for backward compatibility support 1624 (selected with CONFIG_OABI_COMPAT). 1625 1626 To use this you need GCC version 4.0.0 or later. 1627 1628config OABI_COMPAT 1629 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1630 depends on AEABI && !THUMB2_KERNEL 1631 help 1632 This option preserves the old syscall interface along with the 1633 new (ARM EABI) one. It also provides a compatibility layer to 1634 intercept syscalls that have structure arguments which layout 1635 in memory differs between the legacy ABI and the new ARM EABI 1636 (only for non "thumb" binaries). This option adds a tiny 1637 overhead to all syscalls and produces a slightly larger kernel. 1638 1639 The seccomp filter system will not be available when this is 1640 selected, since there is no way yet to sensibly distinguish 1641 between calling conventions during filtering. 1642 1643 If you know you'll be using only pure EABI user space then you 1644 can say N here. If this option is not selected and you attempt 1645 to execute a legacy ABI binary then the result will be 1646 UNPREDICTABLE (in fact it can be predicted that it won't work 1647 at all). If in doubt say N. 1648 1649config ARCH_HAS_HOLES_MEMORYMODEL 1650 bool 1651 1652config ARCH_SPARSEMEM_ENABLE 1653 bool 1654 1655config ARCH_SPARSEMEM_DEFAULT 1656 def_bool ARCH_SPARSEMEM_ENABLE 1657 1658config ARCH_SELECT_MEMORY_MODEL 1659 def_bool ARCH_SPARSEMEM_ENABLE 1660 1661config HAVE_ARCH_PFN_VALID 1662 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1663 1664config HAVE_GENERIC_RCU_GUP 1665 def_bool y 1666 depends on ARM_LPAE 1667 1668config HIGHMEM 1669 bool "High Memory Support" 1670 depends on MMU 1671 help 1672 The address space of ARM processors is only 4 Gigabytes large 1673 and it has to accommodate user address space, kernel address 1674 space as well as some memory mapped IO. That means that, if you 1675 have a large amount of physical memory and/or IO, not all of the 1676 memory can be "permanently mapped" by the kernel. The physical 1677 memory that is not permanently mapped is called "high memory". 1678 1679 Depending on the selected kernel/user memory split, minimum 1680 vmalloc space and actual amount of RAM, you may not need this 1681 option which should result in a slightly faster kernel. 1682 1683 If unsure, say n. 1684 1685config HIGHPTE 1686 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1687 depends on HIGHMEM 1688 default y 1689 help 1690 The VM uses one page of physical memory for each page table. 1691 For systems with a lot of processes, this can use a lot of 1692 precious low memory, eventually leading to low memory being 1693 consumed by page tables. Setting this option will allow 1694 user-space 2nd level page tables to reside in high memory. 1695 1696config CPU_SW_DOMAIN_PAN 1697 bool "Enable use of CPU domains to implement privileged no-access" 1698 depends on MMU && !ARM_LPAE 1699 default y 1700 help 1701 Increase kernel security by ensuring that normal kernel accesses 1702 are unable to access userspace addresses. This can help prevent 1703 use-after-free bugs becoming an exploitable privilege escalation 1704 by ensuring that magic values (such as LIST_POISON) will always 1705 fault when dereferenced. 1706 1707 CPUs with low-vector mappings use a best-efforts implementation. 1708 Their lower 1MB needs to remain accessible for the vectors, but 1709 the remainder of userspace will become appropriately inaccessible. 1710 1711config HW_PERF_EVENTS 1712 def_bool y 1713 depends on ARM_PMU 1714 1715config SYS_SUPPORTS_HUGETLBFS 1716 def_bool y 1717 depends on ARM_LPAE 1718 1719config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1720 def_bool y 1721 depends on ARM_LPAE 1722 1723config ARCH_WANT_GENERAL_HUGETLB 1724 def_bool y 1725 1726config ARM_MODULE_PLTS 1727 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1728 depends on MODULES 1729 help 1730 Allocate PLTs when loading modules so that jumps and calls whose 1731 targets are too far away for their relative offsets to be encoded 1732 in the instructions themselves can be bounced via veneers in the 1733 module's PLT. This allows modules to be allocated in the generic 1734 vmalloc area after the dedicated module memory area has been 1735 exhausted. The modules will use slightly more memory, but after 1736 rounding up to page size, the actual memory footprint is usually 1737 the same. 1738 1739 Say y if you are getting out of memory errors while loading modules 1740 1741source "mm/Kconfig" 1742 1743config FORCE_MAX_ZONEORDER 1744 int "Maximum zone order" 1745 default "12" if SOC_AM33XX 1746 default "9" if SA1111 || ARCH_EFM32 1747 default "11" 1748 help 1749 The kernel memory allocator divides physically contiguous memory 1750 blocks into "zones", where each zone is a power of two number of 1751 pages. This option selects the largest power of two that the kernel 1752 keeps in the memory allocator. If you need to allocate very large 1753 blocks of physically contiguous memory, then you may need to 1754 increase this value. 1755 1756 This config option is actually maximum order plus one. For example, 1757 a value of 11 means that the largest free memory block is 2^10 pages. 1758 1759config ALIGNMENT_TRAP 1760 bool 1761 depends on CPU_CP15_MMU 1762 default y if !ARCH_EBSA110 1763 select HAVE_PROC_CPU if PROC_FS 1764 help 1765 ARM processors cannot fetch/store information which is not 1766 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1767 address divisible by 4. On 32-bit ARM processors, these non-aligned 1768 fetch/store instructions will be emulated in software if you say 1769 here, which has a severe performance impact. This is necessary for 1770 correct operation of some network protocols. With an IP-only 1771 configuration it is safe to say N, otherwise say Y. 1772 1773config UACCESS_WITH_MEMCPY 1774 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1775 depends on MMU 1776 default y if CPU_FEROCEON 1777 help 1778 Implement faster copy_to_user and clear_user methods for CPU 1779 cores where a 8-word STM instruction give significantly higher 1780 memory write throughput than a sequence of individual 32bit stores. 1781 1782 A possible side effect is a slight increase in scheduling latency 1783 between threads sharing the same address space if they invoke 1784 such copy operations with large buffers. 1785 1786 However, if the CPU data cache is using a write-allocate mode, 1787 this option is unlikely to provide any performance gain. 1788 1789config SECCOMP 1790 bool 1791 prompt "Enable seccomp to safely compute untrusted bytecode" 1792 ---help--- 1793 This kernel feature is useful for number crunching applications 1794 that may need to compute untrusted bytecode during their 1795 execution. By using pipes or other transports made available to 1796 the process as file descriptors supporting the read/write 1797 syscalls, it's possible to isolate those applications in 1798 their own address space using seccomp. Once seccomp is 1799 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1800 and the task is only allowed to execute a few safe syscalls 1801 defined by each seccomp mode. 1802 1803config SWIOTLB 1804 def_bool y 1805 1806config IOMMU_HELPER 1807 def_bool SWIOTLB 1808 1809config PARAVIRT 1810 bool "Enable paravirtualization code" 1811 help 1812 This changes the kernel so it can modify itself when it is run 1813 under a hypervisor, potentially improving performance significantly 1814 over full virtualization. 1815 1816config PARAVIRT_TIME_ACCOUNTING 1817 bool "Paravirtual steal time accounting" 1818 select PARAVIRT 1819 default n 1820 help 1821 Select this option to enable fine granularity task steal time 1822 accounting. Time spent executing other tasks in parallel with 1823 the current vCPU is discounted from the vCPU power. To account for 1824 that, there can be a small performance impact. 1825 1826 If in doubt, say N here. 1827 1828config XEN_DOM0 1829 def_bool y 1830 depends on XEN 1831 1832config XEN 1833 bool "Xen guest support on ARM" 1834 depends on ARM && AEABI && OF 1835 depends on CPU_V7 && !CPU_V6 1836 depends on !GENERIC_ATOMIC64 1837 depends on MMU 1838 select ARCH_DMA_ADDR_T_64BIT 1839 select ARM_PSCI 1840 select SWIOTLB_XEN 1841 select PARAVIRT 1842 help 1843 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1844 1845endmenu 1846 1847menu "Boot options" 1848 1849config USE_OF 1850 bool "Flattened Device Tree support" 1851 select IRQ_DOMAIN 1852 select OF 1853 help 1854 Include support for flattened device tree machine descriptions. 1855 1856config ATAGS 1857 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1858 default y 1859 help 1860 This is the traditional way of passing data to the kernel at boot 1861 time. If you are solely relying on the flattened device tree (or 1862 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1863 to remove ATAGS support from your kernel binary. If unsure, 1864 leave this to y. 1865 1866config DEPRECATED_PARAM_STRUCT 1867 bool "Provide old way to pass kernel parameters" 1868 depends on ATAGS 1869 help 1870 This was deprecated in 2001 and announced to live on for 5 years. 1871 Some old boot loaders still use this way. 1872 1873# Compressed boot loader in ROM. Yes, we really want to ask about 1874# TEXT and BSS so we preserve their values in the config files. 1875config ZBOOT_ROM_TEXT 1876 hex "Compressed ROM boot loader base address" 1877 default "0" 1878 help 1879 The physical address at which the ROM-able zImage is to be 1880 placed in the target. Platforms which normally make use of 1881 ROM-able zImage formats normally set this to a suitable 1882 value in their defconfig file. 1883 1884 If ZBOOT_ROM is not enabled, this has no effect. 1885 1886config ZBOOT_ROM_BSS 1887 hex "Compressed ROM boot loader BSS address" 1888 default "0" 1889 help 1890 The base address of an area of read/write memory in the target 1891 for the ROM-able zImage which must be available while the 1892 decompressor is running. It must be large enough to hold the 1893 entire decompressed kernel plus an additional 128 KiB. 1894 Platforms which normally make use of ROM-able zImage formats 1895 normally set this to a suitable value in their defconfig file. 1896 1897 If ZBOOT_ROM is not enabled, this has no effect. 1898 1899config ZBOOT_ROM 1900 bool "Compressed boot loader in ROM/flash" 1901 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1902 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1903 help 1904 Say Y here if you intend to execute your compressed kernel image 1905 (zImage) directly from ROM or flash. If unsure, say N. 1906 1907config ARM_APPENDED_DTB 1908 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1909 depends on OF 1910 help 1911 With this option, the boot code will look for a device tree binary 1912 (DTB) appended to zImage 1913 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1914 1915 This is meant as a backward compatibility convenience for those 1916 systems with a bootloader that can't be upgraded to accommodate 1917 the documented boot protocol using a device tree. 1918 1919 Beware that there is very little in terms of protection against 1920 this option being confused by leftover garbage in memory that might 1921 look like a DTB header after a reboot if no actual DTB is appended 1922 to zImage. Do not leave this option active in a production kernel 1923 if you don't intend to always append a DTB. Proper passing of the 1924 location into r2 of a bootloader provided DTB is always preferable 1925 to this option. 1926 1927config ARM_ATAG_DTB_COMPAT 1928 bool "Supplement the appended DTB with traditional ATAG information" 1929 depends on ARM_APPENDED_DTB 1930 help 1931 Some old bootloaders can't be updated to a DTB capable one, yet 1932 they provide ATAGs with memory configuration, the ramdisk address, 1933 the kernel cmdline string, etc. Such information is dynamically 1934 provided by the bootloader and can't always be stored in a static 1935 DTB. To allow a device tree enabled kernel to be used with such 1936 bootloaders, this option allows zImage to extract the information 1937 from the ATAG list and store it at run time into the appended DTB. 1938 1939choice 1940 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1941 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1942 1943config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1944 bool "Use bootloader kernel arguments if available" 1945 help 1946 Uses the command-line options passed by the boot loader instead of 1947 the device tree bootargs property. If the boot loader doesn't provide 1948 any, the device tree bootargs property will be used. 1949 1950config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1951 bool "Extend with bootloader kernel arguments" 1952 help 1953 The command-line arguments provided by the boot loader will be 1954 appended to the the device tree bootargs property. 1955 1956endchoice 1957 1958config CMDLINE 1959 string "Default kernel command string" 1960 default "" 1961 help 1962 On some architectures (EBSA110 and CATS), there is currently no way 1963 for the boot loader to pass arguments to the kernel. For these 1964 architectures, you should supply some command-line options at build 1965 time by entering them here. As a minimum, you should specify the 1966 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1967 1968choice 1969 prompt "Kernel command line type" if CMDLINE != "" 1970 default CMDLINE_FROM_BOOTLOADER 1971 depends on ATAGS 1972 1973config CMDLINE_FROM_BOOTLOADER 1974 bool "Use bootloader kernel arguments if available" 1975 help 1976 Uses the command-line options passed by the boot loader. If 1977 the boot loader doesn't provide any, the default kernel command 1978 string provided in CMDLINE will be used. 1979 1980config CMDLINE_EXTEND 1981 bool "Extend bootloader kernel arguments" 1982 help 1983 The command-line arguments provided by the boot loader will be 1984 appended to the default kernel command string. 1985 1986config CMDLINE_FORCE 1987 bool "Always use the default kernel command string" 1988 help 1989 Always use the default kernel command string, even if the boot 1990 loader passes other arguments to the kernel. 1991 This is useful if you cannot or don't want to change the 1992 command-line options your boot loader passes to the kernel. 1993endchoice 1994 1995config XIP_KERNEL 1996 bool "Kernel Execute-In-Place from ROM" 1997 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1998 help 1999 Execute-In-Place allows the kernel to run from non-volatile storage 2000 directly addressable by the CPU, such as NOR flash. This saves RAM 2001 space since the text section of the kernel is not loaded from flash 2002 to RAM. Read-write sections, such as the data section and stack, 2003 are still copied to RAM. The XIP kernel is not compressed since 2004 it has to run directly from flash, so it will take more space to 2005 store it. The flash address used to link the kernel object files, 2006 and for storing it, is configuration dependent. Therefore, if you 2007 say Y here, you must know the proper physical address where to 2008 store the kernel image depending on your own flash memory usage. 2009 2010 Also note that the make target becomes "make xipImage" rather than 2011 "make zImage" or "make Image". The final kernel binary to put in 2012 ROM memory will be arch/arm/boot/xipImage. 2013 2014 If unsure, say N. 2015 2016config XIP_PHYS_ADDR 2017 hex "XIP Kernel Physical Location" 2018 depends on XIP_KERNEL 2019 default "0x00080000" 2020 help 2021 This is the physical address in your flash memory the kernel will 2022 be linked for and stored to. This address is dependent on your 2023 own flash usage. 2024 2025config KEXEC 2026 bool "Kexec system call (EXPERIMENTAL)" 2027 depends on (!SMP || PM_SLEEP_SMP) 2028 depends on !CPU_V7M 2029 select KEXEC_CORE 2030 help 2031 kexec is a system call that implements the ability to shutdown your 2032 current kernel, and to start another kernel. It is like a reboot 2033 but it is independent of the system firmware. And like a reboot 2034 you can start any kernel with it, not just Linux. 2035 2036 It is an ongoing process to be certain the hardware in a machine 2037 is properly shutdown, so do not be surprised if this code does not 2038 initially work for you. 2039 2040config ATAGS_PROC 2041 bool "Export atags in procfs" 2042 depends on ATAGS && KEXEC 2043 default y 2044 help 2045 Should the atags used to boot the kernel be exported in an "atags" 2046 file in procfs. Useful with kexec. 2047 2048config CRASH_DUMP 2049 bool "Build kdump crash kernel (EXPERIMENTAL)" 2050 help 2051 Generate crash dump after being started by kexec. This should 2052 be normally only set in special crash dump kernels which are 2053 loaded in the main kernel with kexec-tools into a specially 2054 reserved region and then later executed after a crash by 2055 kdump/kexec. The crash dump kernel must be compiled to a 2056 memory address not used by the main kernel 2057 2058 For more details see Documentation/kdump/kdump.txt 2059 2060config AUTO_ZRELADDR 2061 bool "Auto calculation of the decompressed kernel image address" 2062 help 2063 ZRELADDR is the physical address where the decompressed kernel 2064 image will be placed. If AUTO_ZRELADDR is selected, the address 2065 will be determined at run-time by masking the current IP with 2066 0xf8000000. This assumes the zImage being placed in the first 128MB 2067 from start of memory. 2068 2069config EFI_STUB 2070 bool 2071 2072config EFI 2073 bool "UEFI runtime support" 2074 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2075 select UCS2_STRING 2076 select EFI_PARAMS_FROM_FDT 2077 select EFI_STUB 2078 select EFI_ARMSTUB 2079 select EFI_RUNTIME_WRAPPERS 2080 ---help--- 2081 This option provides support for runtime services provided 2082 by UEFI firmware (such as non-volatile variables, realtime 2083 clock, and platform reset). A UEFI stub is also provided to 2084 allow the kernel to be booted as an EFI application. This 2085 is only useful for kernels that may run on systems that have 2086 UEFI firmware. 2087 2088endmenu 2089 2090menu "CPU Power Management" 2091 2092source "drivers/cpufreq/Kconfig" 2093 2094source "drivers/cpuidle/Kconfig" 2095 2096endmenu 2097 2098menu "Floating point emulation" 2099 2100comment "At least one emulation must be selected" 2101 2102config FPE_NWFPE 2103 bool "NWFPE math emulation" 2104 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2105 ---help--- 2106 Say Y to include the NWFPE floating point emulator in the kernel. 2107 This is necessary to run most binaries. Linux does not currently 2108 support floating point hardware so you need to say Y here even if 2109 your machine has an FPA or floating point co-processor podule. 2110 2111 You may say N here if you are going to load the Acorn FPEmulator 2112 early in the bootup. 2113 2114config FPE_NWFPE_XP 2115 bool "Support extended precision" 2116 depends on FPE_NWFPE 2117 help 2118 Say Y to include 80-bit support in the kernel floating-point 2119 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2120 Note that gcc does not generate 80-bit operations by default, 2121 so in most cases this option only enlarges the size of the 2122 floating point emulator without any good reason. 2123 2124 You almost surely want to say N here. 2125 2126config FPE_FASTFPE 2127 bool "FastFPE math emulation (EXPERIMENTAL)" 2128 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2129 ---help--- 2130 Say Y here to include the FAST floating point emulator in the kernel. 2131 This is an experimental much faster emulator which now also has full 2132 precision for the mantissa. It does not support any exceptions. 2133 It is very simple, and approximately 3-6 times faster than NWFPE. 2134 2135 It should be sufficient for most programs. It may be not suitable 2136 for scientific calculations, but you have to check this for yourself. 2137 If you do not feel you need a faster FP emulation you should better 2138 choose NWFPE. 2139 2140config VFP 2141 bool "VFP-format floating point maths" 2142 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2143 help 2144 Say Y to include VFP support code in the kernel. This is needed 2145 if your hardware includes a VFP unit. 2146 2147 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2148 release notes and additional status information. 2149 2150 Say N if your target does not have VFP hardware. 2151 2152config VFPv3 2153 bool 2154 depends on VFP 2155 default y if CPU_V7 2156 2157config NEON 2158 bool "Advanced SIMD (NEON) Extension support" 2159 depends on VFPv3 && CPU_V7 2160 help 2161 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2162 Extension. 2163 2164config KERNEL_MODE_NEON 2165 bool "Support for NEON in kernel mode" 2166 depends on NEON && AEABI 2167 help 2168 Say Y to include support for NEON in kernel mode. 2169 2170endmenu 2171 2172menu "Userspace binary formats" 2173 2174source "fs/Kconfig.binfmt" 2175 2176endmenu 2177 2178menu "Power management options" 2179 2180source "kernel/power/Kconfig" 2181 2182config ARCH_SUSPEND_POSSIBLE 2183 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2184 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2185 def_bool y 2186 2187config ARM_CPU_SUSPEND 2188 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2189 depends on ARCH_SUSPEND_POSSIBLE 2190 2191config ARCH_HIBERNATION_POSSIBLE 2192 bool 2193 depends on MMU 2194 default y if ARCH_SUSPEND_POSSIBLE 2195 2196endmenu 2197 2198source "net/Kconfig" 2199 2200source "drivers/Kconfig" 2201 2202source "drivers/firmware/Kconfig" 2203 2204source "fs/Kconfig" 2205 2206source "arch/arm/Kconfig.debug" 2207 2208source "security/Kconfig" 2209 2210source "crypto/Kconfig" 2211if CRYPTO 2212source "arch/arm/crypto/Kconfig" 2213endif 2214 2215source "lib/Kconfig" 2216 2217source "arch/arm/kvm/Kconfig" 2218