1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_CLOCKSOURCE_DATA 6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KCOV 12 select ARCH_HAS_MEMBARRIER_SYNC_CORE 13 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 14 select ARCH_HAS_PHYS_TO_DMA 15 select ARCH_HAS_SET_MEMORY 16 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 17 select ARCH_HAS_STRICT_MODULE_RWX if MMU 18 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 19 select ARCH_HAVE_CUSTOM_GPIO_H 20 select ARCH_HAS_GCOV_PROFILE_ALL 21 select ARCH_MIGHT_HAVE_PC_PARPORT 22 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 23 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 24 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 25 select ARCH_SUPPORTS_ATOMIC_RMW 26 select ARCH_USE_BUILTIN_BSWAP 27 select ARCH_USE_CMPXCHG_LOCKREF 28 select ARCH_WANT_IPC_PARSE_VERSION 29 select BUILDTIME_EXTABLE_SORT if MMU 30 select CLONE_BACKWARDS 31 select CPU_PM if SUSPEND || CPU_IDLE 32 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 33 select DMA_REMAP if MMU 34 select EDAC_SUPPORT 35 select EDAC_ATOMIC_SCRUB 36 select GENERIC_ALLOCATOR 37 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 38 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 39 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 40 select GENERIC_CPU_AUTOPROBE 41 select GENERIC_EARLY_IOREMAP 42 select GENERIC_IDLE_POLL_SETUP 43 select GENERIC_IRQ_PROBE 44 select GENERIC_IRQ_SHOW 45 select GENERIC_IRQ_SHOW_LEVEL 46 select GENERIC_PCI_IOMAP 47 select GENERIC_SCHED_CLOCK 48 select GENERIC_SMP_IDLE_THREAD 49 select GENERIC_STRNCPY_FROM_USER 50 select GENERIC_STRNLEN_USER 51 select HANDLE_DOMAIN_IRQ 52 select HARDIRQS_SW_RESEND 53 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 54 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 55 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 56 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 57 select HAVE_ARCH_MMAP_RND_BITS if MMU 58 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 59 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 60 select HAVE_ARCH_TRACEHOOK 61 select HAVE_ARM_SMCCC if CPU_V7 62 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 63 select HAVE_CONTEXT_TRACKING 64 select HAVE_C_RECORDMCOUNT 65 select HAVE_DEBUG_KMEMLEAK 66 select HAVE_DMA_CONTIGUOUS if MMU 67 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 68 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 69 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 70 select HAVE_EXIT_THREAD 71 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 72 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL 73 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 74 select HAVE_GCC_PLUGINS 75 select HAVE_GENERIC_DMA_COHERENT 76 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 77 select HAVE_IDE if PCI || ISA || PCMCIA 78 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_KERNEL_GZIP 80 select HAVE_KERNEL_LZ4 81 select HAVE_KERNEL_LZMA 82 select HAVE_KERNEL_LZO 83 select HAVE_KERNEL_XZ 84 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 85 select HAVE_KRETPROBES if HAVE_KPROBES 86 select HAVE_MOD_ARCH_SPECIFIC 87 select HAVE_NMI 88 select HAVE_OPROFILE if HAVE_PERF_EVENTS 89 select HAVE_OPTPROBES if !THUMB2_KERNEL 90 select HAVE_PERF_EVENTS 91 select HAVE_PERF_REGS 92 select HAVE_PERF_USER_STACK_DUMP 93 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE 94 select HAVE_REGS_AND_STACK_ACCESS_API 95 select HAVE_RSEQ 96 select HAVE_STACKPROTECTOR 97 select HAVE_SYSCALL_TRACEPOINTS 98 select HAVE_UID16 99 select HAVE_VIRT_CPU_ACCOUNTING_GEN 100 select IRQ_FORCED_THREADING 101 select MODULES_USE_ELF_REL 102 select NEED_DMA_MAP_STATE 103 select OF_EARLY_FLATTREE if OF 104 select OF_RESERVED_MEM if OF 105 select OLD_SIGACTION 106 select OLD_SIGSUSPEND3 107 select PCI_SYSCALL if PCI 108 select PERF_USE_VMALLOC 109 select REFCOUNT_FULL 110 select RTC_LIB 111 select SYS_SUPPORTS_APM_EMULATION 112 # Above selects are sorted alphabetically; please add new ones 113 # according to that. Thanks. 114 help 115 The ARM series is a line of low-power-consumption RISC chip designs 116 licensed by ARM Ltd and targeted at embedded applications and 117 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 118 manufactured, but legacy ARM-based PC hardware remains popular in 119 Europe. There is an ARM Linux project with a web page at 120 <http://www.arm.linux.org.uk/>. 121 122config ARM_HAS_SG_CHAIN 123 bool 124 125config ARM_DMA_USE_IOMMU 126 bool 127 select ARM_HAS_SG_CHAIN 128 select NEED_SG_DMA_LENGTH 129 130if ARM_DMA_USE_IOMMU 131 132config ARM_DMA_IOMMU_ALIGNMENT 133 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 134 range 4 9 135 default 8 136 help 137 DMA mapping framework by default aligns all buffers to the smallest 138 PAGE_SIZE order which is greater than or equal to the requested buffer 139 size. This works well for buffers up to a few hundreds kilobytes, but 140 for larger buffers it just a waste of address space. Drivers which has 141 relatively small addressing window (like 64Mib) might run out of 142 virtual space with just a few allocations. 143 144 With this parameter you can specify the maximum PAGE_SIZE order for 145 DMA IOMMU buffers. Larger buffers will be aligned only to this 146 specified order. The order is expressed as a power of two multiplied 147 by the PAGE_SIZE. 148 149endif 150 151config SYS_SUPPORTS_APM_EMULATION 152 bool 153 154config HAVE_TCM 155 bool 156 select GENERIC_ALLOCATOR 157 158config HAVE_PROC_CPU 159 bool 160 161config NO_IOPORT_MAP 162 bool 163 164config SBUS 165 bool 166 167config STACKTRACE_SUPPORT 168 bool 169 default y 170 171config LOCKDEP_SUPPORT 172 bool 173 default y 174 175config TRACE_IRQFLAGS_SUPPORT 176 bool 177 default !CPU_V7M 178 179config RWSEM_XCHGADD_ALGORITHM 180 bool 181 default y 182 183config ARCH_HAS_ILOG2_U32 184 bool 185 186config ARCH_HAS_ILOG2_U64 187 bool 188 189config ARCH_HAS_BANDGAP 190 bool 191 192config FIX_EARLYCON_MEM 193 def_bool y if MMU 194 195config GENERIC_HWEIGHT 196 bool 197 default y 198 199config GENERIC_CALIBRATE_DELAY 200 bool 201 default y 202 203config ARCH_MAY_HAVE_PC_FDC 204 bool 205 206config ZONE_DMA 207 bool 208 209config ARCH_SUPPORTS_UPROBES 210 def_bool y 211 212config ARCH_HAS_DMA_SET_COHERENT_MASK 213 bool 214 215config GENERIC_ISA_DMA 216 bool 217 218config FIQ 219 bool 220 221config NEED_RET_TO_USER 222 bool 223 224config ARCH_MTD_XIP 225 bool 226 227config ARM_PATCH_PHYS_VIRT 228 bool "Patch physical to virtual translations at runtime" if EMBEDDED 229 default y 230 depends on !XIP_KERNEL && MMU 231 help 232 Patch phys-to-virt and virt-to-phys translation functions at 233 boot and module load time according to the position of the 234 kernel in system memory. 235 236 This can only be used with non-XIP MMU kernels where the base 237 of physical memory is at a 16MB boundary. 238 239 Only disable this option if you know that you do not require 240 this feature (eg, building a kernel for a single machine) and 241 you need to shrink the kernel to the minimal size. 242 243config NEED_MACH_IO_H 244 bool 245 help 246 Select this when mach/io.h is required to provide special 247 definitions for this platform. The need for mach/io.h should 248 be avoided when possible. 249 250config NEED_MACH_MEMORY_H 251 bool 252 help 253 Select this when mach/memory.h is required to provide special 254 definitions for this platform. The need for mach/memory.h should 255 be avoided when possible. 256 257config PHYS_OFFSET 258 hex "Physical address of main memory" if MMU 259 depends on !ARM_PATCH_PHYS_VIRT 260 default DRAM_BASE if !MMU 261 default 0x00000000 if ARCH_EBSA110 || \ 262 ARCH_FOOTBRIDGE || \ 263 ARCH_INTEGRATOR || \ 264 ARCH_IOP13XX || \ 265 ARCH_KS8695 || \ 266 ARCH_REALVIEW 267 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 268 default 0x20000000 if ARCH_S5PV210 269 default 0xc0000000 if ARCH_SA1100 270 help 271 Please provide the physical address corresponding to the 272 location of main memory in your system. 273 274config GENERIC_BUG 275 def_bool y 276 depends on BUG 277 278config PGTABLE_LEVELS 279 int 280 default 3 if ARM_LPAE 281 default 2 282 283menu "System Type" 284 285config MMU 286 bool "MMU-based Paged Memory Management Support" 287 default y 288 help 289 Select if you want MMU-based virtualised addressing space 290 support by paged memory management. If unsure, say 'Y'. 291 292config ARCH_MMAP_RND_BITS_MIN 293 default 8 294 295config ARCH_MMAP_RND_BITS_MAX 296 default 14 if PAGE_OFFSET=0x40000000 297 default 15 if PAGE_OFFSET=0x80000000 298 default 16 299 300# 301# The "ARM system type" choice list is ordered alphabetically by option 302# text. Please add new entries in the option alphabetic order. 303# 304choice 305 prompt "ARM system type" 306 default ARM_SINGLE_ARMV7M if !MMU 307 default ARCH_MULTIPLATFORM if MMU 308 309config ARCH_MULTIPLATFORM 310 bool "Allow multiple platforms to be selected" 311 depends on MMU 312 select ARM_HAS_SG_CHAIN 313 select ARM_PATCH_PHYS_VIRT 314 select AUTO_ZRELADDR 315 select TIMER_OF 316 select COMMON_CLK 317 select GENERIC_CLOCKEVENTS 318 select GENERIC_IRQ_MULTI_HANDLER 319 select HAVE_PCI 320 select PCI_DOMAINS_GENERIC if PCI 321 select SPARSE_IRQ 322 select USE_OF 323 324config ARM_SINGLE_ARMV7M 325 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 326 depends on !MMU 327 select ARM_NVIC 328 select AUTO_ZRELADDR 329 select TIMER_OF 330 select COMMON_CLK 331 select CPU_V7M 332 select GENERIC_CLOCKEVENTS 333 select NO_IOPORT_MAP 334 select SPARSE_IRQ 335 select USE_OF 336 337config ARCH_EBSA110 338 bool "EBSA-110" 339 select ARCH_USES_GETTIMEOFFSET 340 select CPU_SA110 341 select ISA 342 select NEED_MACH_IO_H 343 select NEED_MACH_MEMORY_H 344 select NO_IOPORT_MAP 345 help 346 This is an evaluation board for the StrongARM processor available 347 from Digital. It has limited hardware on-board, including an 348 Ethernet interface, two PCMCIA sockets, two serial ports and a 349 parallel port. 350 351config ARCH_EP93XX 352 bool "EP93xx-based" 353 select ARCH_SPARSEMEM_ENABLE 354 select ARM_AMBA 355 imply ARM_PATCH_PHYS_VIRT 356 select ARM_VIC 357 select AUTO_ZRELADDR 358 select CLKDEV_LOOKUP 359 select CLKSRC_MMIO 360 select CPU_ARM920T 361 select GENERIC_CLOCKEVENTS 362 select GPIOLIB 363 help 364 This enables support for the Cirrus EP93xx series of CPUs. 365 366config ARCH_FOOTBRIDGE 367 bool "FootBridge" 368 select CPU_SA110 369 select FOOTBRIDGE 370 select GENERIC_CLOCKEVENTS 371 select HAVE_IDE 372 select NEED_MACH_IO_H if !MMU 373 select NEED_MACH_MEMORY_H 374 help 375 Support for systems based on the DC21285 companion chip 376 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 377 378config ARCH_NETX 379 bool "Hilscher NetX based" 380 select ARM_VIC 381 select CLKSRC_MMIO 382 select CPU_ARM926T 383 select GENERIC_CLOCKEVENTS 384 help 385 This enables support for systems based on the Hilscher NetX Soc 386 387config ARCH_IOP13XX 388 bool "IOP13xx-based" 389 depends on MMU 390 select CPU_XSC3 391 select NEED_MACH_MEMORY_H 392 select NEED_RET_TO_USER 393 select FORCE_PCI 394 select PLAT_IOP 395 select VMSPLIT_1G 396 select SPARSE_IRQ 397 help 398 Support for Intel's IOP13XX (XScale) family of processors. 399 400config ARCH_IOP32X 401 bool "IOP32x-based" 402 depends on MMU 403 select CPU_XSCALE 404 select GPIO_IOP 405 select GPIOLIB 406 select NEED_RET_TO_USER 407 select FORCE_PCI 408 select PLAT_IOP 409 help 410 Support for Intel's 80219 and IOP32X (XScale) family of 411 processors. 412 413config ARCH_IOP33X 414 bool "IOP33x-based" 415 depends on MMU 416 select CPU_XSCALE 417 select GPIO_IOP 418 select GPIOLIB 419 select NEED_RET_TO_USER 420 select FORCE_PCI 421 select PLAT_IOP 422 help 423 Support for Intel's IOP33X (XScale) family of processors. 424 425config ARCH_IXP4XX 426 bool "IXP4xx-based" 427 depends on MMU 428 select ARCH_HAS_DMA_SET_COHERENT_MASK 429 select ARCH_SUPPORTS_BIG_ENDIAN 430 select CLKSRC_MMIO 431 select CPU_XSCALE 432 select DMABOUNCE if PCI 433 select GENERIC_CLOCKEVENTS 434 select GPIOLIB 435 select HAVE_PCI 436 select NEED_MACH_IO_H 437 select USB_EHCI_BIG_ENDIAN_DESC 438 select USB_EHCI_BIG_ENDIAN_MMIO 439 help 440 Support for Intel's IXP4XX (XScale) family of processors. 441 442config ARCH_DOVE 443 bool "Marvell Dove" 444 select CPU_PJ4 445 select GENERIC_CLOCKEVENTS 446 select GENERIC_IRQ_MULTI_HANDLER 447 select GPIOLIB 448 select HAVE_PCI 449 select MVEBU_MBUS 450 select PINCTRL 451 select PINCTRL_DOVE 452 select PLAT_ORION_LEGACY 453 select SPARSE_IRQ 454 select PM_GENERIC_DOMAINS if PM 455 help 456 Support for the Marvell Dove SoC 88AP510 457 458config ARCH_KS8695 459 bool "Micrel/Kendin KS8695" 460 select CLKSRC_MMIO 461 select CPU_ARM922T 462 select GENERIC_CLOCKEVENTS 463 select GPIOLIB 464 select NEED_MACH_MEMORY_H 465 help 466 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 467 System-on-Chip devices. 468 469config ARCH_W90X900 470 bool "Nuvoton W90X900 CPU" 471 select CLKDEV_LOOKUP 472 select CLKSRC_MMIO 473 select CPU_ARM926T 474 select GENERIC_CLOCKEVENTS 475 select GPIOLIB 476 help 477 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 478 At present, the w90x900 has been renamed nuc900, regarding 479 the ARM series product line, you can login the following 480 link address to know more. 481 482 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 483 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 484 485config ARCH_LPC32XX 486 bool "NXP LPC32XX" 487 select ARM_AMBA 488 select CLKDEV_LOOKUP 489 select CLKSRC_LPC32XX 490 select COMMON_CLK 491 select CPU_ARM926T 492 select GENERIC_CLOCKEVENTS 493 select GENERIC_IRQ_MULTI_HANDLER 494 select GPIOLIB 495 select SPARSE_IRQ 496 select USE_OF 497 help 498 Support for the NXP LPC32XX family of processors 499 500config ARCH_PXA 501 bool "PXA2xx/PXA3xx-based" 502 depends on MMU 503 select ARCH_MTD_XIP 504 select ARM_CPU_SUSPEND if PM 505 select AUTO_ZRELADDR 506 select COMMON_CLK 507 select CLKDEV_LOOKUP 508 select CLKSRC_PXA 509 select CLKSRC_MMIO 510 select TIMER_OF 511 select CPU_XSCALE if !CPU_XSC3 512 select GENERIC_CLOCKEVENTS 513 select GENERIC_IRQ_MULTI_HANDLER 514 select GPIO_PXA 515 select GPIOLIB 516 select HAVE_IDE 517 select IRQ_DOMAIN 518 select PLAT_PXA 519 select SPARSE_IRQ 520 help 521 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 522 523config ARCH_RPC 524 bool "RiscPC" 525 depends on MMU 526 select ARCH_ACORN 527 select ARCH_MAY_HAVE_PC_FDC 528 select ARCH_SPARSEMEM_ENABLE 529 select ARCH_USES_GETTIMEOFFSET 530 select CPU_SA110 531 select FIQ 532 select HAVE_IDE 533 select HAVE_PATA_PLATFORM 534 select ISA_DMA_API 535 select NEED_MACH_IO_H 536 select NEED_MACH_MEMORY_H 537 select NO_IOPORT_MAP 538 help 539 On the Acorn Risc-PC, Linux can support the internal IDE disk and 540 CD-ROM interface, serial and parallel port, and the floppy drive. 541 542config ARCH_SA1100 543 bool "SA1100-based" 544 select ARCH_MTD_XIP 545 select ARCH_SPARSEMEM_ENABLE 546 select CLKDEV_LOOKUP 547 select CLKSRC_MMIO 548 select CLKSRC_PXA 549 select TIMER_OF if OF 550 select CPU_FREQ 551 select CPU_SA1100 552 select GENERIC_CLOCKEVENTS 553 select GENERIC_IRQ_MULTI_HANDLER 554 select GPIOLIB 555 select HAVE_IDE 556 select IRQ_DOMAIN 557 select ISA 558 select NEED_MACH_MEMORY_H 559 select SPARSE_IRQ 560 help 561 Support for StrongARM 11x0 based boards. 562 563config ARCH_S3C24XX 564 bool "Samsung S3C24XX SoCs" 565 select ATAGS 566 select CLKDEV_LOOKUP 567 select CLKSRC_SAMSUNG_PWM 568 select GENERIC_CLOCKEVENTS 569 select GPIO_SAMSUNG 570 select GPIOLIB 571 select GENERIC_IRQ_MULTI_HANDLER 572 select HAVE_S3C2410_I2C if I2C 573 select HAVE_S3C2410_WATCHDOG if WATCHDOG 574 select HAVE_S3C_RTC if RTC_CLASS 575 select NEED_MACH_IO_H 576 select SAMSUNG_ATAGS 577 select USE_OF 578 help 579 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 580 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 581 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 582 Samsung SMDK2410 development board (and derivatives). 583 584config ARCH_DAVINCI 585 bool "TI DaVinci" 586 select ARCH_HAS_HOLES_MEMORYMODEL 587 select COMMON_CLK 588 select CPU_ARM926T 589 select GENERIC_ALLOCATOR 590 select GENERIC_CLOCKEVENTS 591 select GENERIC_IRQ_CHIP 592 select GPIOLIB 593 select HAVE_IDE 594 select PM_GENERIC_DOMAINS if PM 595 select PM_GENERIC_DOMAINS_OF if PM && OF 596 select RESET_CONTROLLER 597 select USE_OF 598 select ZONE_DMA 599 help 600 Support for TI's DaVinci platform. 601 602config ARCH_OMAP1 603 bool "TI OMAP1" 604 depends on MMU 605 select ARCH_HAS_HOLES_MEMORYMODEL 606 select ARCH_OMAP 607 select CLKDEV_LOOKUP 608 select CLKSRC_MMIO 609 select GENERIC_CLOCKEVENTS 610 select GENERIC_IRQ_CHIP 611 select GENERIC_IRQ_MULTI_HANDLER 612 select GPIOLIB 613 select HAVE_IDE 614 select IRQ_DOMAIN 615 select NEED_MACH_IO_H if PCCARD 616 select NEED_MACH_MEMORY_H 617 select SPARSE_IRQ 618 help 619 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 620 621endchoice 622 623menu "Multiple platform selection" 624 depends on ARCH_MULTIPLATFORM 625 626comment "CPU Core family selection" 627 628config ARCH_MULTI_V4 629 bool "ARMv4 based platforms (FA526)" 630 depends on !ARCH_MULTI_V6_V7 631 select ARCH_MULTI_V4_V5 632 select CPU_FA526 633 634config ARCH_MULTI_V4T 635 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 636 depends on !ARCH_MULTI_V6_V7 637 select ARCH_MULTI_V4_V5 638 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 639 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 640 CPU_ARM925T || CPU_ARM940T) 641 642config ARCH_MULTI_V5 643 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 644 depends on !ARCH_MULTI_V6_V7 645 select ARCH_MULTI_V4_V5 646 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 647 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 648 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 649 650config ARCH_MULTI_V4_V5 651 bool 652 653config ARCH_MULTI_V6 654 bool "ARMv6 based platforms (ARM11)" 655 select ARCH_MULTI_V6_V7 656 select CPU_V6K 657 658config ARCH_MULTI_V7 659 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 660 default y 661 select ARCH_MULTI_V6_V7 662 select CPU_V7 663 select HAVE_SMP 664 665config ARCH_MULTI_V6_V7 666 bool 667 select MIGHT_HAVE_CACHE_L2X0 668 669config ARCH_MULTI_CPU_AUTO 670 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 671 select ARCH_MULTI_V5 672 673endmenu 674 675config ARCH_VIRT 676 bool "Dummy Virtual Machine" 677 depends on ARCH_MULTI_V7 678 select ARM_AMBA 679 select ARM_GIC 680 select ARM_GIC_V2M if PCI 681 select ARM_GIC_V3 682 select ARM_GIC_V3_ITS if PCI 683 select ARM_PSCI 684 select HAVE_ARM_ARCH_TIMER 685 select ARCH_SUPPORTS_BIG_ENDIAN 686 687# 688# This is sorted alphabetically by mach-* pathname. However, plat-* 689# Kconfigs may be included either alphabetically (according to the 690# plat- suffix) or along side the corresponding mach-* source. 691# 692source "arch/arm/mach-actions/Kconfig" 693 694source "arch/arm/mach-alpine/Kconfig" 695 696source "arch/arm/mach-artpec/Kconfig" 697 698source "arch/arm/mach-asm9260/Kconfig" 699 700source "arch/arm/mach-aspeed/Kconfig" 701 702source "arch/arm/mach-at91/Kconfig" 703 704source "arch/arm/mach-axxia/Kconfig" 705 706source "arch/arm/mach-bcm/Kconfig" 707 708source "arch/arm/mach-berlin/Kconfig" 709 710source "arch/arm/mach-clps711x/Kconfig" 711 712source "arch/arm/mach-cns3xxx/Kconfig" 713 714source "arch/arm/mach-davinci/Kconfig" 715 716source "arch/arm/mach-digicolor/Kconfig" 717 718source "arch/arm/mach-dove/Kconfig" 719 720source "arch/arm/mach-ep93xx/Kconfig" 721 722source "arch/arm/mach-exynos/Kconfig" 723source "arch/arm/plat-samsung/Kconfig" 724 725source "arch/arm/mach-footbridge/Kconfig" 726 727source "arch/arm/mach-gemini/Kconfig" 728 729source "arch/arm/mach-highbank/Kconfig" 730 731source "arch/arm/mach-hisi/Kconfig" 732 733source "arch/arm/mach-imx/Kconfig" 734 735source "arch/arm/mach-integrator/Kconfig" 736 737source "arch/arm/mach-iop13xx/Kconfig" 738 739source "arch/arm/mach-iop32x/Kconfig" 740 741source "arch/arm/mach-iop33x/Kconfig" 742 743source "arch/arm/mach-ixp4xx/Kconfig" 744 745source "arch/arm/mach-keystone/Kconfig" 746 747source "arch/arm/mach-ks8695/Kconfig" 748 749source "arch/arm/mach-mediatek/Kconfig" 750 751source "arch/arm/mach-meson/Kconfig" 752 753source "arch/arm/mach-mmp/Kconfig" 754 755source "arch/arm/mach-moxart/Kconfig" 756 757source "arch/arm/mach-mv78xx0/Kconfig" 758 759source "arch/arm/mach-mvebu/Kconfig" 760 761source "arch/arm/mach-mxs/Kconfig" 762 763source "arch/arm/mach-netx/Kconfig" 764 765source "arch/arm/mach-nomadik/Kconfig" 766 767source "arch/arm/mach-npcm/Kconfig" 768 769source "arch/arm/mach-nspire/Kconfig" 770 771source "arch/arm/plat-omap/Kconfig" 772 773source "arch/arm/mach-omap1/Kconfig" 774 775source "arch/arm/mach-omap2/Kconfig" 776 777source "arch/arm/mach-orion5x/Kconfig" 778 779source "arch/arm/mach-oxnas/Kconfig" 780 781source "arch/arm/mach-picoxcell/Kconfig" 782 783source "arch/arm/mach-prima2/Kconfig" 784 785source "arch/arm/mach-pxa/Kconfig" 786source "arch/arm/plat-pxa/Kconfig" 787 788source "arch/arm/mach-qcom/Kconfig" 789 790source "arch/arm/mach-rda/Kconfig" 791 792source "arch/arm/mach-realview/Kconfig" 793 794source "arch/arm/mach-rockchip/Kconfig" 795 796source "arch/arm/mach-s3c24xx/Kconfig" 797 798source "arch/arm/mach-s3c64xx/Kconfig" 799 800source "arch/arm/mach-s5pv210/Kconfig" 801 802source "arch/arm/mach-sa1100/Kconfig" 803 804source "arch/arm/mach-shmobile/Kconfig" 805 806source "arch/arm/mach-socfpga/Kconfig" 807 808source "arch/arm/mach-spear/Kconfig" 809 810source "arch/arm/mach-sti/Kconfig" 811 812source "arch/arm/mach-stm32/Kconfig" 813 814source "arch/arm/mach-sunxi/Kconfig" 815 816source "arch/arm/mach-tango/Kconfig" 817 818source "arch/arm/mach-tegra/Kconfig" 819 820source "arch/arm/mach-u300/Kconfig" 821 822source "arch/arm/mach-uniphier/Kconfig" 823 824source "arch/arm/mach-ux500/Kconfig" 825 826source "arch/arm/mach-versatile/Kconfig" 827 828source "arch/arm/mach-vexpress/Kconfig" 829source "arch/arm/plat-versatile/Kconfig" 830 831source "arch/arm/mach-vt8500/Kconfig" 832 833source "arch/arm/mach-w90x900/Kconfig" 834 835source "arch/arm/mach-zx/Kconfig" 836 837source "arch/arm/mach-zynq/Kconfig" 838 839# ARMv7-M architecture 840config ARCH_EFM32 841 bool "Energy Micro efm32" 842 depends on ARM_SINGLE_ARMV7M 843 select GPIOLIB 844 help 845 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 846 processors. 847 848config ARCH_LPC18XX 849 bool "NXP LPC18xx/LPC43xx" 850 depends on ARM_SINGLE_ARMV7M 851 select ARCH_HAS_RESET_CONTROLLER 852 select ARM_AMBA 853 select CLKSRC_LPC32XX 854 select PINCTRL 855 help 856 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 857 high performance microcontrollers. 858 859config ARCH_MPS2 860 bool "ARM MPS2 platform" 861 depends on ARM_SINGLE_ARMV7M 862 select ARM_AMBA 863 select CLKSRC_MPS2 864 help 865 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 866 with a range of available cores like Cortex-M3/M4/M7. 867 868 Please, note that depends which Application Note is used memory map 869 for the platform may vary, so adjustment of RAM base might be needed. 870 871# Definitions to make life easier 872config ARCH_ACORN 873 bool 874 875config PLAT_IOP 876 bool 877 select GENERIC_CLOCKEVENTS 878 879config PLAT_ORION 880 bool 881 select CLKSRC_MMIO 882 select COMMON_CLK 883 select GENERIC_IRQ_CHIP 884 select IRQ_DOMAIN 885 886config PLAT_ORION_LEGACY 887 bool 888 select PLAT_ORION 889 890config PLAT_PXA 891 bool 892 893config PLAT_VERSATILE 894 bool 895 896source "arch/arm/firmware/Kconfig" 897 898source "arch/arm/mm/Kconfig" 899 900config IWMMXT 901 bool "Enable iWMMXt support" 902 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 903 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 904 help 905 Enable support for iWMMXt context switching at run time if 906 running on a CPU that supports it. 907 908if !MMU 909source "arch/arm/Kconfig-nommu" 910endif 911 912config PJ4B_ERRATA_4742 913 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 914 depends on CPU_PJ4B && MACH_ARMADA_370 915 default y 916 help 917 When coming out of either a Wait for Interrupt (WFI) or a Wait for 918 Event (WFE) IDLE states, a specific timing sensitivity exists between 919 the retiring WFI/WFE instructions and the newly issued subsequent 920 instructions. This sensitivity can result in a CPU hang scenario. 921 Workaround: 922 The software must insert either a Data Synchronization Barrier (DSB) 923 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 924 instruction 925 926config ARM_ERRATA_326103 927 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 928 depends on CPU_V6 929 help 930 Executing a SWP instruction to read-only memory does not set bit 11 931 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 932 treat the access as a read, preventing a COW from occurring and 933 causing the faulting task to livelock. 934 935config ARM_ERRATA_411920 936 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 937 depends on CPU_V6 || CPU_V6K 938 help 939 Invalidation of the Instruction Cache operation can 940 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 941 It does not affect the MPCore. This option enables the ARM Ltd. 942 recommended workaround. 943 944config ARM_ERRATA_430973 945 bool "ARM errata: Stale prediction on replaced interworking branch" 946 depends on CPU_V7 947 help 948 This option enables the workaround for the 430973 Cortex-A8 949 r1p* erratum. If a code sequence containing an ARM/Thumb 950 interworking branch is replaced with another code sequence at the 951 same virtual address, whether due to self-modifying code or virtual 952 to physical address re-mapping, Cortex-A8 does not recover from the 953 stale interworking branch prediction. This results in Cortex-A8 954 executing the new code sequence in the incorrect ARM or Thumb state. 955 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 956 and also flushes the branch target cache at every context switch. 957 Note that setting specific bits in the ACTLR register may not be 958 available in non-secure mode. 959 960config ARM_ERRATA_458693 961 bool "ARM errata: Processor deadlock when a false hazard is created" 962 depends on CPU_V7 963 depends on !ARCH_MULTIPLATFORM 964 help 965 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 966 erratum. For very specific sequences of memory operations, it is 967 possible for a hazard condition intended for a cache line to instead 968 be incorrectly associated with a different cache line. This false 969 hazard might then cause a processor deadlock. The workaround enables 970 the L1 caching of the NEON accesses and disables the PLD instruction 971 in the ACTLR register. Note that setting specific bits in the ACTLR 972 register may not be available in non-secure mode. 973 974config ARM_ERRATA_460075 975 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 976 depends on CPU_V7 977 depends on !ARCH_MULTIPLATFORM 978 help 979 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 980 erratum. Any asynchronous access to the L2 cache may encounter a 981 situation in which recent store transactions to the L2 cache are lost 982 and overwritten with stale memory contents from external memory. The 983 workaround disables the write-allocate mode for the L2 cache via the 984 ACTLR register. Note that setting specific bits in the ACTLR register 985 may not be available in non-secure mode. 986 987config ARM_ERRATA_742230 988 bool "ARM errata: DMB operation may be faulty" 989 depends on CPU_V7 && SMP 990 depends on !ARCH_MULTIPLATFORM 991 help 992 This option enables the workaround for the 742230 Cortex-A9 993 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 994 between two write operations may not ensure the correct visibility 995 ordering of the two writes. This workaround sets a specific bit in 996 the diagnostic register of the Cortex-A9 which causes the DMB 997 instruction to behave as a DSB, ensuring the correct behaviour of 998 the two writes. 999 1000config ARM_ERRATA_742231 1001 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1002 depends on CPU_V7 && SMP 1003 depends on !ARCH_MULTIPLATFORM 1004 help 1005 This option enables the workaround for the 742231 Cortex-A9 1006 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1007 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1008 accessing some data located in the same cache line, may get corrupted 1009 data due to bad handling of the address hazard when the line gets 1010 replaced from one of the CPUs at the same time as another CPU is 1011 accessing it. This workaround sets specific bits in the diagnostic 1012 register of the Cortex-A9 which reduces the linefill issuing 1013 capabilities of the processor. 1014 1015config ARM_ERRATA_643719 1016 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1017 depends on CPU_V7 && SMP 1018 default y 1019 help 1020 This option enables the workaround for the 643719 Cortex-A9 (prior to 1021 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1022 register returns zero when it should return one. The workaround 1023 corrects this value, ensuring cache maintenance operations which use 1024 it behave as intended and avoiding data corruption. 1025 1026config ARM_ERRATA_720789 1027 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1028 depends on CPU_V7 1029 help 1030 This option enables the workaround for the 720789 Cortex-A9 (prior to 1031 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1032 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1033 As a consequence of this erratum, some TLB entries which should be 1034 invalidated are not, resulting in an incoherency in the system page 1035 tables. The workaround changes the TLB flushing routines to invalidate 1036 entries regardless of the ASID. 1037 1038config ARM_ERRATA_743622 1039 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1040 depends on CPU_V7 1041 depends on !ARCH_MULTIPLATFORM 1042 help 1043 This option enables the workaround for the 743622 Cortex-A9 1044 (r2p*) erratum. Under very rare conditions, a faulty 1045 optimisation in the Cortex-A9 Store Buffer may lead to data 1046 corruption. This workaround sets a specific bit in the diagnostic 1047 register of the Cortex-A9 which disables the Store Buffer 1048 optimisation, preventing the defect from occurring. This has no 1049 visible impact on the overall performance or power consumption of the 1050 processor. 1051 1052config ARM_ERRATA_751472 1053 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1054 depends on CPU_V7 1055 depends on !ARCH_MULTIPLATFORM 1056 help 1057 This option enables the workaround for the 751472 Cortex-A9 (prior 1058 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1059 completion of a following broadcasted operation if the second 1060 operation is received by a CPU before the ICIALLUIS has completed, 1061 potentially leading to corrupted entries in the cache or TLB. 1062 1063config ARM_ERRATA_754322 1064 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1065 depends on CPU_V7 1066 help 1067 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1068 r3p*) erratum. A speculative memory access may cause a page table walk 1069 which starts prior to an ASID switch but completes afterwards. This 1070 can populate the micro-TLB with a stale entry which may be hit with 1071 the new ASID. This workaround places two dsb instructions in the mm 1072 switching code so that no page table walks can cross the ASID switch. 1073 1074config ARM_ERRATA_754327 1075 bool "ARM errata: no automatic Store Buffer drain" 1076 depends on CPU_V7 && SMP 1077 help 1078 This option enables the workaround for the 754327 Cortex-A9 (prior to 1079 r2p0) erratum. The Store Buffer does not have any automatic draining 1080 mechanism and therefore a livelock may occur if an external agent 1081 continuously polls a memory location waiting to observe an update. 1082 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1083 written polling loops from denying visibility of updates to memory. 1084 1085config ARM_ERRATA_364296 1086 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1087 depends on CPU_V6 1088 help 1089 This options enables the workaround for the 364296 ARM1136 1090 r0p2 erratum (possible cache data corruption with 1091 hit-under-miss enabled). It sets the undocumented bit 31 in 1092 the auxiliary control register and the FI bit in the control 1093 register, thus disabling hit-under-miss without putting the 1094 processor into full low interrupt latency mode. ARM11MPCore 1095 is not affected. 1096 1097config ARM_ERRATA_764369 1098 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1099 depends on CPU_V7 && SMP 1100 help 1101 This option enables the workaround for erratum 764369 1102 affecting Cortex-A9 MPCore with two or more processors (all 1103 current revisions). Under certain timing circumstances, a data 1104 cache line maintenance operation by MVA targeting an Inner 1105 Shareable memory region may fail to proceed up to either the 1106 Point of Coherency or to the Point of Unification of the 1107 system. This workaround adds a DSB instruction before the 1108 relevant cache maintenance functions and sets a specific bit 1109 in the diagnostic control register of the SCU. 1110 1111config ARM_ERRATA_775420 1112 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1113 depends on CPU_V7 1114 help 1115 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1116 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1117 operation aborts with MMU exception, it might cause the processor 1118 to deadlock. This workaround puts DSB before executing ISB if 1119 an abort may occur on cache maintenance. 1120 1121config ARM_ERRATA_798181 1122 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1123 depends on CPU_V7 && SMP 1124 help 1125 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1126 adequately shooting down all use of the old entries. This 1127 option enables the Linux kernel workaround for this erratum 1128 which sends an IPI to the CPUs that are running the same ASID 1129 as the one being invalidated. 1130 1131config ARM_ERRATA_773022 1132 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1133 depends on CPU_V7 1134 help 1135 This option enables the workaround for the 773022 Cortex-A15 1136 (up to r0p4) erratum. In certain rare sequences of code, the 1137 loop buffer may deliver incorrect instructions. This 1138 workaround disables the loop buffer to avoid the erratum. 1139 1140config ARM_ERRATA_818325_852422 1141 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1142 depends on CPU_V7 1143 help 1144 This option enables the workaround for: 1145 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1146 instruction might deadlock. Fixed in r0p1. 1147 - Cortex-A12 852422: Execution of a sequence of instructions might 1148 lead to either a data corruption or a CPU deadlock. Not fixed in 1149 any Cortex-A12 cores yet. 1150 This workaround for all both errata involves setting bit[12] of the 1151 Feature Register. This bit disables an optimisation applied to a 1152 sequence of 2 instructions that use opposing condition codes. 1153 1154config ARM_ERRATA_821420 1155 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1156 depends on CPU_V7 1157 help 1158 This option enables the workaround for the 821420 Cortex-A12 1159 (all revs) erratum. In very rare timing conditions, a sequence 1160 of VMOV to Core registers instructions, for which the second 1161 one is in the shadow of a branch or abort, can lead to a 1162 deadlock when the VMOV instructions are issued out-of-order. 1163 1164config ARM_ERRATA_825619 1165 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1166 depends on CPU_V7 1167 help 1168 This option enables the workaround for the 825619 Cortex-A12 1169 (all revs) erratum. Within rare timing constraints, executing a 1170 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1171 and Device/Strongly-Ordered loads and stores might cause deadlock 1172 1173config ARM_ERRATA_852421 1174 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1175 depends on CPU_V7 1176 help 1177 This option enables the workaround for the 852421 Cortex-A17 1178 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1179 execution of a DMB ST instruction might fail to properly order 1180 stores from GroupA and stores from GroupB. 1181 1182config ARM_ERRATA_852423 1183 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1184 depends on CPU_V7 1185 help 1186 This option enables the workaround for: 1187 - Cortex-A17 852423: Execution of a sequence of instructions might 1188 lead to either a data corruption or a CPU deadlock. Not fixed in 1189 any Cortex-A17 cores yet. 1190 This is identical to Cortex-A12 erratum 852422. It is a separate 1191 config option from the A12 erratum due to the way errata are checked 1192 for and handled. 1193 1194endmenu 1195 1196source "arch/arm/common/Kconfig" 1197 1198menu "Bus support" 1199 1200config ISA 1201 bool 1202 help 1203 Find out whether you have ISA slots on your motherboard. ISA is the 1204 name of a bus system, i.e. the way the CPU talks to the other stuff 1205 inside your box. Other bus systems are PCI, EISA, MicroChannel 1206 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1207 newer boards don't support it. If you have ISA, say Y, otherwise N. 1208 1209# Select ISA DMA controller support 1210config ISA_DMA 1211 bool 1212 select ISA_DMA_API 1213 1214# Select ISA DMA interface 1215config ISA_DMA_API 1216 bool 1217 1218config PCI_NANOENGINE 1219 bool "BSE nanoEngine PCI support" 1220 depends on SA1100_NANOENGINE 1221 help 1222 Enable PCI on the BSE nanoEngine board. 1223 1224config PCI_HOST_ITE8152 1225 bool 1226 depends on PCI && MACH_ARMCORE 1227 default y 1228 select DMABOUNCE 1229 1230endmenu 1231 1232menu "Kernel Features" 1233 1234config HAVE_SMP 1235 bool 1236 help 1237 This option should be selected by machines which have an SMP- 1238 capable CPU. 1239 1240 The only effect of this option is to make the SMP-related 1241 options available to the user for configuration. 1242 1243config SMP 1244 bool "Symmetric Multi-Processing" 1245 depends on CPU_V6K || CPU_V7 1246 depends on GENERIC_CLOCKEVENTS 1247 depends on HAVE_SMP 1248 depends on MMU || ARM_MPU 1249 select IRQ_WORK 1250 help 1251 This enables support for systems with more than one CPU. If you have 1252 a system with only one CPU, say N. If you have a system with more 1253 than one CPU, say Y. 1254 1255 If you say N here, the kernel will run on uni- and multiprocessor 1256 machines, but will use only one CPU of a multiprocessor machine. If 1257 you say Y here, the kernel will run on many, but not all, 1258 uniprocessor machines. On a uniprocessor machine, the kernel 1259 will run faster if you say N here. 1260 1261 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1262 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at 1263 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1264 1265 If you don't know what to do here, say N. 1266 1267config SMP_ON_UP 1268 bool "Allow booting SMP kernel on uniprocessor systems" 1269 depends on SMP && !XIP_KERNEL && MMU 1270 default y 1271 help 1272 SMP kernels contain instructions which fail on non-SMP processors. 1273 Enabling this option allows the kernel to modify itself to make 1274 these instructions safe. Disabling it allows about 1K of space 1275 savings. 1276 1277 If you don't know what to do here, say Y. 1278 1279config ARM_CPU_TOPOLOGY 1280 bool "Support cpu topology definition" 1281 depends on SMP && CPU_V7 1282 default y 1283 help 1284 Support ARM cpu topology definition. The MPIDR register defines 1285 affinity between processors which is then used to describe the cpu 1286 topology of an ARM System. 1287 1288config SCHED_MC 1289 bool "Multi-core scheduler support" 1290 depends on ARM_CPU_TOPOLOGY 1291 help 1292 Multi-core scheduler support improves the CPU scheduler's decision 1293 making when dealing with multi-core CPU chips at a cost of slightly 1294 increased overhead in some places. If unsure say N here. 1295 1296config SCHED_SMT 1297 bool "SMT scheduler support" 1298 depends on ARM_CPU_TOPOLOGY 1299 help 1300 Improves the CPU scheduler's decision making when dealing with 1301 MultiThreading at a cost of slightly increased overhead in some 1302 places. If unsure say N here. 1303 1304config HAVE_ARM_SCU 1305 bool 1306 help 1307 This option enables support for the ARM system coherency unit 1308 1309config HAVE_ARM_ARCH_TIMER 1310 bool "Architected timer support" 1311 depends on CPU_V7 1312 select ARM_ARCH_TIMER 1313 select GENERIC_CLOCKEVENTS 1314 help 1315 This option enables support for the ARM architected timer 1316 1317config HAVE_ARM_TWD 1318 bool 1319 select TIMER_OF if OF 1320 help 1321 This options enables support for the ARM timer and watchdog unit 1322 1323config MCPM 1324 bool "Multi-Cluster Power Management" 1325 depends on CPU_V7 && SMP 1326 help 1327 This option provides the common power management infrastructure 1328 for (multi-)cluster based systems, such as big.LITTLE based 1329 systems. 1330 1331config MCPM_QUAD_CLUSTER 1332 bool 1333 depends on MCPM 1334 help 1335 To avoid wasting resources unnecessarily, MCPM only supports up 1336 to 2 clusters by default. 1337 Platforms with 3 or 4 clusters that use MCPM must select this 1338 option to allow the additional clusters to be managed. 1339 1340config BIG_LITTLE 1341 bool "big.LITTLE support (Experimental)" 1342 depends on CPU_V7 && SMP 1343 select MCPM 1344 help 1345 This option enables support selections for the big.LITTLE 1346 system architecture. 1347 1348config BL_SWITCHER 1349 bool "big.LITTLE switcher support" 1350 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1351 select CPU_PM 1352 help 1353 The big.LITTLE "switcher" provides the core functionality to 1354 transparently handle transition between a cluster of A15's 1355 and a cluster of A7's in a big.LITTLE system. 1356 1357config BL_SWITCHER_DUMMY_IF 1358 tristate "Simple big.LITTLE switcher user interface" 1359 depends on BL_SWITCHER && DEBUG_KERNEL 1360 help 1361 This is a simple and dummy char dev interface to control 1362 the big.LITTLE switcher core code. It is meant for 1363 debugging purposes only. 1364 1365choice 1366 prompt "Memory split" 1367 depends on MMU 1368 default VMSPLIT_3G 1369 help 1370 Select the desired split between kernel and user memory. 1371 1372 If you are not absolutely sure what you are doing, leave this 1373 option alone! 1374 1375 config VMSPLIT_3G 1376 bool "3G/1G user/kernel split" 1377 config VMSPLIT_3G_OPT 1378 depends on !ARM_LPAE 1379 bool "3G/1G user/kernel split (for full 1G low memory)" 1380 config VMSPLIT_2G 1381 bool "2G/2G user/kernel split" 1382 config VMSPLIT_1G 1383 bool "1G/3G user/kernel split" 1384endchoice 1385 1386config PAGE_OFFSET 1387 hex 1388 default PHYS_OFFSET if !MMU 1389 default 0x40000000 if VMSPLIT_1G 1390 default 0x80000000 if VMSPLIT_2G 1391 default 0xB0000000 if VMSPLIT_3G_OPT 1392 default 0xC0000000 1393 1394config NR_CPUS 1395 int "Maximum number of CPUs (2-32)" 1396 range 2 32 1397 depends on SMP 1398 default "4" 1399 1400config HOTPLUG_CPU 1401 bool "Support for hot-pluggable CPUs" 1402 depends on SMP 1403 help 1404 Say Y here to experiment with turning CPUs off and on. CPUs 1405 can be controlled through /sys/devices/system/cpu. 1406 1407config ARM_PSCI 1408 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1409 depends on HAVE_ARM_SMCCC 1410 select ARM_PSCI_FW 1411 help 1412 Say Y here if you want Linux to communicate with system firmware 1413 implementing the PSCI specification for CPU-centric power 1414 management operations described in ARM document number ARM DEN 1415 0022A ("Power State Coordination Interface System Software on 1416 ARM processors"). 1417 1418# The GPIO number here must be sorted by descending number. In case of 1419# a multiplatform kernel, we just want the highest value required by the 1420# selected platforms. 1421config ARCH_NR_GPIO 1422 int 1423 default 2048 if ARCH_SOCFPGA 1424 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1425 ARCH_ZYNQ 1426 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1427 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1428 default 416 if ARCH_SUNXI 1429 default 392 if ARCH_U8500 1430 default 352 if ARCH_VT8500 1431 default 288 if ARCH_ROCKCHIP 1432 default 264 if MACH_H4700 1433 default 0 1434 help 1435 Maximum number of GPIOs in the system. 1436 1437 If unsure, leave the default value. 1438 1439config HZ_FIXED 1440 int 1441 default 200 if ARCH_EBSA110 1442 default 128 if SOC_AT91RM9200 1443 default 0 1444 1445choice 1446 depends on HZ_FIXED = 0 1447 prompt "Timer frequency" 1448 1449config HZ_100 1450 bool "100 Hz" 1451 1452config HZ_200 1453 bool "200 Hz" 1454 1455config HZ_250 1456 bool "250 Hz" 1457 1458config HZ_300 1459 bool "300 Hz" 1460 1461config HZ_500 1462 bool "500 Hz" 1463 1464config HZ_1000 1465 bool "1000 Hz" 1466 1467endchoice 1468 1469config HZ 1470 int 1471 default HZ_FIXED if HZ_FIXED != 0 1472 default 100 if HZ_100 1473 default 200 if HZ_200 1474 default 250 if HZ_250 1475 default 300 if HZ_300 1476 default 500 if HZ_500 1477 default 1000 1478 1479config SCHED_HRTICK 1480 def_bool HIGH_RES_TIMERS 1481 1482config THUMB2_KERNEL 1483 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1484 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1485 default y if CPU_THUMBONLY 1486 select ARM_UNWIND 1487 help 1488 By enabling this option, the kernel will be compiled in 1489 Thumb-2 mode. 1490 1491 If unsure, say N. 1492 1493config THUMB2_AVOID_R_ARM_THM_JUMP11 1494 bool "Work around buggy Thumb-2 short branch relocations in gas" 1495 depends on THUMB2_KERNEL && MODULES 1496 default y 1497 help 1498 Various binutils versions can resolve Thumb-2 branches to 1499 locally-defined, preemptible global symbols as short-range "b.n" 1500 branch instructions. 1501 1502 This is a problem, because there's no guarantee the final 1503 destination of the symbol, or any candidate locations for a 1504 trampoline, are within range of the branch. For this reason, the 1505 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1506 relocation in modules at all, and it makes little sense to add 1507 support. 1508 1509 The symptom is that the kernel fails with an "unsupported 1510 relocation" error when loading some modules. 1511 1512 Until fixed tools are available, passing 1513 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1514 code which hits this problem, at the cost of a bit of extra runtime 1515 stack usage in some cases. 1516 1517 The problem is described in more detail at: 1518 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1519 1520 Only Thumb-2 kernels are affected. 1521 1522 Unless you are sure your tools don't have this problem, say Y. 1523 1524config ARM_PATCH_IDIV 1525 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1526 depends on CPU_32v7 && !XIP_KERNEL 1527 default y 1528 help 1529 The ARM compiler inserts calls to __aeabi_idiv() and 1530 __aeabi_uidiv() when it needs to perform division on signed 1531 and unsigned integers. Some v7 CPUs have support for the sdiv 1532 and udiv instructions that can be used to implement those 1533 functions. 1534 1535 Enabling this option allows the kernel to modify itself to 1536 replace the first two instructions of these library functions 1537 with the sdiv or udiv plus "bx lr" instructions when the CPU 1538 it is running on supports them. Typically this will be faster 1539 and less power intensive than running the original library 1540 code to do integer division. 1541 1542config AEABI 1543 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K 1544 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K 1545 help 1546 This option allows for the kernel to be compiled using the latest 1547 ARM ABI (aka EABI). This is only useful if you are using a user 1548 space environment that is also compiled with EABI. 1549 1550 Since there are major incompatibilities between the legacy ABI and 1551 EABI, especially with regard to structure member alignment, this 1552 option also changes the kernel syscall calling convention to 1553 disambiguate both ABIs and allow for backward compatibility support 1554 (selected with CONFIG_OABI_COMPAT). 1555 1556 To use this you need GCC version 4.0.0 or later. 1557 1558config OABI_COMPAT 1559 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1560 depends on AEABI && !THUMB2_KERNEL 1561 help 1562 This option preserves the old syscall interface along with the 1563 new (ARM EABI) one. It also provides a compatibility layer to 1564 intercept syscalls that have structure arguments which layout 1565 in memory differs between the legacy ABI and the new ARM EABI 1566 (only for non "thumb" binaries). This option adds a tiny 1567 overhead to all syscalls and produces a slightly larger kernel. 1568 1569 The seccomp filter system will not be available when this is 1570 selected, since there is no way yet to sensibly distinguish 1571 between calling conventions during filtering. 1572 1573 If you know you'll be using only pure EABI user space then you 1574 can say N here. If this option is not selected and you attempt 1575 to execute a legacy ABI binary then the result will be 1576 UNPREDICTABLE (in fact it can be predicted that it won't work 1577 at all). If in doubt say N. 1578 1579config ARCH_HAS_HOLES_MEMORYMODEL 1580 bool 1581 1582config ARCH_SPARSEMEM_ENABLE 1583 bool 1584 1585config ARCH_SPARSEMEM_DEFAULT 1586 def_bool ARCH_SPARSEMEM_ENABLE 1587 1588config ARCH_SELECT_MEMORY_MODEL 1589 def_bool ARCH_SPARSEMEM_ENABLE 1590 1591config HAVE_ARCH_PFN_VALID 1592 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1593 1594config HAVE_GENERIC_GUP 1595 def_bool y 1596 depends on ARM_LPAE 1597 1598config HIGHMEM 1599 bool "High Memory Support" 1600 depends on MMU 1601 help 1602 The address space of ARM processors is only 4 Gigabytes large 1603 and it has to accommodate user address space, kernel address 1604 space as well as some memory mapped IO. That means that, if you 1605 have a large amount of physical memory and/or IO, not all of the 1606 memory can be "permanently mapped" by the kernel. The physical 1607 memory that is not permanently mapped is called "high memory". 1608 1609 Depending on the selected kernel/user memory split, minimum 1610 vmalloc space and actual amount of RAM, you may not need this 1611 option which should result in a slightly faster kernel. 1612 1613 If unsure, say n. 1614 1615config HIGHPTE 1616 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1617 depends on HIGHMEM 1618 default y 1619 help 1620 The VM uses one page of physical memory for each page table. 1621 For systems with a lot of processes, this can use a lot of 1622 precious low memory, eventually leading to low memory being 1623 consumed by page tables. Setting this option will allow 1624 user-space 2nd level page tables to reside in high memory. 1625 1626config CPU_SW_DOMAIN_PAN 1627 bool "Enable use of CPU domains to implement privileged no-access" 1628 depends on MMU && !ARM_LPAE 1629 default y 1630 help 1631 Increase kernel security by ensuring that normal kernel accesses 1632 are unable to access userspace addresses. This can help prevent 1633 use-after-free bugs becoming an exploitable privilege escalation 1634 by ensuring that magic values (such as LIST_POISON) will always 1635 fault when dereferenced. 1636 1637 CPUs with low-vector mappings use a best-efforts implementation. 1638 Their lower 1MB needs to remain accessible for the vectors, but 1639 the remainder of userspace will become appropriately inaccessible. 1640 1641config HW_PERF_EVENTS 1642 def_bool y 1643 depends on ARM_PMU 1644 1645config SYS_SUPPORTS_HUGETLBFS 1646 def_bool y 1647 depends on ARM_LPAE 1648 1649config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1650 def_bool y 1651 depends on ARM_LPAE 1652 1653config ARCH_WANT_GENERAL_HUGETLB 1654 def_bool y 1655 1656config ARM_MODULE_PLTS 1657 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1658 depends on MODULES 1659 default y 1660 help 1661 Allocate PLTs when loading modules so that jumps and calls whose 1662 targets are too far away for their relative offsets to be encoded 1663 in the instructions themselves can be bounced via veneers in the 1664 module's PLT. This allows modules to be allocated in the generic 1665 vmalloc area after the dedicated module memory area has been 1666 exhausted. The modules will use slightly more memory, but after 1667 rounding up to page size, the actual memory footprint is usually 1668 the same. 1669 1670 Disabling this is usually safe for small single-platform 1671 configurations. If unsure, say y. 1672 1673config FORCE_MAX_ZONEORDER 1674 int "Maximum zone order" 1675 default "12" if SOC_AM33XX 1676 default "9" if SA1111 || ARCH_EFM32 1677 default "11" 1678 help 1679 The kernel memory allocator divides physically contiguous memory 1680 blocks into "zones", where each zone is a power of two number of 1681 pages. This option selects the largest power of two that the kernel 1682 keeps in the memory allocator. If you need to allocate very large 1683 blocks of physically contiguous memory, then you may need to 1684 increase this value. 1685 1686 This config option is actually maximum order plus one. For example, 1687 a value of 11 means that the largest free memory block is 2^10 pages. 1688 1689config ALIGNMENT_TRAP 1690 bool 1691 depends on CPU_CP15_MMU 1692 default y if !ARCH_EBSA110 1693 select HAVE_PROC_CPU if PROC_FS 1694 help 1695 ARM processors cannot fetch/store information which is not 1696 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1697 address divisible by 4. On 32-bit ARM processors, these non-aligned 1698 fetch/store instructions will be emulated in software if you say 1699 here, which has a severe performance impact. This is necessary for 1700 correct operation of some network protocols. With an IP-only 1701 configuration it is safe to say N, otherwise say Y. 1702 1703config UACCESS_WITH_MEMCPY 1704 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1705 depends on MMU 1706 default y if CPU_FEROCEON 1707 help 1708 Implement faster copy_to_user and clear_user methods for CPU 1709 cores where a 8-word STM instruction give significantly higher 1710 memory write throughput than a sequence of individual 32bit stores. 1711 1712 A possible side effect is a slight increase in scheduling latency 1713 between threads sharing the same address space if they invoke 1714 such copy operations with large buffers. 1715 1716 However, if the CPU data cache is using a write-allocate mode, 1717 this option is unlikely to provide any performance gain. 1718 1719config SECCOMP 1720 bool 1721 prompt "Enable seccomp to safely compute untrusted bytecode" 1722 ---help--- 1723 This kernel feature is useful for number crunching applications 1724 that may need to compute untrusted bytecode during their 1725 execution. By using pipes or other transports made available to 1726 the process as file descriptors supporting the read/write 1727 syscalls, it's possible to isolate those applications in 1728 their own address space using seccomp. Once seccomp is 1729 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1730 and the task is only allowed to execute a few safe syscalls 1731 defined by each seccomp mode. 1732 1733config PARAVIRT 1734 bool "Enable paravirtualization code" 1735 help 1736 This changes the kernel so it can modify itself when it is run 1737 under a hypervisor, potentially improving performance significantly 1738 over full virtualization. 1739 1740config PARAVIRT_TIME_ACCOUNTING 1741 bool "Paravirtual steal time accounting" 1742 select PARAVIRT 1743 help 1744 Select this option to enable fine granularity task steal time 1745 accounting. Time spent executing other tasks in parallel with 1746 the current vCPU is discounted from the vCPU power. To account for 1747 that, there can be a small performance impact. 1748 1749 If in doubt, say N here. 1750 1751config XEN_DOM0 1752 def_bool y 1753 depends on XEN 1754 1755config XEN 1756 bool "Xen guest support on ARM" 1757 depends on ARM && AEABI && OF 1758 depends on CPU_V7 && !CPU_V6 1759 depends on !GENERIC_ATOMIC64 1760 depends on MMU 1761 select ARCH_DMA_ADDR_T_64BIT 1762 select ARM_PSCI 1763 select SWIOTLB 1764 select SWIOTLB_XEN 1765 select PARAVIRT 1766 help 1767 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1768 1769config STACKPROTECTOR_PER_TASK 1770 bool "Use a unique stack canary value for each task" 1771 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1772 select GCC_PLUGIN_ARM_SSP_PER_TASK 1773 default y 1774 help 1775 Due to the fact that GCC uses an ordinary symbol reference from 1776 which to load the value of the stack canary, this value can only 1777 change at reboot time on SMP systems, and all tasks running in the 1778 kernel's address space are forced to use the same canary value for 1779 the entire duration that the system is up. 1780 1781 Enable this option to switch to a different method that uses a 1782 different canary value for each task. 1783 1784endmenu 1785 1786menu "Boot options" 1787 1788config USE_OF 1789 bool "Flattened Device Tree support" 1790 select IRQ_DOMAIN 1791 select OF 1792 help 1793 Include support for flattened device tree machine descriptions. 1794 1795config ATAGS 1796 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1797 default y 1798 help 1799 This is the traditional way of passing data to the kernel at boot 1800 time. If you are solely relying on the flattened device tree (or 1801 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1802 to remove ATAGS support from your kernel binary. If unsure, 1803 leave this to y. 1804 1805config DEPRECATED_PARAM_STRUCT 1806 bool "Provide old way to pass kernel parameters" 1807 depends on ATAGS 1808 help 1809 This was deprecated in 2001 and announced to live on for 5 years. 1810 Some old boot loaders still use this way. 1811 1812# Compressed boot loader in ROM. Yes, we really want to ask about 1813# TEXT and BSS so we preserve their values in the config files. 1814config ZBOOT_ROM_TEXT 1815 hex "Compressed ROM boot loader base address" 1816 default "0" 1817 help 1818 The physical address at which the ROM-able zImage is to be 1819 placed in the target. Platforms which normally make use of 1820 ROM-able zImage formats normally set this to a suitable 1821 value in their defconfig file. 1822 1823 If ZBOOT_ROM is not enabled, this has no effect. 1824 1825config ZBOOT_ROM_BSS 1826 hex "Compressed ROM boot loader BSS address" 1827 default "0" 1828 help 1829 The base address of an area of read/write memory in the target 1830 for the ROM-able zImage which must be available while the 1831 decompressor is running. It must be large enough to hold the 1832 entire decompressed kernel plus an additional 128 KiB. 1833 Platforms which normally make use of ROM-able zImage formats 1834 normally set this to a suitable value in their defconfig file. 1835 1836 If ZBOOT_ROM is not enabled, this has no effect. 1837 1838config ZBOOT_ROM 1839 bool "Compressed boot loader in ROM/flash" 1840 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1841 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1842 help 1843 Say Y here if you intend to execute your compressed kernel image 1844 (zImage) directly from ROM or flash. If unsure, say N. 1845 1846config ARM_APPENDED_DTB 1847 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1848 depends on OF 1849 help 1850 With this option, the boot code will look for a device tree binary 1851 (DTB) appended to zImage 1852 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1853 1854 This is meant as a backward compatibility convenience for those 1855 systems with a bootloader that can't be upgraded to accommodate 1856 the documented boot protocol using a device tree. 1857 1858 Beware that there is very little in terms of protection against 1859 this option being confused by leftover garbage in memory that might 1860 look like a DTB header after a reboot if no actual DTB is appended 1861 to zImage. Do not leave this option active in a production kernel 1862 if you don't intend to always append a DTB. Proper passing of the 1863 location into r2 of a bootloader provided DTB is always preferable 1864 to this option. 1865 1866config ARM_ATAG_DTB_COMPAT 1867 bool "Supplement the appended DTB with traditional ATAG information" 1868 depends on ARM_APPENDED_DTB 1869 help 1870 Some old bootloaders can't be updated to a DTB capable one, yet 1871 they provide ATAGs with memory configuration, the ramdisk address, 1872 the kernel cmdline string, etc. Such information is dynamically 1873 provided by the bootloader and can't always be stored in a static 1874 DTB. To allow a device tree enabled kernel to be used with such 1875 bootloaders, this option allows zImage to extract the information 1876 from the ATAG list and store it at run time into the appended DTB. 1877 1878choice 1879 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1880 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1881 1882config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1883 bool "Use bootloader kernel arguments if available" 1884 help 1885 Uses the command-line options passed by the boot loader instead of 1886 the device tree bootargs property. If the boot loader doesn't provide 1887 any, the device tree bootargs property will be used. 1888 1889config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1890 bool "Extend with bootloader kernel arguments" 1891 help 1892 The command-line arguments provided by the boot loader will be 1893 appended to the the device tree bootargs property. 1894 1895endchoice 1896 1897config CMDLINE 1898 string "Default kernel command string" 1899 default "" 1900 help 1901 On some architectures (EBSA110 and CATS), there is currently no way 1902 for the boot loader to pass arguments to the kernel. For these 1903 architectures, you should supply some command-line options at build 1904 time by entering them here. As a minimum, you should specify the 1905 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1906 1907choice 1908 prompt "Kernel command line type" if CMDLINE != "" 1909 default CMDLINE_FROM_BOOTLOADER 1910 depends on ATAGS 1911 1912config CMDLINE_FROM_BOOTLOADER 1913 bool "Use bootloader kernel arguments if available" 1914 help 1915 Uses the command-line options passed by the boot loader. If 1916 the boot loader doesn't provide any, the default kernel command 1917 string provided in CMDLINE will be used. 1918 1919config CMDLINE_EXTEND 1920 bool "Extend bootloader kernel arguments" 1921 help 1922 The command-line arguments provided by the boot loader will be 1923 appended to the default kernel command string. 1924 1925config CMDLINE_FORCE 1926 bool "Always use the default kernel command string" 1927 help 1928 Always use the default kernel command string, even if the boot 1929 loader passes other arguments to the kernel. 1930 This is useful if you cannot or don't want to change the 1931 command-line options your boot loader passes to the kernel. 1932endchoice 1933 1934config XIP_KERNEL 1935 bool "Kernel Execute-In-Place from ROM" 1936 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1937 help 1938 Execute-In-Place allows the kernel to run from non-volatile storage 1939 directly addressable by the CPU, such as NOR flash. This saves RAM 1940 space since the text section of the kernel is not loaded from flash 1941 to RAM. Read-write sections, such as the data section and stack, 1942 are still copied to RAM. The XIP kernel is not compressed since 1943 it has to run directly from flash, so it will take more space to 1944 store it. The flash address used to link the kernel object files, 1945 and for storing it, is configuration dependent. Therefore, if you 1946 say Y here, you must know the proper physical address where to 1947 store the kernel image depending on your own flash memory usage. 1948 1949 Also note that the make target becomes "make xipImage" rather than 1950 "make zImage" or "make Image". The final kernel binary to put in 1951 ROM memory will be arch/arm/boot/xipImage. 1952 1953 If unsure, say N. 1954 1955config XIP_PHYS_ADDR 1956 hex "XIP Kernel Physical Location" 1957 depends on XIP_KERNEL 1958 default "0x00080000" 1959 help 1960 This is the physical address in your flash memory the kernel will 1961 be linked for and stored to. This address is dependent on your 1962 own flash usage. 1963 1964config XIP_DEFLATED_DATA 1965 bool "Store kernel .data section compressed in ROM" 1966 depends on XIP_KERNEL 1967 select ZLIB_INFLATE 1968 help 1969 Before the kernel is actually executed, its .data section has to be 1970 copied to RAM from ROM. This option allows for storing that data 1971 in compressed form and decompressed to RAM rather than merely being 1972 copied, saving some precious ROM space. A possible drawback is a 1973 slightly longer boot delay. 1974 1975config KEXEC 1976 bool "Kexec system call (EXPERIMENTAL)" 1977 depends on (!SMP || PM_SLEEP_SMP) 1978 depends on !CPU_V7M 1979 select KEXEC_CORE 1980 help 1981 kexec is a system call that implements the ability to shutdown your 1982 current kernel, and to start another kernel. It is like a reboot 1983 but it is independent of the system firmware. And like a reboot 1984 you can start any kernel with it, not just Linux. 1985 1986 It is an ongoing process to be certain the hardware in a machine 1987 is properly shutdown, so do not be surprised if this code does not 1988 initially work for you. 1989 1990config ATAGS_PROC 1991 bool "Export atags in procfs" 1992 depends on ATAGS && KEXEC 1993 default y 1994 help 1995 Should the atags used to boot the kernel be exported in an "atags" 1996 file in procfs. Useful with kexec. 1997 1998config CRASH_DUMP 1999 bool "Build kdump crash kernel (EXPERIMENTAL)" 2000 help 2001 Generate crash dump after being started by kexec. This should 2002 be normally only set in special crash dump kernels which are 2003 loaded in the main kernel with kexec-tools into a specially 2004 reserved region and then later executed after a crash by 2005 kdump/kexec. The crash dump kernel must be compiled to a 2006 memory address not used by the main kernel 2007 2008 For more details see Documentation/kdump/kdump.txt 2009 2010config AUTO_ZRELADDR 2011 bool "Auto calculation of the decompressed kernel image address" 2012 help 2013 ZRELADDR is the physical address where the decompressed kernel 2014 image will be placed. If AUTO_ZRELADDR is selected, the address 2015 will be determined at run-time by masking the current IP with 2016 0xf8000000. This assumes the zImage being placed in the first 128MB 2017 from start of memory. 2018 2019config EFI_STUB 2020 bool 2021 2022config EFI 2023 bool "UEFI runtime support" 2024 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2025 select UCS2_STRING 2026 select EFI_PARAMS_FROM_FDT 2027 select EFI_STUB 2028 select EFI_ARMSTUB 2029 select EFI_RUNTIME_WRAPPERS 2030 ---help--- 2031 This option provides support for runtime services provided 2032 by UEFI firmware (such as non-volatile variables, realtime 2033 clock, and platform reset). A UEFI stub is also provided to 2034 allow the kernel to be booted as an EFI application. This 2035 is only useful for kernels that may run on systems that have 2036 UEFI firmware. 2037 2038config DMI 2039 bool "Enable support for SMBIOS (DMI) tables" 2040 depends on EFI 2041 default y 2042 help 2043 This enables SMBIOS/DMI feature for systems. 2044 2045 This option is only useful on systems that have UEFI firmware. 2046 However, even with this option, the resultant kernel should 2047 continue to boot on existing non-UEFI platforms. 2048 2049 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2050 i.e., the the practice of identifying the platform via DMI to 2051 decide whether certain workarounds for buggy hardware and/or 2052 firmware need to be enabled. This would require the DMI subsystem 2053 to be enabled much earlier than we do on ARM, which is non-trivial. 2054 2055endmenu 2056 2057menu "CPU Power Management" 2058 2059source "drivers/cpufreq/Kconfig" 2060 2061source "drivers/cpuidle/Kconfig" 2062 2063endmenu 2064 2065menu "Floating point emulation" 2066 2067comment "At least one emulation must be selected" 2068 2069config FPE_NWFPE 2070 bool "NWFPE math emulation" 2071 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2072 ---help--- 2073 Say Y to include the NWFPE floating point emulator in the kernel. 2074 This is necessary to run most binaries. Linux does not currently 2075 support floating point hardware so you need to say Y here even if 2076 your machine has an FPA or floating point co-processor podule. 2077 2078 You may say N here if you are going to load the Acorn FPEmulator 2079 early in the bootup. 2080 2081config FPE_NWFPE_XP 2082 bool "Support extended precision" 2083 depends on FPE_NWFPE 2084 help 2085 Say Y to include 80-bit support in the kernel floating-point 2086 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2087 Note that gcc does not generate 80-bit operations by default, 2088 so in most cases this option only enlarges the size of the 2089 floating point emulator without any good reason. 2090 2091 You almost surely want to say N here. 2092 2093config FPE_FASTFPE 2094 bool "FastFPE math emulation (EXPERIMENTAL)" 2095 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2096 ---help--- 2097 Say Y here to include the FAST floating point emulator in the kernel. 2098 This is an experimental much faster emulator which now also has full 2099 precision for the mantissa. It does not support any exceptions. 2100 It is very simple, and approximately 3-6 times faster than NWFPE. 2101 2102 It should be sufficient for most programs. It may be not suitable 2103 for scientific calculations, but you have to check this for yourself. 2104 If you do not feel you need a faster FP emulation you should better 2105 choose NWFPE. 2106 2107config VFP 2108 bool "VFP-format floating point maths" 2109 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2110 help 2111 Say Y to include VFP support code in the kernel. This is needed 2112 if your hardware includes a VFP unit. 2113 2114 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2115 release notes and additional status information. 2116 2117 Say N if your target does not have VFP hardware. 2118 2119config VFPv3 2120 bool 2121 depends on VFP 2122 default y if CPU_V7 2123 2124config NEON 2125 bool "Advanced SIMD (NEON) Extension support" 2126 depends on VFPv3 && CPU_V7 2127 help 2128 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2129 Extension. 2130 2131config KERNEL_MODE_NEON 2132 bool "Support for NEON in kernel mode" 2133 depends on NEON && AEABI 2134 help 2135 Say Y to include support for NEON in kernel mode. 2136 2137endmenu 2138 2139menu "Power management options" 2140 2141source "kernel/power/Kconfig" 2142 2143config ARCH_SUSPEND_POSSIBLE 2144 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2145 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2146 def_bool y 2147 2148config ARM_CPU_SUSPEND 2149 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2150 depends on ARCH_SUSPEND_POSSIBLE 2151 2152config ARCH_HIBERNATION_POSSIBLE 2153 bool 2154 depends on MMU 2155 default y if ARCH_SUSPEND_POSSIBLE 2156 2157endmenu 2158 2159source "drivers/firmware/Kconfig" 2160 2161if CRYPTO 2162source "arch/arm/crypto/Kconfig" 2163endif 2164 2165source "arch/arm/kvm/Kconfig" 2166