1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 23 select ARCH_HAS_SYNC_DMA_FOR_CPU 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 28 select ARCH_HAS_GCOV_PROFILE_ALL 29 select ARCH_KEEP_MEMBLOCK 30 select ARCH_MIGHT_HAVE_PC_PARPORT 31 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 32 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 33 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 34 select ARCH_SUPPORTS_ATOMIC_RMW 35 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 36 select ARCH_USE_BUILTIN_BSWAP 37 select ARCH_USE_CMPXCHG_LOCKREF 38 select ARCH_USE_MEMTEST 39 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 40 select ARCH_WANT_GENERAL_HUGETLB 41 select ARCH_WANT_IPC_PARSE_VERSION 42 select ARCH_WANT_LD_ORPHAN_WARN 43 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 44 select BUILDTIME_TABLE_SORT if MMU 45 select CLONE_BACKWARDS 46 select CPU_PM if SUSPEND || CPU_IDLE 47 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 48 select DMA_DECLARE_COHERENT 49 select DMA_GLOBAL_POOL if !MMU 50 select DMA_OPS 51 select DMA_NONCOHERENT_MMAP if MMU 52 select EDAC_SUPPORT 53 select EDAC_ATOMIC_SCRUB 54 select GENERIC_ALLOCATOR 55 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 56 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 57 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 58 select GENERIC_IRQ_IPI if SMP 59 select GENERIC_CPU_AUTOPROBE 60 select GENERIC_EARLY_IOREMAP 61 select GENERIC_IDLE_POLL_SETUP 62 select GENERIC_IRQ_MULTI_HANDLER 63 select GENERIC_IRQ_PROBE 64 select GENERIC_IRQ_SHOW 65 select GENERIC_IRQ_SHOW_LEVEL 66 select GENERIC_LIB_DEVMEM_IS_ALLOWED 67 select GENERIC_PCI_IOMAP 68 select GENERIC_SCHED_CLOCK 69 select GENERIC_SMP_IDLE_THREAD 70 select HARDIRQS_SW_RESEND 71 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 72 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 73 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 74 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 75 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 76 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 77 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 78 select HAVE_ARCH_MMAP_RND_BITS if MMU 79 select HAVE_ARCH_PFN_VALID 80 select HAVE_ARCH_SECCOMP 81 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 82 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 83 select HAVE_ARCH_TRACEHOOK 84 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 85 select HAVE_ARM_SMCCC if CPU_V7 86 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 87 select HAVE_CONTEXT_TRACKING_USER 88 select HAVE_C_RECORDMCOUNT 89 select HAVE_BUILDTIME_MCOUNT_SORT 90 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 91 select HAVE_DMA_CONTIGUOUS if MMU 92 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 93 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 94 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 95 select HAVE_EXIT_THREAD 96 select HAVE_FAST_GUP if ARM_LPAE 97 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 98 select HAVE_FUNCTION_GRAPH_TRACER 99 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 100 select HAVE_GCC_PLUGINS 101 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 102 select HAVE_IRQ_TIME_ACCOUNTING 103 select HAVE_KERNEL_GZIP 104 select HAVE_KERNEL_LZ4 105 select HAVE_KERNEL_LZMA 106 select HAVE_KERNEL_LZO 107 select HAVE_KERNEL_XZ 108 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 109 select HAVE_KRETPROBES if HAVE_KPROBES 110 select HAVE_MOD_ARCH_SPECIFIC 111 select HAVE_NMI 112 select HAVE_OPTPROBES if !THUMB2_KERNEL 113 select HAVE_PERF_EVENTS 114 select HAVE_PERF_REGS 115 select HAVE_PERF_USER_STACK_DUMP 116 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 117 select HAVE_REGS_AND_STACK_ACCESS_API 118 select HAVE_RSEQ 119 select HAVE_STACKPROTECTOR 120 select HAVE_SYSCALL_TRACEPOINTS 121 select HAVE_UID16 122 select HAVE_VIRT_CPU_ACCOUNTING_GEN 123 select IRQ_FORCED_THREADING 124 select MODULES_USE_ELF_REL 125 select NEED_DMA_MAP_STATE 126 select OF_EARLY_FLATTREE if OF 127 select OLD_SIGACTION 128 select OLD_SIGSUSPEND3 129 select PCI_SYSCALL if PCI 130 select PERF_USE_VMALLOC 131 select RTC_LIB 132 select SYS_SUPPORTS_APM_EMULATION 133 select THREAD_INFO_IN_TASK 134 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 135 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 136 # Above selects are sorted alphabetically; please add new ones 137 # according to that. Thanks. 138 help 139 The ARM series is a line of low-power-consumption RISC chip designs 140 licensed by ARM Ltd and targeted at embedded applications and 141 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 142 manufactured, but legacy ARM-based PC hardware remains popular in 143 Europe. There is an ARM Linux project with a web page at 144 <http://www.arm.linux.org.uk/>. 145 146config ARM_HAS_GROUP_RELOCS 147 def_bool y 148 depends on !LD_IS_LLD || LLD_VERSION >= 140000 149 depends on !COMPILE_TEST 150 help 151 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 152 relocations, which have been around for a long time, but were not 153 supported in LLD until version 14. The combined range is -/+ 256 MiB, 154 which is usually sufficient, but not for allyesconfig, so we disable 155 this feature when doing compile testing. 156 157config ARM_HAS_SG_CHAIN 158 bool 159 160config ARM_DMA_USE_IOMMU 161 bool 162 select ARM_HAS_SG_CHAIN 163 select NEED_SG_DMA_LENGTH 164 165if ARM_DMA_USE_IOMMU 166 167config ARM_DMA_IOMMU_ALIGNMENT 168 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 169 range 4 9 170 default 8 171 help 172 DMA mapping framework by default aligns all buffers to the smallest 173 PAGE_SIZE order which is greater than or equal to the requested buffer 174 size. This works well for buffers up to a few hundreds kilobytes, but 175 for larger buffers it just a waste of address space. Drivers which has 176 relatively small addressing window (like 64Mib) might run out of 177 virtual space with just a few allocations. 178 179 With this parameter you can specify the maximum PAGE_SIZE order for 180 DMA IOMMU buffers. Larger buffers will be aligned only to this 181 specified order. The order is expressed as a power of two multiplied 182 by the PAGE_SIZE. 183 184endif 185 186config SYS_SUPPORTS_APM_EMULATION 187 bool 188 189config HAVE_TCM 190 bool 191 select GENERIC_ALLOCATOR 192 193config HAVE_PROC_CPU 194 bool 195 196config NO_IOPORT_MAP 197 bool 198 199config SBUS 200 bool 201 202config STACKTRACE_SUPPORT 203 bool 204 default y 205 206config LOCKDEP_SUPPORT 207 bool 208 default y 209 210config ARCH_HAS_ILOG2_U32 211 bool 212 213config ARCH_HAS_ILOG2_U64 214 bool 215 216config ARCH_HAS_BANDGAP 217 bool 218 219config FIX_EARLYCON_MEM 220 def_bool y if MMU 221 222config GENERIC_HWEIGHT 223 bool 224 default y 225 226config GENERIC_CALIBRATE_DELAY 227 bool 228 default y 229 230config ARCH_MAY_HAVE_PC_FDC 231 bool 232 233config ARCH_SUPPORTS_UPROBES 234 def_bool y 235 236config GENERIC_ISA_DMA 237 bool 238 239config FIQ 240 bool 241 242config ARCH_MTD_XIP 243 bool 244 245config ARM_PATCH_PHYS_VIRT 246 bool "Patch physical to virtual translations at runtime" if EMBEDDED 247 default y 248 depends on !XIP_KERNEL && MMU 249 help 250 Patch phys-to-virt and virt-to-phys translation functions at 251 boot and module load time according to the position of the 252 kernel in system memory. 253 254 This can only be used with non-XIP MMU kernels where the base 255 of physical memory is at a 2 MiB boundary. 256 257 Only disable this option if you know that you do not require 258 this feature (eg, building a kernel for a single machine) and 259 you need to shrink the kernel to the minimal size. 260 261config NEED_MACH_IO_H 262 bool 263 help 264 Select this when mach/io.h is required to provide special 265 definitions for this platform. The need for mach/io.h should 266 be avoided when possible. 267 268config NEED_MACH_MEMORY_H 269 bool 270 help 271 Select this when mach/memory.h is required to provide special 272 definitions for this platform. The need for mach/memory.h should 273 be avoided when possible. 274 275config PHYS_OFFSET 276 hex "Physical address of main memory" if MMU 277 depends on !ARM_PATCH_PHYS_VIRT 278 default DRAM_BASE if !MMU 279 default 0x00000000 if ARCH_FOOTBRIDGE 280 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 281 default 0x30000000 if ARCH_S3C24XX 282 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 283 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 284 default 0 285 help 286 Please provide the physical address corresponding to the 287 location of main memory in your system. 288 289config GENERIC_BUG 290 def_bool y 291 depends on BUG 292 293config PGTABLE_LEVELS 294 int 295 default 3 if ARM_LPAE 296 default 2 297 298menu "System Type" 299 300config MMU 301 bool "MMU-based Paged Memory Management Support" 302 default y 303 help 304 Select if you want MMU-based virtualised addressing space 305 support by paged memory management. If unsure, say 'Y'. 306 307config ARM_SINGLE_ARMV7M 308 def_bool !MMU 309 select ARM_NVIC 310 select AUTO_ZRELADDR 311 select TIMER_OF 312 select COMMON_CLK 313 select CPU_V7M 314 select NO_IOPORT_MAP 315 select SPARSE_IRQ 316 select USE_OF 317 318config ARCH_MMAP_RND_BITS_MIN 319 default 8 320 321config ARCH_MMAP_RND_BITS_MAX 322 default 14 if PAGE_OFFSET=0x40000000 323 default 15 if PAGE_OFFSET=0x80000000 324 default 16 325 326# 327# The "ARM system type" choice list is ordered alphabetically by option 328# text. Please add new entries in the option alphabetic order. 329# 330choice 331 prompt "ARM system type" 332 depends on MMU 333 default ARCH_MULTIPLATFORM 334 335config ARCH_MULTIPLATFORM 336 bool "Allow multiple platforms to be selected" 337 select ARCH_FLATMEM_ENABLE 338 select ARCH_SPARSEMEM_ENABLE 339 select ARCH_SELECT_MEMORY_MODEL 340 select ARM_HAS_SG_CHAIN 341 select ARM_PATCH_PHYS_VIRT 342 select AUTO_ZRELADDR 343 select TIMER_OF 344 select COMMON_CLK 345 select HAVE_PCI 346 select PCI_DOMAINS_GENERIC if PCI 347 select SPARSE_IRQ 348 select USE_OF 349 350config ARCH_FOOTBRIDGE 351 bool "FootBridge" 352 depends on CPU_LITTLE_ENDIAN 353 depends on ATAGS 354 select CPU_SA110 355 select FOOTBRIDGE 356 select NEED_MACH_MEMORY_H 357 help 358 Support for systems based on the DC21285 companion chip 359 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 360 361config ARCH_RPC 362 bool "RiscPC" 363 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 364 depends on CPU_LITTLE_ENDIAN 365 depends on ATAGS 366 select ARCH_ACORN 367 select ARCH_MAY_HAVE_PC_FDC 368 select ARCH_SPARSEMEM_ENABLE 369 select ARM_HAS_SG_CHAIN 370 select CPU_SA110 371 select FIQ 372 select HAVE_PATA_PLATFORM 373 select ISA_DMA_API 374 select LEGACY_TIMER_TICK 375 select NEED_MACH_IO_H 376 select NEED_MACH_MEMORY_H 377 select NO_IOPORT_MAP 378 help 379 On the Acorn Risc-PC, Linux can support the internal IDE disk and 380 CD-ROM interface, serial and parallel port, and the floppy drive. 381 382config ARCH_SA1100 383 bool "SA1100-based" 384 depends on CPU_LITTLE_ENDIAN 385 depends on ATAGS 386 select ARCH_MTD_XIP 387 select ARCH_SPARSEMEM_ENABLE 388 select CLKSRC_MMIO 389 select CLKSRC_PXA 390 select TIMER_OF if OF 391 select COMMON_CLK 392 select CPU_FREQ 393 select CPU_SA1100 394 select GPIOLIB 395 select IRQ_DOMAIN 396 select ISA 397 select NEED_MACH_MEMORY_H 398 select SPARSE_IRQ 399 help 400 Support for StrongARM 11x0 based boards. 401 402endchoice 403 404menu "Multiple platform selection" 405 depends on ARCH_MULTIPLATFORM 406 407comment "CPU Core family selection" 408 409config ARCH_MULTI_V4 410 bool "ARMv4 based platforms (FA526)" 411 depends on !ARCH_MULTI_V6_V7 412 select ARCH_MULTI_V4_V5 413 select CPU_FA526 414 415config ARCH_MULTI_V4T 416 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 417 depends on !ARCH_MULTI_V6_V7 418 select ARCH_MULTI_V4_V5 419 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 420 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 421 CPU_ARM925T || CPU_ARM940T) 422 423config ARCH_MULTI_V5 424 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 425 depends on !ARCH_MULTI_V6_V7 426 select ARCH_MULTI_V4_V5 427 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 428 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 429 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 430 431config ARCH_MULTI_V4_V5 432 bool 433 434config ARCH_MULTI_V6 435 bool "ARMv6 based platforms (ARM11)" 436 select ARCH_MULTI_V6_V7 437 select CPU_V6K 438 439config ARCH_MULTI_V7 440 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 441 default y 442 select ARCH_MULTI_V6_V7 443 select CPU_V7 444 select HAVE_SMP 445 446config ARCH_MULTI_V6_V7 447 bool 448 select MIGHT_HAVE_CACHE_L2X0 449 450config ARCH_MULTI_CPU_AUTO 451 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 452 select ARCH_MULTI_V5 453 454endmenu 455 456config ARCH_VIRT 457 bool "Dummy Virtual Machine" 458 depends on ARCH_MULTI_V7 459 select ARM_AMBA 460 select ARM_GIC 461 select ARM_GIC_V2M if PCI 462 select ARM_GIC_V3 463 select ARM_GIC_V3_ITS if PCI 464 select ARM_PSCI 465 select HAVE_ARM_ARCH_TIMER 466 467config ARCH_AIROHA 468 bool "Airoha SoC Support" 469 depends on ARCH_MULTI_V7 470 select ARM_AMBA 471 select ARM_GIC 472 select ARM_GIC_V3 473 select ARM_PSCI 474 select HAVE_ARM_ARCH_TIMER 475 select COMMON_CLK 476 help 477 Support for Airoha EN7523 SoCs 478 479# 480# This is sorted alphabetically by mach-* pathname. However, plat-* 481# Kconfigs may be included either alphabetically (according to the 482# plat- suffix) or along side the corresponding mach-* source. 483# 484source "arch/arm/mach-actions/Kconfig" 485 486source "arch/arm/mach-alpine/Kconfig" 487 488source "arch/arm/mach-artpec/Kconfig" 489 490source "arch/arm/mach-asm9260/Kconfig" 491 492source "arch/arm/mach-aspeed/Kconfig" 493 494source "arch/arm/mach-at91/Kconfig" 495 496source "arch/arm/mach-axxia/Kconfig" 497 498source "arch/arm/mach-bcm/Kconfig" 499 500source "arch/arm/mach-berlin/Kconfig" 501 502source "arch/arm/mach-clps711x/Kconfig" 503 504source "arch/arm/mach-cns3xxx/Kconfig" 505 506source "arch/arm/mach-davinci/Kconfig" 507 508source "arch/arm/mach-digicolor/Kconfig" 509 510source "arch/arm/mach-dove/Kconfig" 511 512source "arch/arm/mach-ep93xx/Kconfig" 513 514source "arch/arm/mach-exynos/Kconfig" 515 516source "arch/arm/mach-footbridge/Kconfig" 517 518source "arch/arm/mach-gemini/Kconfig" 519 520source "arch/arm/mach-highbank/Kconfig" 521 522source "arch/arm/mach-hisi/Kconfig" 523 524source "arch/arm/mach-hpe/Kconfig" 525 526source "arch/arm/mach-imx/Kconfig" 527 528source "arch/arm/mach-iop32x/Kconfig" 529 530source "arch/arm/mach-ixp4xx/Kconfig" 531 532source "arch/arm/mach-keystone/Kconfig" 533 534source "arch/arm/mach-lpc32xx/Kconfig" 535 536source "arch/arm/mach-mediatek/Kconfig" 537 538source "arch/arm/mach-meson/Kconfig" 539 540source "arch/arm/mach-milbeaut/Kconfig" 541 542source "arch/arm/mach-mmp/Kconfig" 543 544source "arch/arm/mach-moxart/Kconfig" 545 546source "arch/arm/mach-mstar/Kconfig" 547 548source "arch/arm/mach-mv78xx0/Kconfig" 549 550source "arch/arm/mach-mvebu/Kconfig" 551 552source "arch/arm/mach-mxs/Kconfig" 553 554source "arch/arm/mach-nomadik/Kconfig" 555 556source "arch/arm/mach-npcm/Kconfig" 557 558source "arch/arm/mach-nspire/Kconfig" 559 560source "arch/arm/mach-omap1/Kconfig" 561 562source "arch/arm/mach-omap2/Kconfig" 563 564source "arch/arm/mach-orion5x/Kconfig" 565 566source "arch/arm/mach-oxnas/Kconfig" 567 568source "arch/arm/mach-pxa/Kconfig" 569 570source "arch/arm/mach-qcom/Kconfig" 571 572source "arch/arm/mach-rda/Kconfig" 573 574source "arch/arm/mach-realtek/Kconfig" 575 576source "arch/arm/mach-rockchip/Kconfig" 577 578source "arch/arm/mach-s3c/Kconfig" 579 580source "arch/arm/mach-s5pv210/Kconfig" 581 582source "arch/arm/mach-sa1100/Kconfig" 583 584source "arch/arm/mach-shmobile/Kconfig" 585 586source "arch/arm/mach-socfpga/Kconfig" 587 588source "arch/arm/mach-spear/Kconfig" 589 590source "arch/arm/mach-sti/Kconfig" 591 592source "arch/arm/mach-stm32/Kconfig" 593 594source "arch/arm/mach-sunplus/Kconfig" 595 596source "arch/arm/mach-sunxi/Kconfig" 597 598source "arch/arm/mach-tegra/Kconfig" 599 600source "arch/arm/mach-uniphier/Kconfig" 601 602source "arch/arm/mach-ux500/Kconfig" 603 604source "arch/arm/mach-versatile/Kconfig" 605 606source "arch/arm/mach-vt8500/Kconfig" 607 608source "arch/arm/mach-zynq/Kconfig" 609 610# ARMv7-M architecture 611config ARCH_LPC18XX 612 bool "NXP LPC18xx/LPC43xx" 613 depends on ARM_SINGLE_ARMV7M 614 select ARCH_HAS_RESET_CONTROLLER 615 select ARM_AMBA 616 select CLKSRC_LPC32XX 617 select PINCTRL 618 help 619 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 620 high performance microcontrollers. 621 622config ARCH_MPS2 623 bool "ARM MPS2 platform" 624 depends on ARM_SINGLE_ARMV7M 625 select ARM_AMBA 626 select CLKSRC_MPS2 627 help 628 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 629 with a range of available cores like Cortex-M3/M4/M7. 630 631 Please, note that depends which Application Note is used memory map 632 for the platform may vary, so adjustment of RAM base might be needed. 633 634# Definitions to make life easier 635config ARCH_ACORN 636 bool 637 638config PLAT_ORION 639 bool 640 select CLKSRC_MMIO 641 select COMMON_CLK 642 select GENERIC_IRQ_CHIP 643 select IRQ_DOMAIN 644 645config PLAT_ORION_LEGACY 646 bool 647 select PLAT_ORION 648 649config PLAT_VERSATILE 650 bool 651 652source "arch/arm/mm/Kconfig" 653 654config IWMMXT 655 bool "Enable iWMMXt support" 656 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 657 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 658 help 659 Enable support for iWMMXt context switching at run time if 660 running on a CPU that supports it. 661 662if !MMU 663source "arch/arm/Kconfig-nommu" 664endif 665 666config PJ4B_ERRATA_4742 667 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 668 depends on CPU_PJ4B && MACH_ARMADA_370 669 default y 670 help 671 When coming out of either a Wait for Interrupt (WFI) or a Wait for 672 Event (WFE) IDLE states, a specific timing sensitivity exists between 673 the retiring WFI/WFE instructions and the newly issued subsequent 674 instructions. This sensitivity can result in a CPU hang scenario. 675 Workaround: 676 The software must insert either a Data Synchronization Barrier (DSB) 677 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 678 instruction 679 680config ARM_ERRATA_326103 681 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 682 depends on CPU_V6 683 help 684 Executing a SWP instruction to read-only memory does not set bit 11 685 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 686 treat the access as a read, preventing a COW from occurring and 687 causing the faulting task to livelock. 688 689config ARM_ERRATA_411920 690 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 691 depends on CPU_V6 || CPU_V6K 692 help 693 Invalidation of the Instruction Cache operation can 694 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 695 It does not affect the MPCore. This option enables the ARM Ltd. 696 recommended workaround. 697 698config ARM_ERRATA_430973 699 bool "ARM errata: Stale prediction on replaced interworking branch" 700 depends on CPU_V7 701 help 702 This option enables the workaround for the 430973 Cortex-A8 703 r1p* erratum. If a code sequence containing an ARM/Thumb 704 interworking branch is replaced with another code sequence at the 705 same virtual address, whether due to self-modifying code or virtual 706 to physical address re-mapping, Cortex-A8 does not recover from the 707 stale interworking branch prediction. This results in Cortex-A8 708 executing the new code sequence in the incorrect ARM or Thumb state. 709 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 710 and also flushes the branch target cache at every context switch. 711 Note that setting specific bits in the ACTLR register may not be 712 available in non-secure mode. 713 714config ARM_ERRATA_458693 715 bool "ARM errata: Processor deadlock when a false hazard is created" 716 depends on CPU_V7 717 depends on !ARCH_MULTIPLATFORM 718 help 719 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 720 erratum. For very specific sequences of memory operations, it is 721 possible for a hazard condition intended for a cache line to instead 722 be incorrectly associated with a different cache line. This false 723 hazard might then cause a processor deadlock. The workaround enables 724 the L1 caching of the NEON accesses and disables the PLD instruction 725 in the ACTLR register. Note that setting specific bits in the ACTLR 726 register may not be available in non-secure mode. 727 728config ARM_ERRATA_460075 729 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 730 depends on CPU_V7 731 depends on !ARCH_MULTIPLATFORM 732 help 733 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 734 erratum. Any asynchronous access to the L2 cache may encounter a 735 situation in which recent store transactions to the L2 cache are lost 736 and overwritten with stale memory contents from external memory. The 737 workaround disables the write-allocate mode for the L2 cache via the 738 ACTLR register. Note that setting specific bits in the ACTLR register 739 may not be available in non-secure mode. 740 741config ARM_ERRATA_742230 742 bool "ARM errata: DMB operation may be faulty" 743 depends on CPU_V7 && SMP 744 depends on !ARCH_MULTIPLATFORM 745 help 746 This option enables the workaround for the 742230 Cortex-A9 747 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 748 between two write operations may not ensure the correct visibility 749 ordering of the two writes. This workaround sets a specific bit in 750 the diagnostic register of the Cortex-A9 which causes the DMB 751 instruction to behave as a DSB, ensuring the correct behaviour of 752 the two writes. 753 754config ARM_ERRATA_742231 755 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 756 depends on CPU_V7 && SMP 757 depends on !ARCH_MULTIPLATFORM 758 help 759 This option enables the workaround for the 742231 Cortex-A9 760 (r2p0..r2p2) erratum. Under certain conditions, specific to the 761 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 762 accessing some data located in the same cache line, may get corrupted 763 data due to bad handling of the address hazard when the line gets 764 replaced from one of the CPUs at the same time as another CPU is 765 accessing it. This workaround sets specific bits in the diagnostic 766 register of the Cortex-A9 which reduces the linefill issuing 767 capabilities of the processor. 768 769config ARM_ERRATA_643719 770 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 771 depends on CPU_V7 && SMP 772 default y 773 help 774 This option enables the workaround for the 643719 Cortex-A9 (prior to 775 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 776 register returns zero when it should return one. The workaround 777 corrects this value, ensuring cache maintenance operations which use 778 it behave as intended and avoiding data corruption. 779 780config ARM_ERRATA_720789 781 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 782 depends on CPU_V7 783 help 784 This option enables the workaround for the 720789 Cortex-A9 (prior to 785 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 786 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 787 As a consequence of this erratum, some TLB entries which should be 788 invalidated are not, resulting in an incoherency in the system page 789 tables. The workaround changes the TLB flushing routines to invalidate 790 entries regardless of the ASID. 791 792config ARM_ERRATA_743622 793 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 794 depends on CPU_V7 795 depends on !ARCH_MULTIPLATFORM 796 help 797 This option enables the workaround for the 743622 Cortex-A9 798 (r2p*) erratum. Under very rare conditions, a faulty 799 optimisation in the Cortex-A9 Store Buffer may lead to data 800 corruption. This workaround sets a specific bit in the diagnostic 801 register of the Cortex-A9 which disables the Store Buffer 802 optimisation, preventing the defect from occurring. This has no 803 visible impact on the overall performance or power consumption of the 804 processor. 805 806config ARM_ERRATA_751472 807 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 808 depends on CPU_V7 809 depends on !ARCH_MULTIPLATFORM 810 help 811 This option enables the workaround for the 751472 Cortex-A9 (prior 812 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 813 completion of a following broadcasted operation if the second 814 operation is received by a CPU before the ICIALLUIS has completed, 815 potentially leading to corrupted entries in the cache or TLB. 816 817config ARM_ERRATA_754322 818 bool "ARM errata: possible faulty MMU translations following an ASID switch" 819 depends on CPU_V7 820 help 821 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 822 r3p*) erratum. A speculative memory access may cause a page table walk 823 which starts prior to an ASID switch but completes afterwards. This 824 can populate the micro-TLB with a stale entry which may be hit with 825 the new ASID. This workaround places two dsb instructions in the mm 826 switching code so that no page table walks can cross the ASID switch. 827 828config ARM_ERRATA_754327 829 bool "ARM errata: no automatic Store Buffer drain" 830 depends on CPU_V7 && SMP 831 help 832 This option enables the workaround for the 754327 Cortex-A9 (prior to 833 r2p0) erratum. The Store Buffer does not have any automatic draining 834 mechanism and therefore a livelock may occur if an external agent 835 continuously polls a memory location waiting to observe an update. 836 This workaround defines cpu_relax() as smp_mb(), preventing correctly 837 written polling loops from denying visibility of updates to memory. 838 839config ARM_ERRATA_364296 840 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 841 depends on CPU_V6 842 help 843 This options enables the workaround for the 364296 ARM1136 844 r0p2 erratum (possible cache data corruption with 845 hit-under-miss enabled). It sets the undocumented bit 31 in 846 the auxiliary control register and the FI bit in the control 847 register, thus disabling hit-under-miss without putting the 848 processor into full low interrupt latency mode. ARM11MPCore 849 is not affected. 850 851config ARM_ERRATA_764369 852 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 853 depends on CPU_V7 && SMP 854 help 855 This option enables the workaround for erratum 764369 856 affecting Cortex-A9 MPCore with two or more processors (all 857 current revisions). Under certain timing circumstances, a data 858 cache line maintenance operation by MVA targeting an Inner 859 Shareable memory region may fail to proceed up to either the 860 Point of Coherency or to the Point of Unification of the 861 system. This workaround adds a DSB instruction before the 862 relevant cache maintenance functions and sets a specific bit 863 in the diagnostic control register of the SCU. 864 865config ARM_ERRATA_764319 866 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 867 depends on CPU_V7 868 help 869 This option enables the workaround for the 764319 Cortex A-9 erratum. 870 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 871 unexpected Undefined Instruction exception when the DBGSWENABLE 872 external pin is set to 0, even when the CP14 accesses are performed 873 from a privileged mode. This work around catches the exception in a 874 way the kernel does not stop execution. 875 876config ARM_ERRATA_775420 877 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 878 depends on CPU_V7 879 help 880 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 881 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 882 operation aborts with MMU exception, it might cause the processor 883 to deadlock. This workaround puts DSB before executing ISB if 884 an abort may occur on cache maintenance. 885 886config ARM_ERRATA_798181 887 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 888 depends on CPU_V7 && SMP 889 help 890 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 891 adequately shooting down all use of the old entries. This 892 option enables the Linux kernel workaround for this erratum 893 which sends an IPI to the CPUs that are running the same ASID 894 as the one being invalidated. 895 896config ARM_ERRATA_773022 897 bool "ARM errata: incorrect instructions may be executed from loop buffer" 898 depends on CPU_V7 899 help 900 This option enables the workaround for the 773022 Cortex-A15 901 (up to r0p4) erratum. In certain rare sequences of code, the 902 loop buffer may deliver incorrect instructions. This 903 workaround disables the loop buffer to avoid the erratum. 904 905config ARM_ERRATA_818325_852422 906 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 907 depends on CPU_V7 908 help 909 This option enables the workaround for: 910 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 911 instruction might deadlock. Fixed in r0p1. 912 - Cortex-A12 852422: Execution of a sequence of instructions might 913 lead to either a data corruption or a CPU deadlock. Not fixed in 914 any Cortex-A12 cores yet. 915 This workaround for all both errata involves setting bit[12] of the 916 Feature Register. This bit disables an optimisation applied to a 917 sequence of 2 instructions that use opposing condition codes. 918 919config ARM_ERRATA_821420 920 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 921 depends on CPU_V7 922 help 923 This option enables the workaround for the 821420 Cortex-A12 924 (all revs) erratum. In very rare timing conditions, a sequence 925 of VMOV to Core registers instructions, for which the second 926 one is in the shadow of a branch or abort, can lead to a 927 deadlock when the VMOV instructions are issued out-of-order. 928 929config ARM_ERRATA_825619 930 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 931 depends on CPU_V7 932 help 933 This option enables the workaround for the 825619 Cortex-A12 934 (all revs) erratum. Within rare timing constraints, executing a 935 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 936 and Device/Strongly-Ordered loads and stores might cause deadlock 937 938config ARM_ERRATA_857271 939 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 940 depends on CPU_V7 941 help 942 This option enables the workaround for the 857271 Cortex-A12 943 (all revs) erratum. Under very rare timing conditions, the CPU might 944 hang. The workaround is expected to have a < 1% performance impact. 945 946config ARM_ERRATA_852421 947 bool "ARM errata: A17: DMB ST might fail to create order between stores" 948 depends on CPU_V7 949 help 950 This option enables the workaround for the 852421 Cortex-A17 951 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 952 execution of a DMB ST instruction might fail to properly order 953 stores from GroupA and stores from GroupB. 954 955config ARM_ERRATA_852423 956 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 957 depends on CPU_V7 958 help 959 This option enables the workaround for: 960 - Cortex-A17 852423: Execution of a sequence of instructions might 961 lead to either a data corruption or a CPU deadlock. Not fixed in 962 any Cortex-A17 cores yet. 963 This is identical to Cortex-A12 erratum 852422. It is a separate 964 config option from the A12 erratum due to the way errata are checked 965 for and handled. 966 967config ARM_ERRATA_857272 968 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 969 depends on CPU_V7 970 help 971 This option enables the workaround for the 857272 Cortex-A17 erratum. 972 This erratum is not known to be fixed in any A17 revision. 973 This is identical to Cortex-A12 erratum 857271. It is a separate 974 config option from the A12 erratum due to the way errata are checked 975 for and handled. 976 977endmenu 978 979source "arch/arm/common/Kconfig" 980 981menu "Bus support" 982 983config ISA 984 bool 985 help 986 Find out whether you have ISA slots on your motherboard. ISA is the 987 name of a bus system, i.e. the way the CPU talks to the other stuff 988 inside your box. Other bus systems are PCI, EISA, MicroChannel 989 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 990 newer boards don't support it. If you have ISA, say Y, otherwise N. 991 992# Select ISA DMA controller support 993config ISA_DMA 994 bool 995 select ISA_DMA_API 996 997# Select ISA DMA interface 998config ISA_DMA_API 999 bool 1000 1001config PCI_NANOENGINE 1002 bool "BSE nanoEngine PCI support" 1003 depends on SA1100_NANOENGINE 1004 help 1005 Enable PCI on the BSE nanoEngine board. 1006 1007config ARM_ERRATA_814220 1008 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1009 depends on CPU_V7 1010 help 1011 The v7 ARM states that all cache and branch predictor maintenance 1012 operations that do not specify an address execute, relative to 1013 each other, in program order. 1014 However, because of this erratum, an L2 set/way cache maintenance 1015 operation can overtake an L1 set/way cache maintenance operation. 1016 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1017 r0p4, r0p5. 1018 1019endmenu 1020 1021menu "Kernel Features" 1022 1023config HAVE_SMP 1024 bool 1025 help 1026 This option should be selected by machines which have an SMP- 1027 capable CPU. 1028 1029 The only effect of this option is to make the SMP-related 1030 options available to the user for configuration. 1031 1032config SMP 1033 bool "Symmetric Multi-Processing" 1034 depends on CPU_V6K || CPU_V7 1035 depends on HAVE_SMP 1036 depends on MMU || ARM_MPU 1037 select IRQ_WORK 1038 help 1039 This enables support for systems with more than one CPU. If you have 1040 a system with only one CPU, say N. If you have a system with more 1041 than one CPU, say Y. 1042 1043 If you say N here, the kernel will run on uni- and multiprocessor 1044 machines, but will use only one CPU of a multiprocessor machine. If 1045 you say Y here, the kernel will run on many, but not all, 1046 uniprocessor machines. On a uniprocessor machine, the kernel 1047 will run faster if you say N here. 1048 1049 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1050 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1051 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1052 1053 If you don't know what to do here, say N. 1054 1055config SMP_ON_UP 1056 bool "Allow booting SMP kernel on uniprocessor systems" 1057 depends on SMP && !XIP_KERNEL && MMU 1058 default y 1059 help 1060 SMP kernels contain instructions which fail on non-SMP processors. 1061 Enabling this option allows the kernel to modify itself to make 1062 these instructions safe. Disabling it allows about 1K of space 1063 savings. 1064 1065 If you don't know what to do here, say Y. 1066 1067 1068config CURRENT_POINTER_IN_TPIDRURO 1069 def_bool y 1070 depends on CPU_32v6K && !CPU_V6 1071 1072config IRQSTACKS 1073 def_bool y 1074 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1075 select HAVE_SOFTIRQ_ON_OWN_STACK 1076 1077config ARM_CPU_TOPOLOGY 1078 bool "Support cpu topology definition" 1079 depends on SMP && CPU_V7 1080 default y 1081 help 1082 Support ARM cpu topology definition. The MPIDR register defines 1083 affinity between processors which is then used to describe the cpu 1084 topology of an ARM System. 1085 1086config SCHED_MC 1087 bool "Multi-core scheduler support" 1088 depends on ARM_CPU_TOPOLOGY 1089 help 1090 Multi-core scheduler support improves the CPU scheduler's decision 1091 making when dealing with multi-core CPU chips at a cost of slightly 1092 increased overhead in some places. If unsure say N here. 1093 1094config SCHED_SMT 1095 bool "SMT scheduler support" 1096 depends on ARM_CPU_TOPOLOGY 1097 help 1098 Improves the CPU scheduler's decision making when dealing with 1099 MultiThreading at a cost of slightly increased overhead in some 1100 places. If unsure say N here. 1101 1102config HAVE_ARM_SCU 1103 bool 1104 help 1105 This option enables support for the ARM snoop control unit 1106 1107config HAVE_ARM_ARCH_TIMER 1108 bool "Architected timer support" 1109 depends on CPU_V7 1110 select ARM_ARCH_TIMER 1111 help 1112 This option enables support for the ARM architected timer 1113 1114config HAVE_ARM_TWD 1115 bool 1116 help 1117 This options enables support for the ARM timer and watchdog unit 1118 1119config MCPM 1120 bool "Multi-Cluster Power Management" 1121 depends on CPU_V7 && SMP 1122 help 1123 This option provides the common power management infrastructure 1124 for (multi-)cluster based systems, such as big.LITTLE based 1125 systems. 1126 1127config MCPM_QUAD_CLUSTER 1128 bool 1129 depends on MCPM 1130 help 1131 To avoid wasting resources unnecessarily, MCPM only supports up 1132 to 2 clusters by default. 1133 Platforms with 3 or 4 clusters that use MCPM must select this 1134 option to allow the additional clusters to be managed. 1135 1136config BIG_LITTLE 1137 bool "big.LITTLE support (Experimental)" 1138 depends on CPU_V7 && SMP 1139 select MCPM 1140 help 1141 This option enables support selections for the big.LITTLE 1142 system architecture. 1143 1144config BL_SWITCHER 1145 bool "big.LITTLE switcher support" 1146 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1147 select CPU_PM 1148 help 1149 The big.LITTLE "switcher" provides the core functionality to 1150 transparently handle transition between a cluster of A15's 1151 and a cluster of A7's in a big.LITTLE system. 1152 1153config BL_SWITCHER_DUMMY_IF 1154 tristate "Simple big.LITTLE switcher user interface" 1155 depends on BL_SWITCHER && DEBUG_KERNEL 1156 help 1157 This is a simple and dummy char dev interface to control 1158 the big.LITTLE switcher core code. It is meant for 1159 debugging purposes only. 1160 1161choice 1162 prompt "Memory split" 1163 depends on MMU 1164 default VMSPLIT_3G 1165 help 1166 Select the desired split between kernel and user memory. 1167 1168 If you are not absolutely sure what you are doing, leave this 1169 option alone! 1170 1171 config VMSPLIT_3G 1172 bool "3G/1G user/kernel split" 1173 config VMSPLIT_3G_OPT 1174 depends on !ARM_LPAE 1175 bool "3G/1G user/kernel split (for full 1G low memory)" 1176 config VMSPLIT_2G 1177 bool "2G/2G user/kernel split" 1178 config VMSPLIT_1G 1179 bool "1G/3G user/kernel split" 1180endchoice 1181 1182config PAGE_OFFSET 1183 hex 1184 default PHYS_OFFSET if !MMU 1185 default 0x40000000 if VMSPLIT_1G 1186 default 0x80000000 if VMSPLIT_2G 1187 default 0xB0000000 if VMSPLIT_3G_OPT 1188 default 0xC0000000 1189 1190config KASAN_SHADOW_OFFSET 1191 hex 1192 depends on KASAN 1193 default 0x1f000000 if PAGE_OFFSET=0x40000000 1194 default 0x5f000000 if PAGE_OFFSET=0x80000000 1195 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1196 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1197 default 0xffffffff 1198 1199config NR_CPUS 1200 int "Maximum number of CPUs (2-32)" 1201 range 2 16 if DEBUG_KMAP_LOCAL 1202 range 2 32 if !DEBUG_KMAP_LOCAL 1203 depends on SMP 1204 default "4" 1205 help 1206 The maximum number of CPUs that the kernel can support. 1207 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1208 debugging is enabled, which uses half of the per-CPU fixmap 1209 slots as guard regions. 1210 1211config HOTPLUG_CPU 1212 bool "Support for hot-pluggable CPUs" 1213 depends on SMP 1214 select GENERIC_IRQ_MIGRATION 1215 help 1216 Say Y here to experiment with turning CPUs off and on. CPUs 1217 can be controlled through /sys/devices/system/cpu. 1218 1219config ARM_PSCI 1220 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1221 depends on HAVE_ARM_SMCCC 1222 select ARM_PSCI_FW 1223 help 1224 Say Y here if you want Linux to communicate with system firmware 1225 implementing the PSCI specification for CPU-centric power 1226 management operations described in ARM document number ARM DEN 1227 0022A ("Power State Coordination Interface System Software on 1228 ARM processors"). 1229 1230# The GPIO number here must be sorted by descending number. In case of 1231# a multiplatform kernel, we just want the highest value required by the 1232# selected platforms. 1233config ARCH_NR_GPIO 1234 int 1235 default 2048 if ARCH_INTEL_SOCFPGA 1236 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1237 ARCH_ZYNQ || ARCH_ASPEED 1238 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1239 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1240 default 416 if ARCH_SUNXI 1241 default 392 if ARCH_U8500 1242 default 352 if ARCH_VT8500 1243 default 288 if ARCH_ROCKCHIP 1244 default 264 if MACH_H4700 1245 default 0 1246 help 1247 Maximum number of GPIOs in the system. 1248 1249 If unsure, leave the default value. 1250 1251config HZ_FIXED 1252 int 1253 default 128 if SOC_AT91RM9200 1254 default 0 1255 1256choice 1257 depends on HZ_FIXED = 0 1258 prompt "Timer frequency" 1259 1260config HZ_100 1261 bool "100 Hz" 1262 1263config HZ_200 1264 bool "200 Hz" 1265 1266config HZ_250 1267 bool "250 Hz" 1268 1269config HZ_300 1270 bool "300 Hz" 1271 1272config HZ_500 1273 bool "500 Hz" 1274 1275config HZ_1000 1276 bool "1000 Hz" 1277 1278endchoice 1279 1280config HZ 1281 int 1282 default HZ_FIXED if HZ_FIXED != 0 1283 default 100 if HZ_100 1284 default 200 if HZ_200 1285 default 250 if HZ_250 1286 default 300 if HZ_300 1287 default 500 if HZ_500 1288 default 1000 1289 1290config SCHED_HRTICK 1291 def_bool HIGH_RES_TIMERS 1292 1293config THUMB2_KERNEL 1294 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1295 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1296 default y if CPU_THUMBONLY 1297 select ARM_UNWIND 1298 help 1299 By enabling this option, the kernel will be compiled in 1300 Thumb-2 mode. 1301 1302 If unsure, say N. 1303 1304config ARM_PATCH_IDIV 1305 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1306 depends on CPU_32v7 && !XIP_KERNEL 1307 default y 1308 help 1309 The ARM compiler inserts calls to __aeabi_idiv() and 1310 __aeabi_uidiv() when it needs to perform division on signed 1311 and unsigned integers. Some v7 CPUs have support for the sdiv 1312 and udiv instructions that can be used to implement those 1313 functions. 1314 1315 Enabling this option allows the kernel to modify itself to 1316 replace the first two instructions of these library functions 1317 with the sdiv or udiv plus "bx lr" instructions when the CPU 1318 it is running on supports them. Typically this will be faster 1319 and less power intensive than running the original library 1320 code to do integer division. 1321 1322config AEABI 1323 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1324 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1325 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1326 help 1327 This option allows for the kernel to be compiled using the latest 1328 ARM ABI (aka EABI). This is only useful if you are using a user 1329 space environment that is also compiled with EABI. 1330 1331 Since there are major incompatibilities between the legacy ABI and 1332 EABI, especially with regard to structure member alignment, this 1333 option also changes the kernel syscall calling convention to 1334 disambiguate both ABIs and allow for backward compatibility support 1335 (selected with CONFIG_OABI_COMPAT). 1336 1337 To use this you need GCC version 4.0.0 or later. 1338 1339config OABI_COMPAT 1340 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1341 depends on AEABI && !THUMB2_KERNEL 1342 help 1343 This option preserves the old syscall interface along with the 1344 new (ARM EABI) one. It also provides a compatibility layer to 1345 intercept syscalls that have structure arguments which layout 1346 in memory differs between the legacy ABI and the new ARM EABI 1347 (only for non "thumb" binaries). This option adds a tiny 1348 overhead to all syscalls and produces a slightly larger kernel. 1349 1350 The seccomp filter system will not be available when this is 1351 selected, since there is no way yet to sensibly distinguish 1352 between calling conventions during filtering. 1353 1354 If you know you'll be using only pure EABI user space then you 1355 can say N here. If this option is not selected and you attempt 1356 to execute a legacy ABI binary then the result will be 1357 UNPREDICTABLE (in fact it can be predicted that it won't work 1358 at all). If in doubt say N. 1359 1360config ARCH_SELECT_MEMORY_MODEL 1361 bool 1362 1363config ARCH_FLATMEM_ENABLE 1364 bool 1365 1366config ARCH_SPARSEMEM_ENABLE 1367 bool 1368 select SPARSEMEM_STATIC if SPARSEMEM 1369 1370config HIGHMEM 1371 bool "High Memory Support" 1372 depends on MMU 1373 select KMAP_LOCAL 1374 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1375 help 1376 The address space of ARM processors is only 4 Gigabytes large 1377 and it has to accommodate user address space, kernel address 1378 space as well as some memory mapped IO. That means that, if you 1379 have a large amount of physical memory and/or IO, not all of the 1380 memory can be "permanently mapped" by the kernel. The physical 1381 memory that is not permanently mapped is called "high memory". 1382 1383 Depending on the selected kernel/user memory split, minimum 1384 vmalloc space and actual amount of RAM, you may not need this 1385 option which should result in a slightly faster kernel. 1386 1387 If unsure, say n. 1388 1389config HIGHPTE 1390 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1391 depends on HIGHMEM 1392 default y 1393 help 1394 The VM uses one page of physical memory for each page table. 1395 For systems with a lot of processes, this can use a lot of 1396 precious low memory, eventually leading to low memory being 1397 consumed by page tables. Setting this option will allow 1398 user-space 2nd level page tables to reside in high memory. 1399 1400config CPU_SW_DOMAIN_PAN 1401 bool "Enable use of CPU domains to implement privileged no-access" 1402 depends on MMU && !ARM_LPAE 1403 default y 1404 help 1405 Increase kernel security by ensuring that normal kernel accesses 1406 are unable to access userspace addresses. This can help prevent 1407 use-after-free bugs becoming an exploitable privilege escalation 1408 by ensuring that magic values (such as LIST_POISON) will always 1409 fault when dereferenced. 1410 1411 CPUs with low-vector mappings use a best-efforts implementation. 1412 Their lower 1MB needs to remain accessible for the vectors, but 1413 the remainder of userspace will become appropriately inaccessible. 1414 1415config HW_PERF_EVENTS 1416 def_bool y 1417 depends on ARM_PMU 1418 1419config ARM_MODULE_PLTS 1420 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1421 depends on MODULES 1422 select KASAN_VMALLOC if KASAN 1423 default y 1424 help 1425 Allocate PLTs when loading modules so that jumps and calls whose 1426 targets are too far away for their relative offsets to be encoded 1427 in the instructions themselves can be bounced via veneers in the 1428 module's PLT. This allows modules to be allocated in the generic 1429 vmalloc area after the dedicated module memory area has been 1430 exhausted. The modules will use slightly more memory, but after 1431 rounding up to page size, the actual memory footprint is usually 1432 the same. 1433 1434 Disabling this is usually safe for small single-platform 1435 configurations. If unsure, say y. 1436 1437config FORCE_MAX_ZONEORDER 1438 int "Maximum zone order" 1439 default "12" if SOC_AM33XX 1440 default "9" if SA1111 1441 default "11" 1442 help 1443 The kernel memory allocator divides physically contiguous memory 1444 blocks into "zones", where each zone is a power of two number of 1445 pages. This option selects the largest power of two that the kernel 1446 keeps in the memory allocator. If you need to allocate very large 1447 blocks of physically contiguous memory, then you may need to 1448 increase this value. 1449 1450 This config option is actually maximum order plus one. For example, 1451 a value of 11 means that the largest free memory block is 2^10 pages. 1452 1453config ALIGNMENT_TRAP 1454 def_bool CPU_CP15_MMU 1455 select HAVE_PROC_CPU if PROC_FS 1456 help 1457 ARM processors cannot fetch/store information which is not 1458 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1459 address divisible by 4. On 32-bit ARM processors, these non-aligned 1460 fetch/store instructions will be emulated in software if you say 1461 here, which has a severe performance impact. This is necessary for 1462 correct operation of some network protocols. With an IP-only 1463 configuration it is safe to say N, otherwise say Y. 1464 1465config UACCESS_WITH_MEMCPY 1466 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1467 depends on MMU 1468 default y if CPU_FEROCEON 1469 help 1470 Implement faster copy_to_user and clear_user methods for CPU 1471 cores where a 8-word STM instruction give significantly higher 1472 memory write throughput than a sequence of individual 32bit stores. 1473 1474 A possible side effect is a slight increase in scheduling latency 1475 between threads sharing the same address space if they invoke 1476 such copy operations with large buffers. 1477 1478 However, if the CPU data cache is using a write-allocate mode, 1479 this option is unlikely to provide any performance gain. 1480 1481config PARAVIRT 1482 bool "Enable paravirtualization code" 1483 help 1484 This changes the kernel so it can modify itself when it is run 1485 under a hypervisor, potentially improving performance significantly 1486 over full virtualization. 1487 1488config PARAVIRT_TIME_ACCOUNTING 1489 bool "Paravirtual steal time accounting" 1490 select PARAVIRT 1491 help 1492 Select this option to enable fine granularity task steal time 1493 accounting. Time spent executing other tasks in parallel with 1494 the current vCPU is discounted from the vCPU power. To account for 1495 that, there can be a small performance impact. 1496 1497 If in doubt, say N here. 1498 1499config XEN_DOM0 1500 def_bool y 1501 depends on XEN 1502 1503config XEN 1504 bool "Xen guest support on ARM" 1505 depends on ARM && AEABI && OF 1506 depends on CPU_V7 && !CPU_V6 1507 depends on !GENERIC_ATOMIC64 1508 depends on MMU 1509 select ARCH_DMA_ADDR_T_64BIT 1510 select ARM_PSCI 1511 select SWIOTLB 1512 select SWIOTLB_XEN 1513 select PARAVIRT 1514 help 1515 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1516 1517config CC_HAVE_STACKPROTECTOR_TLS 1518 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1519 1520config STACKPROTECTOR_PER_TASK 1521 bool "Use a unique stack canary value for each task" 1522 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1523 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1524 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1525 default y 1526 help 1527 Due to the fact that GCC uses an ordinary symbol reference from 1528 which to load the value of the stack canary, this value can only 1529 change at reboot time on SMP systems, and all tasks running in the 1530 kernel's address space are forced to use the same canary value for 1531 the entire duration that the system is up. 1532 1533 Enable this option to switch to a different method that uses a 1534 different canary value for each task. 1535 1536endmenu 1537 1538menu "Boot options" 1539 1540config USE_OF 1541 bool "Flattened Device Tree support" 1542 select IRQ_DOMAIN 1543 select OF 1544 help 1545 Include support for flattened device tree machine descriptions. 1546 1547config ATAGS 1548 bool "Support for the traditional ATAGS boot data passing" 1549 default y 1550 help 1551 This is the traditional way of passing data to the kernel at boot 1552 time. If you are solely relying on the flattened device tree (or 1553 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1554 to remove ATAGS support from your kernel binary. 1555 1556config UNUSED_BOARD_FILES 1557 bool "Board support for machines without known users" 1558 depends on ATAGS 1559 help 1560 Most ATAGS based board files are completely unused and are 1561 scheduled for removal in early 2023, and left out of kernels 1562 by default now. If you are using a board file that is marked 1563 as unused, turn on this option to build support into the kernel. 1564 1565 To keep support for your individual board from being removed, 1566 send a reply to the email discussion at 1567 https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/ 1568 1569config DEPRECATED_PARAM_STRUCT 1570 bool "Provide old way to pass kernel parameters" 1571 depends on ATAGS 1572 help 1573 This was deprecated in 2001 and announced to live on for 5 years. 1574 Some old boot loaders still use this way. 1575 1576# Compressed boot loader in ROM. Yes, we really want to ask about 1577# TEXT and BSS so we preserve their values in the config files. 1578config ZBOOT_ROM_TEXT 1579 hex "Compressed ROM boot loader base address" 1580 default 0x0 1581 help 1582 The physical address at which the ROM-able zImage is to be 1583 placed in the target. Platforms which normally make use of 1584 ROM-able zImage formats normally set this to a suitable 1585 value in their defconfig file. 1586 1587 If ZBOOT_ROM is not enabled, this has no effect. 1588 1589config ZBOOT_ROM_BSS 1590 hex "Compressed ROM boot loader BSS address" 1591 default 0x0 1592 help 1593 The base address of an area of read/write memory in the target 1594 for the ROM-able zImage which must be available while the 1595 decompressor is running. It must be large enough to hold the 1596 entire decompressed kernel plus an additional 128 KiB. 1597 Platforms which normally make use of ROM-able zImage formats 1598 normally set this to a suitable value in their defconfig file. 1599 1600 If ZBOOT_ROM is not enabled, this has no effect. 1601 1602config ZBOOT_ROM 1603 bool "Compressed boot loader in ROM/flash" 1604 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1605 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1606 help 1607 Say Y here if you intend to execute your compressed kernel image 1608 (zImage) directly from ROM or flash. If unsure, say N. 1609 1610config ARM_APPENDED_DTB 1611 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1612 depends on OF 1613 help 1614 With this option, the boot code will look for a device tree binary 1615 (DTB) appended to zImage 1616 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1617 1618 This is meant as a backward compatibility convenience for those 1619 systems with a bootloader that can't be upgraded to accommodate 1620 the documented boot protocol using a device tree. 1621 1622 Beware that there is very little in terms of protection against 1623 this option being confused by leftover garbage in memory that might 1624 look like a DTB header after a reboot if no actual DTB is appended 1625 to zImage. Do not leave this option active in a production kernel 1626 if you don't intend to always append a DTB. Proper passing of the 1627 location into r2 of a bootloader provided DTB is always preferable 1628 to this option. 1629 1630config ARM_ATAG_DTB_COMPAT 1631 bool "Supplement the appended DTB with traditional ATAG information" 1632 depends on ARM_APPENDED_DTB 1633 help 1634 Some old bootloaders can't be updated to a DTB capable one, yet 1635 they provide ATAGs with memory configuration, the ramdisk address, 1636 the kernel cmdline string, etc. Such information is dynamically 1637 provided by the bootloader and can't always be stored in a static 1638 DTB. To allow a device tree enabled kernel to be used with such 1639 bootloaders, this option allows zImage to extract the information 1640 from the ATAG list and store it at run time into the appended DTB. 1641 1642choice 1643 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1644 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1645 1646config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1647 bool "Use bootloader kernel arguments if available" 1648 help 1649 Uses the command-line options passed by the boot loader instead of 1650 the device tree bootargs property. If the boot loader doesn't provide 1651 any, the device tree bootargs property will be used. 1652 1653config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1654 bool "Extend with bootloader kernel arguments" 1655 help 1656 The command-line arguments provided by the boot loader will be 1657 appended to the the device tree bootargs property. 1658 1659endchoice 1660 1661config CMDLINE 1662 string "Default kernel command string" 1663 default "" 1664 help 1665 On some architectures (e.g. CATS), there is currently no way 1666 for the boot loader to pass arguments to the kernel. For these 1667 architectures, you should supply some command-line options at build 1668 time by entering them here. As a minimum, you should specify the 1669 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1670 1671choice 1672 prompt "Kernel command line type" if CMDLINE != "" 1673 default CMDLINE_FROM_BOOTLOADER 1674 depends on ATAGS 1675 1676config CMDLINE_FROM_BOOTLOADER 1677 bool "Use bootloader kernel arguments if available" 1678 help 1679 Uses the command-line options passed by the boot loader. If 1680 the boot loader doesn't provide any, the default kernel command 1681 string provided in CMDLINE will be used. 1682 1683config CMDLINE_EXTEND 1684 bool "Extend bootloader kernel arguments" 1685 help 1686 The command-line arguments provided by the boot loader will be 1687 appended to the default kernel command string. 1688 1689config CMDLINE_FORCE 1690 bool "Always use the default kernel command string" 1691 help 1692 Always use the default kernel command string, even if the boot 1693 loader passes other arguments to the kernel. 1694 This is useful if you cannot or don't want to change the 1695 command-line options your boot loader passes to the kernel. 1696endchoice 1697 1698config XIP_KERNEL 1699 bool "Kernel Execute-In-Place from ROM" 1700 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1701 help 1702 Execute-In-Place allows the kernel to run from non-volatile storage 1703 directly addressable by the CPU, such as NOR flash. This saves RAM 1704 space since the text section of the kernel is not loaded from flash 1705 to RAM. Read-write sections, such as the data section and stack, 1706 are still copied to RAM. The XIP kernel is not compressed since 1707 it has to run directly from flash, so it will take more space to 1708 store it. The flash address used to link the kernel object files, 1709 and for storing it, is configuration dependent. Therefore, if you 1710 say Y here, you must know the proper physical address where to 1711 store the kernel image depending on your own flash memory usage. 1712 1713 Also note that the make target becomes "make xipImage" rather than 1714 "make zImage" or "make Image". The final kernel binary to put in 1715 ROM memory will be arch/arm/boot/xipImage. 1716 1717 If unsure, say N. 1718 1719config XIP_PHYS_ADDR 1720 hex "XIP Kernel Physical Location" 1721 depends on XIP_KERNEL 1722 default "0x00080000" 1723 help 1724 This is the physical address in your flash memory the kernel will 1725 be linked for and stored to. This address is dependent on your 1726 own flash usage. 1727 1728config XIP_DEFLATED_DATA 1729 bool "Store kernel .data section compressed in ROM" 1730 depends on XIP_KERNEL 1731 select ZLIB_INFLATE 1732 help 1733 Before the kernel is actually executed, its .data section has to be 1734 copied to RAM from ROM. This option allows for storing that data 1735 in compressed form and decompressed to RAM rather than merely being 1736 copied, saving some precious ROM space. A possible drawback is a 1737 slightly longer boot delay. 1738 1739config KEXEC 1740 bool "Kexec system call (EXPERIMENTAL)" 1741 depends on (!SMP || PM_SLEEP_SMP) 1742 depends on MMU 1743 select KEXEC_CORE 1744 help 1745 kexec is a system call that implements the ability to shutdown your 1746 current kernel, and to start another kernel. It is like a reboot 1747 but it is independent of the system firmware. And like a reboot 1748 you can start any kernel with it, not just Linux. 1749 1750 It is an ongoing process to be certain the hardware in a machine 1751 is properly shutdown, so do not be surprised if this code does not 1752 initially work for you. 1753 1754config ATAGS_PROC 1755 bool "Export atags in procfs" 1756 depends on ATAGS && KEXEC 1757 default y 1758 help 1759 Should the atags used to boot the kernel be exported in an "atags" 1760 file in procfs. Useful with kexec. 1761 1762config CRASH_DUMP 1763 bool "Build kdump crash kernel (EXPERIMENTAL)" 1764 help 1765 Generate crash dump after being started by kexec. This should 1766 be normally only set in special crash dump kernels which are 1767 loaded in the main kernel with kexec-tools into a specially 1768 reserved region and then later executed after a crash by 1769 kdump/kexec. The crash dump kernel must be compiled to a 1770 memory address not used by the main kernel 1771 1772 For more details see Documentation/admin-guide/kdump/kdump.rst 1773 1774config AUTO_ZRELADDR 1775 bool "Auto calculation of the decompressed kernel image address" 1776 help 1777 ZRELADDR is the physical address where the decompressed kernel 1778 image will be placed. If AUTO_ZRELADDR is selected, the address 1779 will be determined at run-time, either by masking the current IP 1780 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1781 This assumes the zImage being placed in the first 128MB from 1782 start of memory. 1783 1784config EFI_STUB 1785 bool 1786 1787config EFI 1788 bool "UEFI runtime support" 1789 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1790 select UCS2_STRING 1791 select EFI_PARAMS_FROM_FDT 1792 select EFI_STUB 1793 select EFI_GENERIC_STUB 1794 select EFI_RUNTIME_WRAPPERS 1795 help 1796 This option provides support for runtime services provided 1797 by UEFI firmware (such as non-volatile variables, realtime 1798 clock, and platform reset). A UEFI stub is also provided to 1799 allow the kernel to be booted as an EFI application. This 1800 is only useful for kernels that may run on systems that have 1801 UEFI firmware. 1802 1803config DMI 1804 bool "Enable support for SMBIOS (DMI) tables" 1805 depends on EFI 1806 default y 1807 help 1808 This enables SMBIOS/DMI feature for systems. 1809 1810 This option is only useful on systems that have UEFI firmware. 1811 However, even with this option, the resultant kernel should 1812 continue to boot on existing non-UEFI platforms. 1813 1814 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1815 i.e., the the practice of identifying the platform via DMI to 1816 decide whether certain workarounds for buggy hardware and/or 1817 firmware need to be enabled. This would require the DMI subsystem 1818 to be enabled much earlier than we do on ARM, which is non-trivial. 1819 1820endmenu 1821 1822menu "CPU Power Management" 1823 1824source "drivers/cpufreq/Kconfig" 1825 1826source "drivers/cpuidle/Kconfig" 1827 1828endmenu 1829 1830menu "Floating point emulation" 1831 1832comment "At least one emulation must be selected" 1833 1834config FPE_NWFPE 1835 bool "NWFPE math emulation" 1836 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1837 help 1838 Say Y to include the NWFPE floating point emulator in the kernel. 1839 This is necessary to run most binaries. Linux does not currently 1840 support floating point hardware so you need to say Y here even if 1841 your machine has an FPA or floating point co-processor podule. 1842 1843 You may say N here if you are going to load the Acorn FPEmulator 1844 early in the bootup. 1845 1846config FPE_NWFPE_XP 1847 bool "Support extended precision" 1848 depends on FPE_NWFPE 1849 help 1850 Say Y to include 80-bit support in the kernel floating-point 1851 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1852 Note that gcc does not generate 80-bit operations by default, 1853 so in most cases this option only enlarges the size of the 1854 floating point emulator without any good reason. 1855 1856 You almost surely want to say N here. 1857 1858config FPE_FASTFPE 1859 bool "FastFPE math emulation (EXPERIMENTAL)" 1860 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1861 help 1862 Say Y here to include the FAST floating point emulator in the kernel. 1863 This is an experimental much faster emulator which now also has full 1864 precision for the mantissa. It does not support any exceptions. 1865 It is very simple, and approximately 3-6 times faster than NWFPE. 1866 1867 It should be sufficient for most programs. It may be not suitable 1868 for scientific calculations, but you have to check this for yourself. 1869 If you do not feel you need a faster FP emulation you should better 1870 choose NWFPE. 1871 1872config VFP 1873 bool "VFP-format floating point maths" 1874 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1875 help 1876 Say Y to include VFP support code in the kernel. This is needed 1877 if your hardware includes a VFP unit. 1878 1879 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1880 release notes and additional status information. 1881 1882 Say N if your target does not have VFP hardware. 1883 1884config VFPv3 1885 bool 1886 depends on VFP 1887 default y if CPU_V7 1888 1889config NEON 1890 bool "Advanced SIMD (NEON) Extension support" 1891 depends on VFPv3 && CPU_V7 1892 help 1893 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1894 Extension. 1895 1896config KERNEL_MODE_NEON 1897 bool "Support for NEON in kernel mode" 1898 depends on NEON && AEABI 1899 help 1900 Say Y to include support for NEON in kernel mode. 1901 1902endmenu 1903 1904menu "Power management options" 1905 1906source "kernel/power/Kconfig" 1907 1908config ARCH_SUSPEND_POSSIBLE 1909 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1910 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1911 def_bool y 1912 1913config ARM_CPU_SUSPEND 1914 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1915 depends on ARCH_SUSPEND_POSSIBLE 1916 1917config ARCH_HIBERNATION_POSSIBLE 1918 bool 1919 depends on MMU 1920 default y if ARCH_SUSPEND_POSSIBLE 1921 1922endmenu 1923 1924source "arch/arm/Kconfig.assembler" 1925