1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 39 select BUILDTIME_TABLE_SORT if MMU 40 select CLONE_BACKWARDS 41 select CPU_PM if SUSPEND || CPU_IDLE 42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 43 select DMA_DECLARE_COHERENT 44 select DMA_OPS 45 select DMA_REMAP if MMU 46 select EDAC_SUPPORT 47 select EDAC_ATOMIC_SCRUB 48 select GENERIC_ALLOCATOR 49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 52 select GENERIC_IRQ_IPI if SMP 53 select GENERIC_CPU_AUTOPROBE 54 select GENERIC_EARLY_IOREMAP 55 select GENERIC_IDLE_POLL_SETUP 56 select GENERIC_IRQ_PROBE 57 select GENERIC_IRQ_SHOW 58 select GENERIC_IRQ_SHOW_LEVEL 59 select GENERIC_PCI_IOMAP 60 select GENERIC_SCHED_CLOCK 61 select GENERIC_SMP_IDLE_THREAD 62 select GENERIC_STRNCPY_FROM_USER 63 select GENERIC_STRNLEN_USER 64 select HANDLE_DOMAIN_IRQ 65 select HARDIRQS_SW_RESEND 66 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 67 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 68 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 69 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 70 select HAVE_ARCH_MMAP_RND_BITS if MMU 71 select HAVE_ARCH_SECCOMP 72 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 73 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 74 select HAVE_ARCH_TRACEHOOK 75 select HAVE_ARM_SMCCC if CPU_V7 76 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 77 select HAVE_CONTEXT_TRACKING 78 select HAVE_C_RECORDMCOUNT 79 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 80 select HAVE_DMA_CONTIGUOUS if MMU 81 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 82 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 83 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 84 select HAVE_EXIT_THREAD 85 select HAVE_FAST_GUP if ARM_LPAE 86 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 87 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 88 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 89 select HAVE_GCC_PLUGINS 90 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 91 select HAVE_IDE if PCI || ISA || PCMCIA 92 select HAVE_IRQ_TIME_ACCOUNTING 93 select HAVE_KERNEL_GZIP 94 select HAVE_KERNEL_LZ4 95 select HAVE_KERNEL_LZMA 96 select HAVE_KERNEL_LZO 97 select HAVE_KERNEL_XZ 98 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 99 select HAVE_KRETPROBES if HAVE_KPROBES 100 select HAVE_MOD_ARCH_SPECIFIC 101 select HAVE_NMI 102 select HAVE_OPROFILE if HAVE_PERF_EVENTS 103 select HAVE_OPTPROBES if !THUMB2_KERNEL 104 select HAVE_PERF_EVENTS 105 select HAVE_PERF_REGS 106 select HAVE_PERF_USER_STACK_DUMP 107 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 108 select HAVE_REGS_AND_STACK_ACCESS_API 109 select HAVE_RSEQ 110 select HAVE_STACKPROTECTOR 111 select HAVE_SYSCALL_TRACEPOINTS 112 select HAVE_UID16 113 select HAVE_VIRT_CPU_ACCOUNTING_GEN 114 select IRQ_FORCED_THREADING 115 select MODULES_USE_ELF_REL 116 select NEED_DMA_MAP_STATE 117 select OF_EARLY_FLATTREE if OF 118 select OLD_SIGACTION 119 select OLD_SIGSUSPEND3 120 select PCI_SYSCALL if PCI 121 select PERF_USE_VMALLOC 122 select RTC_LIB 123 select SET_FS 124 select SYS_SUPPORTS_APM_EMULATION 125 # Above selects are sorted alphabetically; please add new ones 126 # according to that. Thanks. 127 help 128 The ARM series is a line of low-power-consumption RISC chip designs 129 licensed by ARM Ltd and targeted at embedded applications and 130 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 131 manufactured, but legacy ARM-based PC hardware remains popular in 132 Europe. There is an ARM Linux project with a web page at 133 <http://www.arm.linux.org.uk/>. 134 135config ARM_HAS_SG_CHAIN 136 bool 137 138config ARM_DMA_USE_IOMMU 139 bool 140 select ARM_HAS_SG_CHAIN 141 select NEED_SG_DMA_LENGTH 142 143if ARM_DMA_USE_IOMMU 144 145config ARM_DMA_IOMMU_ALIGNMENT 146 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 147 range 4 9 148 default 8 149 help 150 DMA mapping framework by default aligns all buffers to the smallest 151 PAGE_SIZE order which is greater than or equal to the requested buffer 152 size. This works well for buffers up to a few hundreds kilobytes, but 153 for larger buffers it just a waste of address space. Drivers which has 154 relatively small addressing window (like 64Mib) might run out of 155 virtual space with just a few allocations. 156 157 With this parameter you can specify the maximum PAGE_SIZE order for 158 DMA IOMMU buffers. Larger buffers will be aligned only to this 159 specified order. The order is expressed as a power of two multiplied 160 by the PAGE_SIZE. 161 162endif 163 164config SYS_SUPPORTS_APM_EMULATION 165 bool 166 167config HAVE_TCM 168 bool 169 select GENERIC_ALLOCATOR 170 171config HAVE_PROC_CPU 172 bool 173 174config NO_IOPORT_MAP 175 bool 176 177config SBUS 178 bool 179 180config STACKTRACE_SUPPORT 181 bool 182 default y 183 184config LOCKDEP_SUPPORT 185 bool 186 default y 187 188config TRACE_IRQFLAGS_SUPPORT 189 bool 190 default !CPU_V7M 191 192config ARCH_HAS_ILOG2_U32 193 bool 194 195config ARCH_HAS_ILOG2_U64 196 bool 197 198config ARCH_HAS_BANDGAP 199 bool 200 201config FIX_EARLYCON_MEM 202 def_bool y if MMU 203 204config GENERIC_HWEIGHT 205 bool 206 default y 207 208config GENERIC_CALIBRATE_DELAY 209 bool 210 default y 211 212config ARCH_MAY_HAVE_PC_FDC 213 bool 214 215config ZONE_DMA 216 bool 217 218config ARCH_SUPPORTS_UPROBES 219 def_bool y 220 221config ARCH_HAS_DMA_SET_COHERENT_MASK 222 bool 223 224config GENERIC_ISA_DMA 225 bool 226 227config FIQ 228 bool 229 230config NEED_RET_TO_USER 231 bool 232 233config ARCH_MTD_XIP 234 bool 235 236config ARM_PATCH_PHYS_VIRT 237 bool "Patch physical to virtual translations at runtime" if EMBEDDED 238 default y 239 depends on !XIP_KERNEL && MMU 240 help 241 Patch phys-to-virt and virt-to-phys translation functions at 242 boot and module load time according to the position of the 243 kernel in system memory. 244 245 This can only be used with non-XIP MMU kernels where the base 246 of physical memory is at a 16MB boundary. 247 248 Only disable this option if you know that you do not require 249 this feature (eg, building a kernel for a single machine) and 250 you need to shrink the kernel to the minimal size. 251 252config NEED_MACH_IO_H 253 bool 254 help 255 Select this when mach/io.h is required to provide special 256 definitions for this platform. The need for mach/io.h should 257 be avoided when possible. 258 259config NEED_MACH_MEMORY_H 260 bool 261 help 262 Select this when mach/memory.h is required to provide special 263 definitions for this platform. The need for mach/memory.h should 264 be avoided when possible. 265 266config PHYS_OFFSET 267 hex "Physical address of main memory" if MMU 268 depends on !ARM_PATCH_PHYS_VIRT 269 default DRAM_BASE if !MMU 270 default 0x00000000 if ARCH_EBSA110 || \ 271 ARCH_FOOTBRIDGE 272 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 273 default 0x20000000 if ARCH_S5PV210 274 default 0xc0000000 if ARCH_SA1100 275 help 276 Please provide the physical address corresponding to the 277 location of main memory in your system. 278 279config GENERIC_BUG 280 def_bool y 281 depends on BUG 282 283config PGTABLE_LEVELS 284 int 285 default 3 if ARM_LPAE 286 default 2 287 288menu "System Type" 289 290config MMU 291 bool "MMU-based Paged Memory Management Support" 292 default y 293 help 294 Select if you want MMU-based virtualised addressing space 295 support by paged memory management. If unsure, say 'Y'. 296 297config ARCH_MMAP_RND_BITS_MIN 298 default 8 299 300config ARCH_MMAP_RND_BITS_MAX 301 default 14 if PAGE_OFFSET=0x40000000 302 default 15 if PAGE_OFFSET=0x80000000 303 default 16 304 305# 306# The "ARM system type" choice list is ordered alphabetically by option 307# text. Please add new entries in the option alphabetic order. 308# 309choice 310 prompt "ARM system type" 311 default ARM_SINGLE_ARMV7M if !MMU 312 default ARCH_MULTIPLATFORM if MMU 313 314config ARCH_MULTIPLATFORM 315 bool "Allow multiple platforms to be selected" 316 depends on MMU 317 select ARCH_FLATMEM_ENABLE 318 select ARCH_SPARSEMEM_ENABLE 319 select ARCH_SELECT_MEMORY_MODEL 320 select ARM_HAS_SG_CHAIN 321 select ARM_PATCH_PHYS_VIRT 322 select AUTO_ZRELADDR 323 select TIMER_OF 324 select COMMON_CLK 325 select GENERIC_CLOCKEVENTS 326 select GENERIC_IRQ_MULTI_HANDLER 327 select HAVE_PCI 328 select PCI_DOMAINS_GENERIC if PCI 329 select SPARSE_IRQ 330 select USE_OF 331 332config ARM_SINGLE_ARMV7M 333 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 334 depends on !MMU 335 select ARM_NVIC 336 select AUTO_ZRELADDR 337 select TIMER_OF 338 select COMMON_CLK 339 select CPU_V7M 340 select GENERIC_CLOCKEVENTS 341 select NO_IOPORT_MAP 342 select SPARSE_IRQ 343 select USE_OF 344 345config ARCH_EBSA110 346 bool "EBSA-110" 347 select ARCH_USES_GETTIMEOFFSET 348 select CPU_SA110 349 select ISA 350 select NEED_MACH_IO_H 351 select NEED_MACH_MEMORY_H 352 select NO_IOPORT_MAP 353 help 354 This is an evaluation board for the StrongARM processor available 355 from Digital. It has limited hardware on-board, including an 356 Ethernet interface, two PCMCIA sockets, two serial ports and a 357 parallel port. 358 359config ARCH_EP93XX 360 bool "EP93xx-based" 361 select ARCH_SPARSEMEM_ENABLE 362 select ARM_AMBA 363 imply ARM_PATCH_PHYS_VIRT 364 select ARM_VIC 365 select AUTO_ZRELADDR 366 select CLKDEV_LOOKUP 367 select CLKSRC_MMIO 368 select CPU_ARM920T 369 select GENERIC_CLOCKEVENTS 370 select GPIOLIB 371 select HAVE_LEGACY_CLK 372 help 373 This enables support for the Cirrus EP93xx series of CPUs. 374 375config ARCH_FOOTBRIDGE 376 bool "FootBridge" 377 select CPU_SA110 378 select FOOTBRIDGE 379 select GENERIC_CLOCKEVENTS 380 select HAVE_IDE 381 select NEED_MACH_IO_H if !MMU 382 select NEED_MACH_MEMORY_H 383 help 384 Support for systems based on the DC21285 companion chip 385 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 386 387config ARCH_IOP32X 388 bool "IOP32x-based" 389 depends on MMU 390 select CPU_XSCALE 391 select GPIO_IOP 392 select GPIOLIB 393 select NEED_RET_TO_USER 394 select FORCE_PCI 395 select PLAT_IOP 396 help 397 Support for Intel's 80219 and IOP32X (XScale) family of 398 processors. 399 400config ARCH_IXP4XX 401 bool "IXP4xx-based" 402 depends on MMU 403 select ARCH_HAS_DMA_SET_COHERENT_MASK 404 select ARCH_SUPPORTS_BIG_ENDIAN 405 select CPU_XSCALE 406 select DMABOUNCE if PCI 407 select GENERIC_CLOCKEVENTS 408 select GENERIC_IRQ_MULTI_HANDLER 409 select GPIO_IXP4XX 410 select GPIOLIB 411 select HAVE_PCI 412 select IXP4XX_IRQ 413 select IXP4XX_TIMER 414 select NEED_MACH_IO_H 415 select USB_EHCI_BIG_ENDIAN_DESC 416 select USB_EHCI_BIG_ENDIAN_MMIO 417 help 418 Support for Intel's IXP4XX (XScale) family of processors. 419 420config ARCH_DOVE 421 bool "Marvell Dove" 422 select CPU_PJ4 423 select GENERIC_CLOCKEVENTS 424 select GENERIC_IRQ_MULTI_HANDLER 425 select GPIOLIB 426 select HAVE_PCI 427 select MVEBU_MBUS 428 select PINCTRL 429 select PINCTRL_DOVE 430 select PLAT_ORION_LEGACY 431 select SPARSE_IRQ 432 select PM_GENERIC_DOMAINS if PM 433 help 434 Support for the Marvell Dove SoC 88AP510 435 436config ARCH_PXA 437 bool "PXA2xx/PXA3xx-based" 438 depends on MMU 439 select ARCH_MTD_XIP 440 select ARM_CPU_SUSPEND if PM 441 select AUTO_ZRELADDR 442 select COMMON_CLK 443 select CLKSRC_PXA 444 select CLKSRC_MMIO 445 select TIMER_OF 446 select CPU_XSCALE if !CPU_XSC3 447 select GENERIC_CLOCKEVENTS 448 select GENERIC_IRQ_MULTI_HANDLER 449 select GPIO_PXA 450 select GPIOLIB 451 select HAVE_IDE 452 select IRQ_DOMAIN 453 select PLAT_PXA 454 select SPARSE_IRQ 455 help 456 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 457 458config ARCH_RPC 459 bool "RiscPC" 460 depends on MMU 461 select ARCH_ACORN 462 select ARCH_MAY_HAVE_PC_FDC 463 select ARCH_SPARSEMEM_ENABLE 464 select ARM_HAS_SG_CHAIN 465 select CPU_SA110 466 select FIQ 467 select HAVE_IDE 468 select HAVE_PATA_PLATFORM 469 select ISA_DMA_API 470 select NEED_MACH_IO_H 471 select NEED_MACH_MEMORY_H 472 select NO_IOPORT_MAP 473 help 474 On the Acorn Risc-PC, Linux can support the internal IDE disk and 475 CD-ROM interface, serial and parallel port, and the floppy drive. 476 477config ARCH_SA1100 478 bool "SA1100-based" 479 select ARCH_MTD_XIP 480 select ARCH_SPARSEMEM_ENABLE 481 select CLKSRC_MMIO 482 select CLKSRC_PXA 483 select TIMER_OF if OF 484 select COMMON_CLK 485 select CPU_FREQ 486 select CPU_SA1100 487 select GENERIC_CLOCKEVENTS 488 select GENERIC_IRQ_MULTI_HANDLER 489 select GPIOLIB 490 select HAVE_IDE 491 select IRQ_DOMAIN 492 select ISA 493 select NEED_MACH_MEMORY_H 494 select SPARSE_IRQ 495 help 496 Support for StrongARM 11x0 based boards. 497 498config ARCH_S3C24XX 499 bool "Samsung S3C24XX SoCs" 500 select ATAGS 501 select CLKSRC_SAMSUNG_PWM 502 select GENERIC_CLOCKEVENTS 503 select GPIO_SAMSUNG 504 select GPIOLIB 505 select GENERIC_IRQ_MULTI_HANDLER 506 select HAVE_S3C2410_I2C if I2C 507 select HAVE_S3C_RTC if RTC_CLASS 508 select NEED_MACH_IO_H 509 select S3C2410_WATCHDOG 510 select SAMSUNG_ATAGS 511 select USE_OF 512 select WATCHDOG 513 help 514 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 515 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 516 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 517 Samsung SMDK2410 development board (and derivatives). 518 519config ARCH_OMAP1 520 bool "TI OMAP1" 521 depends on MMU 522 select ARCH_HAS_HOLES_MEMORYMODEL 523 select ARCH_OMAP 524 select CLKDEV_LOOKUP 525 select CLKSRC_MMIO 526 select GENERIC_CLOCKEVENTS 527 select GENERIC_IRQ_CHIP 528 select GENERIC_IRQ_MULTI_HANDLER 529 select GPIOLIB 530 select HAVE_IDE 531 select HAVE_LEGACY_CLK 532 select IRQ_DOMAIN 533 select NEED_MACH_IO_H if PCCARD 534 select NEED_MACH_MEMORY_H 535 select SPARSE_IRQ 536 help 537 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 538 539endchoice 540 541menu "Multiple platform selection" 542 depends on ARCH_MULTIPLATFORM 543 544comment "CPU Core family selection" 545 546config ARCH_MULTI_V4 547 bool "ARMv4 based platforms (FA526)" 548 depends on !ARCH_MULTI_V6_V7 549 select ARCH_MULTI_V4_V5 550 select CPU_FA526 551 552config ARCH_MULTI_V4T 553 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 554 depends on !ARCH_MULTI_V6_V7 555 select ARCH_MULTI_V4_V5 556 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 557 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 558 CPU_ARM925T || CPU_ARM940T) 559 560config ARCH_MULTI_V5 561 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 562 depends on !ARCH_MULTI_V6_V7 563 select ARCH_MULTI_V4_V5 564 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 565 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 566 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 567 568config ARCH_MULTI_V4_V5 569 bool 570 571config ARCH_MULTI_V6 572 bool "ARMv6 based platforms (ARM11)" 573 select ARCH_MULTI_V6_V7 574 select CPU_V6K 575 576config ARCH_MULTI_V7 577 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 578 default y 579 select ARCH_MULTI_V6_V7 580 select CPU_V7 581 select HAVE_SMP 582 583config ARCH_MULTI_V6_V7 584 bool 585 select MIGHT_HAVE_CACHE_L2X0 586 587config ARCH_MULTI_CPU_AUTO 588 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 589 select ARCH_MULTI_V5 590 591endmenu 592 593config ARCH_VIRT 594 bool "Dummy Virtual Machine" 595 depends on ARCH_MULTI_V7 596 select ARM_AMBA 597 select ARM_GIC 598 select ARM_GIC_V2M if PCI 599 select ARM_GIC_V3 600 select ARM_GIC_V3_ITS if PCI 601 select ARM_PSCI 602 select HAVE_ARM_ARCH_TIMER 603 select ARCH_SUPPORTS_BIG_ENDIAN 604 605# 606# This is sorted alphabetically by mach-* pathname. However, plat-* 607# Kconfigs may be included either alphabetically (according to the 608# plat- suffix) or along side the corresponding mach-* source. 609# 610source "arch/arm/mach-actions/Kconfig" 611 612source "arch/arm/mach-alpine/Kconfig" 613 614source "arch/arm/mach-artpec/Kconfig" 615 616source "arch/arm/mach-asm9260/Kconfig" 617 618source "arch/arm/mach-aspeed/Kconfig" 619 620source "arch/arm/mach-at91/Kconfig" 621 622source "arch/arm/mach-axxia/Kconfig" 623 624source "arch/arm/mach-bcm/Kconfig" 625 626source "arch/arm/mach-berlin/Kconfig" 627 628source "arch/arm/mach-clps711x/Kconfig" 629 630source "arch/arm/mach-cns3xxx/Kconfig" 631 632source "arch/arm/mach-davinci/Kconfig" 633 634source "arch/arm/mach-digicolor/Kconfig" 635 636source "arch/arm/mach-dove/Kconfig" 637 638source "arch/arm/mach-ep93xx/Kconfig" 639 640source "arch/arm/mach-exynos/Kconfig" 641 642source "arch/arm/mach-footbridge/Kconfig" 643 644source "arch/arm/mach-gemini/Kconfig" 645 646source "arch/arm/mach-highbank/Kconfig" 647 648source "arch/arm/mach-hisi/Kconfig" 649 650source "arch/arm/mach-imx/Kconfig" 651 652source "arch/arm/mach-integrator/Kconfig" 653 654source "arch/arm/mach-iop32x/Kconfig" 655 656source "arch/arm/mach-ixp4xx/Kconfig" 657 658source "arch/arm/mach-keystone/Kconfig" 659 660source "arch/arm/mach-lpc32xx/Kconfig" 661 662source "arch/arm/mach-mediatek/Kconfig" 663 664source "arch/arm/mach-meson/Kconfig" 665 666source "arch/arm/mach-milbeaut/Kconfig" 667 668source "arch/arm/mach-mmp/Kconfig" 669 670source "arch/arm/mach-moxart/Kconfig" 671 672source "arch/arm/mach-mstar/Kconfig" 673 674source "arch/arm/mach-mv78xx0/Kconfig" 675 676source "arch/arm/mach-mvebu/Kconfig" 677 678source "arch/arm/mach-mxs/Kconfig" 679 680source "arch/arm/mach-nomadik/Kconfig" 681 682source "arch/arm/mach-npcm/Kconfig" 683 684source "arch/arm/mach-nspire/Kconfig" 685 686source "arch/arm/plat-omap/Kconfig" 687 688source "arch/arm/mach-omap1/Kconfig" 689 690source "arch/arm/mach-omap2/Kconfig" 691 692source "arch/arm/mach-orion5x/Kconfig" 693 694source "arch/arm/mach-oxnas/Kconfig" 695 696source "arch/arm/mach-picoxcell/Kconfig" 697 698source "arch/arm/mach-prima2/Kconfig" 699 700source "arch/arm/mach-pxa/Kconfig" 701source "arch/arm/plat-pxa/Kconfig" 702 703source "arch/arm/mach-qcom/Kconfig" 704 705source "arch/arm/mach-rda/Kconfig" 706 707source "arch/arm/mach-realtek/Kconfig" 708 709source "arch/arm/mach-realview/Kconfig" 710 711source "arch/arm/mach-rockchip/Kconfig" 712 713source "arch/arm/mach-s3c/Kconfig" 714 715source "arch/arm/mach-s5pv210/Kconfig" 716 717source "arch/arm/mach-sa1100/Kconfig" 718 719source "arch/arm/mach-shmobile/Kconfig" 720 721source "arch/arm/mach-socfpga/Kconfig" 722 723source "arch/arm/mach-spear/Kconfig" 724 725source "arch/arm/mach-sti/Kconfig" 726 727source "arch/arm/mach-stm32/Kconfig" 728 729source "arch/arm/mach-sunxi/Kconfig" 730 731source "arch/arm/mach-tango/Kconfig" 732 733source "arch/arm/mach-tegra/Kconfig" 734 735source "arch/arm/mach-u300/Kconfig" 736 737source "arch/arm/mach-uniphier/Kconfig" 738 739source "arch/arm/mach-ux500/Kconfig" 740 741source "arch/arm/mach-versatile/Kconfig" 742 743source "arch/arm/mach-vexpress/Kconfig" 744 745source "arch/arm/mach-vt8500/Kconfig" 746 747source "arch/arm/mach-zx/Kconfig" 748 749source "arch/arm/mach-zynq/Kconfig" 750 751# ARMv7-M architecture 752config ARCH_EFM32 753 bool "Energy Micro efm32" 754 depends on ARM_SINGLE_ARMV7M 755 select GPIOLIB 756 help 757 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 758 processors. 759 760config ARCH_LPC18XX 761 bool "NXP LPC18xx/LPC43xx" 762 depends on ARM_SINGLE_ARMV7M 763 select ARCH_HAS_RESET_CONTROLLER 764 select ARM_AMBA 765 select CLKSRC_LPC32XX 766 select PINCTRL 767 help 768 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 769 high performance microcontrollers. 770 771config ARCH_MPS2 772 bool "ARM MPS2 platform" 773 depends on ARM_SINGLE_ARMV7M 774 select ARM_AMBA 775 select CLKSRC_MPS2 776 help 777 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 778 with a range of available cores like Cortex-M3/M4/M7. 779 780 Please, note that depends which Application Note is used memory map 781 for the platform may vary, so adjustment of RAM base might be needed. 782 783# Definitions to make life easier 784config ARCH_ACORN 785 bool 786 787config PLAT_IOP 788 bool 789 select GENERIC_CLOCKEVENTS 790 791config PLAT_ORION 792 bool 793 select CLKSRC_MMIO 794 select COMMON_CLK 795 select GENERIC_IRQ_CHIP 796 select IRQ_DOMAIN 797 798config PLAT_ORION_LEGACY 799 bool 800 select PLAT_ORION 801 802config PLAT_PXA 803 bool 804 805config PLAT_VERSATILE 806 bool 807 808source "arch/arm/mm/Kconfig" 809 810config IWMMXT 811 bool "Enable iWMMXt support" 812 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 813 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 814 help 815 Enable support for iWMMXt context switching at run time if 816 running on a CPU that supports it. 817 818if !MMU 819source "arch/arm/Kconfig-nommu" 820endif 821 822config PJ4B_ERRATA_4742 823 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 824 depends on CPU_PJ4B && MACH_ARMADA_370 825 default y 826 help 827 When coming out of either a Wait for Interrupt (WFI) or a Wait for 828 Event (WFE) IDLE states, a specific timing sensitivity exists between 829 the retiring WFI/WFE instructions and the newly issued subsequent 830 instructions. This sensitivity can result in a CPU hang scenario. 831 Workaround: 832 The software must insert either a Data Synchronization Barrier (DSB) 833 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 834 instruction 835 836config ARM_ERRATA_326103 837 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 838 depends on CPU_V6 839 help 840 Executing a SWP instruction to read-only memory does not set bit 11 841 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 842 treat the access as a read, preventing a COW from occurring and 843 causing the faulting task to livelock. 844 845config ARM_ERRATA_411920 846 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 847 depends on CPU_V6 || CPU_V6K 848 help 849 Invalidation of the Instruction Cache operation can 850 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 851 It does not affect the MPCore. This option enables the ARM Ltd. 852 recommended workaround. 853 854config ARM_ERRATA_430973 855 bool "ARM errata: Stale prediction on replaced interworking branch" 856 depends on CPU_V7 857 help 858 This option enables the workaround for the 430973 Cortex-A8 859 r1p* erratum. If a code sequence containing an ARM/Thumb 860 interworking branch is replaced with another code sequence at the 861 same virtual address, whether due to self-modifying code or virtual 862 to physical address re-mapping, Cortex-A8 does not recover from the 863 stale interworking branch prediction. This results in Cortex-A8 864 executing the new code sequence in the incorrect ARM or Thumb state. 865 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 866 and also flushes the branch target cache at every context switch. 867 Note that setting specific bits in the ACTLR register may not be 868 available in non-secure mode. 869 870config ARM_ERRATA_458693 871 bool "ARM errata: Processor deadlock when a false hazard is created" 872 depends on CPU_V7 873 depends on !ARCH_MULTIPLATFORM 874 help 875 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 876 erratum. For very specific sequences of memory operations, it is 877 possible for a hazard condition intended for a cache line to instead 878 be incorrectly associated with a different cache line. This false 879 hazard might then cause a processor deadlock. The workaround enables 880 the L1 caching of the NEON accesses and disables the PLD instruction 881 in the ACTLR register. Note that setting specific bits in the ACTLR 882 register may not be available in non-secure mode. 883 884config ARM_ERRATA_460075 885 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 886 depends on CPU_V7 887 depends on !ARCH_MULTIPLATFORM 888 help 889 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 890 erratum. Any asynchronous access to the L2 cache may encounter a 891 situation in which recent store transactions to the L2 cache are lost 892 and overwritten with stale memory contents from external memory. The 893 workaround disables the write-allocate mode for the L2 cache via the 894 ACTLR register. Note that setting specific bits in the ACTLR register 895 may not be available in non-secure mode. 896 897config ARM_ERRATA_742230 898 bool "ARM errata: DMB operation may be faulty" 899 depends on CPU_V7 && SMP 900 depends on !ARCH_MULTIPLATFORM 901 help 902 This option enables the workaround for the 742230 Cortex-A9 903 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 904 between two write operations may not ensure the correct visibility 905 ordering of the two writes. This workaround sets a specific bit in 906 the diagnostic register of the Cortex-A9 which causes the DMB 907 instruction to behave as a DSB, ensuring the correct behaviour of 908 the two writes. 909 910config ARM_ERRATA_742231 911 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 912 depends on CPU_V7 && SMP 913 depends on !ARCH_MULTIPLATFORM 914 help 915 This option enables the workaround for the 742231 Cortex-A9 916 (r2p0..r2p2) erratum. Under certain conditions, specific to the 917 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 918 accessing some data located in the same cache line, may get corrupted 919 data due to bad handling of the address hazard when the line gets 920 replaced from one of the CPUs at the same time as another CPU is 921 accessing it. This workaround sets specific bits in the diagnostic 922 register of the Cortex-A9 which reduces the linefill issuing 923 capabilities of the processor. 924 925config ARM_ERRATA_643719 926 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 927 depends on CPU_V7 && SMP 928 default y 929 help 930 This option enables the workaround for the 643719 Cortex-A9 (prior to 931 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 932 register returns zero when it should return one. The workaround 933 corrects this value, ensuring cache maintenance operations which use 934 it behave as intended and avoiding data corruption. 935 936config ARM_ERRATA_720789 937 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 938 depends on CPU_V7 939 help 940 This option enables the workaround for the 720789 Cortex-A9 (prior to 941 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 942 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 943 As a consequence of this erratum, some TLB entries which should be 944 invalidated are not, resulting in an incoherency in the system page 945 tables. The workaround changes the TLB flushing routines to invalidate 946 entries regardless of the ASID. 947 948config ARM_ERRATA_743622 949 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 950 depends on CPU_V7 951 depends on !ARCH_MULTIPLATFORM 952 help 953 This option enables the workaround for the 743622 Cortex-A9 954 (r2p*) erratum. Under very rare conditions, a faulty 955 optimisation in the Cortex-A9 Store Buffer may lead to data 956 corruption. This workaround sets a specific bit in the diagnostic 957 register of the Cortex-A9 which disables the Store Buffer 958 optimisation, preventing the defect from occurring. This has no 959 visible impact on the overall performance or power consumption of the 960 processor. 961 962config ARM_ERRATA_751472 963 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 964 depends on CPU_V7 965 depends on !ARCH_MULTIPLATFORM 966 help 967 This option enables the workaround for the 751472 Cortex-A9 (prior 968 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 969 completion of a following broadcasted operation if the second 970 operation is received by a CPU before the ICIALLUIS has completed, 971 potentially leading to corrupted entries in the cache or TLB. 972 973config ARM_ERRATA_754322 974 bool "ARM errata: possible faulty MMU translations following an ASID switch" 975 depends on CPU_V7 976 help 977 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 978 r3p*) erratum. A speculative memory access may cause a page table walk 979 which starts prior to an ASID switch but completes afterwards. This 980 can populate the micro-TLB with a stale entry which may be hit with 981 the new ASID. This workaround places two dsb instructions in the mm 982 switching code so that no page table walks can cross the ASID switch. 983 984config ARM_ERRATA_754327 985 bool "ARM errata: no automatic Store Buffer drain" 986 depends on CPU_V7 && SMP 987 help 988 This option enables the workaround for the 754327 Cortex-A9 (prior to 989 r2p0) erratum. The Store Buffer does not have any automatic draining 990 mechanism and therefore a livelock may occur if an external agent 991 continuously polls a memory location waiting to observe an update. 992 This workaround defines cpu_relax() as smp_mb(), preventing correctly 993 written polling loops from denying visibility of updates to memory. 994 995config ARM_ERRATA_364296 996 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 997 depends on CPU_V6 998 help 999 This options enables the workaround for the 364296 ARM1136 1000 r0p2 erratum (possible cache data corruption with 1001 hit-under-miss enabled). It sets the undocumented bit 31 in 1002 the auxiliary control register and the FI bit in the control 1003 register, thus disabling hit-under-miss without putting the 1004 processor into full low interrupt latency mode. ARM11MPCore 1005 is not affected. 1006 1007config ARM_ERRATA_764369 1008 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1009 depends on CPU_V7 && SMP 1010 help 1011 This option enables the workaround for erratum 764369 1012 affecting Cortex-A9 MPCore with two or more processors (all 1013 current revisions). Under certain timing circumstances, a data 1014 cache line maintenance operation by MVA targeting an Inner 1015 Shareable memory region may fail to proceed up to either the 1016 Point of Coherency or to the Point of Unification of the 1017 system. This workaround adds a DSB instruction before the 1018 relevant cache maintenance functions and sets a specific bit 1019 in the diagnostic control register of the SCU. 1020 1021config ARM_ERRATA_775420 1022 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1023 depends on CPU_V7 1024 help 1025 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1026 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1027 operation aborts with MMU exception, it might cause the processor 1028 to deadlock. This workaround puts DSB before executing ISB if 1029 an abort may occur on cache maintenance. 1030 1031config ARM_ERRATA_798181 1032 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1033 depends on CPU_V7 && SMP 1034 help 1035 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1036 adequately shooting down all use of the old entries. This 1037 option enables the Linux kernel workaround for this erratum 1038 which sends an IPI to the CPUs that are running the same ASID 1039 as the one being invalidated. 1040 1041config ARM_ERRATA_773022 1042 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1043 depends on CPU_V7 1044 help 1045 This option enables the workaround for the 773022 Cortex-A15 1046 (up to r0p4) erratum. In certain rare sequences of code, the 1047 loop buffer may deliver incorrect instructions. This 1048 workaround disables the loop buffer to avoid the erratum. 1049 1050config ARM_ERRATA_818325_852422 1051 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1052 depends on CPU_V7 1053 help 1054 This option enables the workaround for: 1055 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1056 instruction might deadlock. Fixed in r0p1. 1057 - Cortex-A12 852422: Execution of a sequence of instructions might 1058 lead to either a data corruption or a CPU deadlock. Not fixed in 1059 any Cortex-A12 cores yet. 1060 This workaround for all both errata involves setting bit[12] of the 1061 Feature Register. This bit disables an optimisation applied to a 1062 sequence of 2 instructions that use opposing condition codes. 1063 1064config ARM_ERRATA_821420 1065 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1066 depends on CPU_V7 1067 help 1068 This option enables the workaround for the 821420 Cortex-A12 1069 (all revs) erratum. In very rare timing conditions, a sequence 1070 of VMOV to Core registers instructions, for which the second 1071 one is in the shadow of a branch or abort, can lead to a 1072 deadlock when the VMOV instructions are issued out-of-order. 1073 1074config ARM_ERRATA_825619 1075 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1076 depends on CPU_V7 1077 help 1078 This option enables the workaround for the 825619 Cortex-A12 1079 (all revs) erratum. Within rare timing constraints, executing a 1080 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1081 and Device/Strongly-Ordered loads and stores might cause deadlock 1082 1083config ARM_ERRATA_857271 1084 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1085 depends on CPU_V7 1086 help 1087 This option enables the workaround for the 857271 Cortex-A12 1088 (all revs) erratum. Under very rare timing conditions, the CPU might 1089 hang. The workaround is expected to have a < 1% performance impact. 1090 1091config ARM_ERRATA_852421 1092 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1093 depends on CPU_V7 1094 help 1095 This option enables the workaround for the 852421 Cortex-A17 1096 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1097 execution of a DMB ST instruction might fail to properly order 1098 stores from GroupA and stores from GroupB. 1099 1100config ARM_ERRATA_852423 1101 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1102 depends on CPU_V7 1103 help 1104 This option enables the workaround for: 1105 - Cortex-A17 852423: Execution of a sequence of instructions might 1106 lead to either a data corruption or a CPU deadlock. Not fixed in 1107 any Cortex-A17 cores yet. 1108 This is identical to Cortex-A12 erratum 852422. It is a separate 1109 config option from the A12 erratum due to the way errata are checked 1110 for and handled. 1111 1112config ARM_ERRATA_857272 1113 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1114 depends on CPU_V7 1115 help 1116 This option enables the workaround for the 857272 Cortex-A17 erratum. 1117 This erratum is not known to be fixed in any A17 revision. 1118 This is identical to Cortex-A12 erratum 857271. It is a separate 1119 config option from the A12 erratum due to the way errata are checked 1120 for and handled. 1121 1122endmenu 1123 1124source "arch/arm/common/Kconfig" 1125 1126menu "Bus support" 1127 1128config ISA 1129 bool 1130 help 1131 Find out whether you have ISA slots on your motherboard. ISA is the 1132 name of a bus system, i.e. the way the CPU talks to the other stuff 1133 inside your box. Other bus systems are PCI, EISA, MicroChannel 1134 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1135 newer boards don't support it. If you have ISA, say Y, otherwise N. 1136 1137# Select ISA DMA controller support 1138config ISA_DMA 1139 bool 1140 select ISA_DMA_API 1141 1142# Select ISA DMA interface 1143config ISA_DMA_API 1144 bool 1145 1146config PCI_NANOENGINE 1147 bool "BSE nanoEngine PCI support" 1148 depends on SA1100_NANOENGINE 1149 help 1150 Enable PCI on the BSE nanoEngine board. 1151 1152config ARM_ERRATA_814220 1153 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1154 depends on CPU_V7 1155 help 1156 The v7 ARM states that all cache and branch predictor maintenance 1157 operations that do not specify an address execute, relative to 1158 each other, in program order. 1159 However, because of this erratum, an L2 set/way cache maintenance 1160 operation can overtake an L1 set/way cache maintenance operation. 1161 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1162 r0p4, r0p5. 1163 1164endmenu 1165 1166menu "Kernel Features" 1167 1168config HAVE_SMP 1169 bool 1170 help 1171 This option should be selected by machines which have an SMP- 1172 capable CPU. 1173 1174 The only effect of this option is to make the SMP-related 1175 options available to the user for configuration. 1176 1177config SMP 1178 bool "Symmetric Multi-Processing" 1179 depends on CPU_V6K || CPU_V7 1180 depends on GENERIC_CLOCKEVENTS 1181 depends on HAVE_SMP 1182 depends on MMU || ARM_MPU 1183 select IRQ_WORK 1184 help 1185 This enables support for systems with more than one CPU. If you have 1186 a system with only one CPU, say N. If you have a system with more 1187 than one CPU, say Y. 1188 1189 If you say N here, the kernel will run on uni- and multiprocessor 1190 machines, but will use only one CPU of a multiprocessor machine. If 1191 you say Y here, the kernel will run on many, but not all, 1192 uniprocessor machines. On a uniprocessor machine, the kernel 1193 will run faster if you say N here. 1194 1195 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1196 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1197 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1198 1199 If you don't know what to do here, say N. 1200 1201config SMP_ON_UP 1202 bool "Allow booting SMP kernel on uniprocessor systems" 1203 depends on SMP && !XIP_KERNEL && MMU 1204 default y 1205 help 1206 SMP kernels contain instructions which fail on non-SMP processors. 1207 Enabling this option allows the kernel to modify itself to make 1208 these instructions safe. Disabling it allows about 1K of space 1209 savings. 1210 1211 If you don't know what to do here, say Y. 1212 1213config ARM_CPU_TOPOLOGY 1214 bool "Support cpu topology definition" 1215 depends on SMP && CPU_V7 1216 default y 1217 help 1218 Support ARM cpu topology definition. The MPIDR register defines 1219 affinity between processors which is then used to describe the cpu 1220 topology of an ARM System. 1221 1222config SCHED_MC 1223 bool "Multi-core scheduler support" 1224 depends on ARM_CPU_TOPOLOGY 1225 help 1226 Multi-core scheduler support improves the CPU scheduler's decision 1227 making when dealing with multi-core CPU chips at a cost of slightly 1228 increased overhead in some places. If unsure say N here. 1229 1230config SCHED_SMT 1231 bool "SMT scheduler support" 1232 depends on ARM_CPU_TOPOLOGY 1233 help 1234 Improves the CPU scheduler's decision making when dealing with 1235 MultiThreading at a cost of slightly increased overhead in some 1236 places. If unsure say N here. 1237 1238config HAVE_ARM_SCU 1239 bool 1240 help 1241 This option enables support for the ARM snoop control unit 1242 1243config HAVE_ARM_ARCH_TIMER 1244 bool "Architected timer support" 1245 depends on CPU_V7 1246 select ARM_ARCH_TIMER 1247 help 1248 This option enables support for the ARM architected timer 1249 1250config HAVE_ARM_TWD 1251 bool 1252 help 1253 This options enables support for the ARM timer and watchdog unit 1254 1255config MCPM 1256 bool "Multi-Cluster Power Management" 1257 depends on CPU_V7 && SMP 1258 help 1259 This option provides the common power management infrastructure 1260 for (multi-)cluster based systems, such as big.LITTLE based 1261 systems. 1262 1263config MCPM_QUAD_CLUSTER 1264 bool 1265 depends on MCPM 1266 help 1267 To avoid wasting resources unnecessarily, MCPM only supports up 1268 to 2 clusters by default. 1269 Platforms with 3 or 4 clusters that use MCPM must select this 1270 option to allow the additional clusters to be managed. 1271 1272config BIG_LITTLE 1273 bool "big.LITTLE support (Experimental)" 1274 depends on CPU_V7 && SMP 1275 select MCPM 1276 help 1277 This option enables support selections for the big.LITTLE 1278 system architecture. 1279 1280config BL_SWITCHER 1281 bool "big.LITTLE switcher support" 1282 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1283 select CPU_PM 1284 help 1285 The big.LITTLE "switcher" provides the core functionality to 1286 transparently handle transition between a cluster of A15's 1287 and a cluster of A7's in a big.LITTLE system. 1288 1289config BL_SWITCHER_DUMMY_IF 1290 tristate "Simple big.LITTLE switcher user interface" 1291 depends on BL_SWITCHER && DEBUG_KERNEL 1292 help 1293 This is a simple and dummy char dev interface to control 1294 the big.LITTLE switcher core code. It is meant for 1295 debugging purposes only. 1296 1297choice 1298 prompt "Memory split" 1299 depends on MMU 1300 default VMSPLIT_3G 1301 help 1302 Select the desired split between kernel and user memory. 1303 1304 If you are not absolutely sure what you are doing, leave this 1305 option alone! 1306 1307 config VMSPLIT_3G 1308 bool "3G/1G user/kernel split" 1309 config VMSPLIT_3G_OPT 1310 depends on !ARM_LPAE 1311 bool "3G/1G user/kernel split (for full 1G low memory)" 1312 config VMSPLIT_2G 1313 bool "2G/2G user/kernel split" 1314 config VMSPLIT_1G 1315 bool "1G/3G user/kernel split" 1316endchoice 1317 1318config PAGE_OFFSET 1319 hex 1320 default PHYS_OFFSET if !MMU 1321 default 0x40000000 if VMSPLIT_1G 1322 default 0x80000000 if VMSPLIT_2G 1323 default 0xB0000000 if VMSPLIT_3G_OPT 1324 default 0xC0000000 1325 1326config NR_CPUS 1327 int "Maximum number of CPUs (2-32)" 1328 range 2 32 1329 depends on SMP 1330 default "4" 1331 1332config HOTPLUG_CPU 1333 bool "Support for hot-pluggable CPUs" 1334 depends on SMP 1335 select GENERIC_IRQ_MIGRATION 1336 help 1337 Say Y here to experiment with turning CPUs off and on. CPUs 1338 can be controlled through /sys/devices/system/cpu. 1339 1340config ARM_PSCI 1341 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1342 depends on HAVE_ARM_SMCCC 1343 select ARM_PSCI_FW 1344 help 1345 Say Y here if you want Linux to communicate with system firmware 1346 implementing the PSCI specification for CPU-centric power 1347 management operations described in ARM document number ARM DEN 1348 0022A ("Power State Coordination Interface System Software on 1349 ARM processors"). 1350 1351# The GPIO number here must be sorted by descending number. In case of 1352# a multiplatform kernel, we just want the highest value required by the 1353# selected platforms. 1354config ARCH_NR_GPIO 1355 int 1356 default 2048 if ARCH_SOCFPGA 1357 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1358 ARCH_ZYNQ || ARCH_ASPEED 1359 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1360 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1361 default 416 if ARCH_SUNXI 1362 default 392 if ARCH_U8500 1363 default 352 if ARCH_VT8500 1364 default 288 if ARCH_ROCKCHIP 1365 default 264 if MACH_H4700 1366 default 0 1367 help 1368 Maximum number of GPIOs in the system. 1369 1370 If unsure, leave the default value. 1371 1372config HZ_FIXED 1373 int 1374 default 200 if ARCH_EBSA110 1375 default 128 if SOC_AT91RM9200 1376 default 0 1377 1378choice 1379 depends on HZ_FIXED = 0 1380 prompt "Timer frequency" 1381 1382config HZ_100 1383 bool "100 Hz" 1384 1385config HZ_200 1386 bool "200 Hz" 1387 1388config HZ_250 1389 bool "250 Hz" 1390 1391config HZ_300 1392 bool "300 Hz" 1393 1394config HZ_500 1395 bool "500 Hz" 1396 1397config HZ_1000 1398 bool "1000 Hz" 1399 1400endchoice 1401 1402config HZ 1403 int 1404 default HZ_FIXED if HZ_FIXED != 0 1405 default 100 if HZ_100 1406 default 200 if HZ_200 1407 default 250 if HZ_250 1408 default 300 if HZ_300 1409 default 500 if HZ_500 1410 default 1000 1411 1412config SCHED_HRTICK 1413 def_bool HIGH_RES_TIMERS 1414 1415config THUMB2_KERNEL 1416 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1417 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1418 default y if CPU_THUMBONLY 1419 select ARM_UNWIND 1420 help 1421 By enabling this option, the kernel will be compiled in 1422 Thumb-2 mode. 1423 1424 If unsure, say N. 1425 1426config ARM_PATCH_IDIV 1427 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1428 depends on CPU_32v7 && !XIP_KERNEL 1429 default y 1430 help 1431 The ARM compiler inserts calls to __aeabi_idiv() and 1432 __aeabi_uidiv() when it needs to perform division on signed 1433 and unsigned integers. Some v7 CPUs have support for the sdiv 1434 and udiv instructions that can be used to implement those 1435 functions. 1436 1437 Enabling this option allows the kernel to modify itself to 1438 replace the first two instructions of these library functions 1439 with the sdiv or udiv plus "bx lr" instructions when the CPU 1440 it is running on supports them. Typically this will be faster 1441 and less power intensive than running the original library 1442 code to do integer division. 1443 1444config AEABI 1445 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1446 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1447 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1448 help 1449 This option allows for the kernel to be compiled using the latest 1450 ARM ABI (aka EABI). This is only useful if you are using a user 1451 space environment that is also compiled with EABI. 1452 1453 Since there are major incompatibilities between the legacy ABI and 1454 EABI, especially with regard to structure member alignment, this 1455 option also changes the kernel syscall calling convention to 1456 disambiguate both ABIs and allow for backward compatibility support 1457 (selected with CONFIG_OABI_COMPAT). 1458 1459 To use this you need GCC version 4.0.0 or later. 1460 1461config OABI_COMPAT 1462 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1463 depends on AEABI && !THUMB2_KERNEL 1464 help 1465 This option preserves the old syscall interface along with the 1466 new (ARM EABI) one. It also provides a compatibility layer to 1467 intercept syscalls that have structure arguments which layout 1468 in memory differs between the legacy ABI and the new ARM EABI 1469 (only for non "thumb" binaries). This option adds a tiny 1470 overhead to all syscalls and produces a slightly larger kernel. 1471 1472 The seccomp filter system will not be available when this is 1473 selected, since there is no way yet to sensibly distinguish 1474 between calling conventions during filtering. 1475 1476 If you know you'll be using only pure EABI user space then you 1477 can say N here. If this option is not selected and you attempt 1478 to execute a legacy ABI binary then the result will be 1479 UNPREDICTABLE (in fact it can be predicted that it won't work 1480 at all). If in doubt say N. 1481 1482config ARCH_HAS_HOLES_MEMORYMODEL 1483 bool 1484 1485config ARCH_SELECT_MEMORY_MODEL 1486 bool 1487 1488config ARCH_FLATMEM_ENABLE 1489 bool 1490 1491config ARCH_SPARSEMEM_ENABLE 1492 bool 1493 select SPARSEMEM_STATIC if SPARSEMEM 1494 1495config HAVE_ARCH_PFN_VALID 1496 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1497 1498config HIGHMEM 1499 bool "High Memory Support" 1500 depends on MMU 1501 help 1502 The address space of ARM processors is only 4 Gigabytes large 1503 and it has to accommodate user address space, kernel address 1504 space as well as some memory mapped IO. That means that, if you 1505 have a large amount of physical memory and/or IO, not all of the 1506 memory can be "permanently mapped" by the kernel. The physical 1507 memory that is not permanently mapped is called "high memory". 1508 1509 Depending on the selected kernel/user memory split, minimum 1510 vmalloc space and actual amount of RAM, you may not need this 1511 option which should result in a slightly faster kernel. 1512 1513 If unsure, say n. 1514 1515config HIGHPTE 1516 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1517 depends on HIGHMEM 1518 default y 1519 help 1520 The VM uses one page of physical memory for each page table. 1521 For systems with a lot of processes, this can use a lot of 1522 precious low memory, eventually leading to low memory being 1523 consumed by page tables. Setting this option will allow 1524 user-space 2nd level page tables to reside in high memory. 1525 1526config CPU_SW_DOMAIN_PAN 1527 bool "Enable use of CPU domains to implement privileged no-access" 1528 depends on MMU && !ARM_LPAE 1529 default y 1530 help 1531 Increase kernel security by ensuring that normal kernel accesses 1532 are unable to access userspace addresses. This can help prevent 1533 use-after-free bugs becoming an exploitable privilege escalation 1534 by ensuring that magic values (such as LIST_POISON) will always 1535 fault when dereferenced. 1536 1537 CPUs with low-vector mappings use a best-efforts implementation. 1538 Their lower 1MB needs to remain accessible for the vectors, but 1539 the remainder of userspace will become appropriately inaccessible. 1540 1541config HW_PERF_EVENTS 1542 def_bool y 1543 depends on ARM_PMU 1544 1545config SYS_SUPPORTS_HUGETLBFS 1546 def_bool y 1547 depends on ARM_LPAE 1548 1549config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1550 def_bool y 1551 depends on ARM_LPAE 1552 1553config ARCH_WANT_GENERAL_HUGETLB 1554 def_bool y 1555 1556config ARM_MODULE_PLTS 1557 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1558 depends on MODULES 1559 default y 1560 help 1561 Allocate PLTs when loading modules so that jumps and calls whose 1562 targets are too far away for their relative offsets to be encoded 1563 in the instructions themselves can be bounced via veneers in the 1564 module's PLT. This allows modules to be allocated in the generic 1565 vmalloc area after the dedicated module memory area has been 1566 exhausted. The modules will use slightly more memory, but after 1567 rounding up to page size, the actual memory footprint is usually 1568 the same. 1569 1570 Disabling this is usually safe for small single-platform 1571 configurations. If unsure, say y. 1572 1573config FORCE_MAX_ZONEORDER 1574 int "Maximum zone order" 1575 default "12" if SOC_AM33XX 1576 default "9" if SA1111 || ARCH_EFM32 1577 default "11" 1578 help 1579 The kernel memory allocator divides physically contiguous memory 1580 blocks into "zones", where each zone is a power of two number of 1581 pages. This option selects the largest power of two that the kernel 1582 keeps in the memory allocator. If you need to allocate very large 1583 blocks of physically contiguous memory, then you may need to 1584 increase this value. 1585 1586 This config option is actually maximum order plus one. For example, 1587 a value of 11 means that the largest free memory block is 2^10 pages. 1588 1589config ALIGNMENT_TRAP 1590 bool 1591 depends on CPU_CP15_MMU 1592 default y if !ARCH_EBSA110 1593 select HAVE_PROC_CPU if PROC_FS 1594 help 1595 ARM processors cannot fetch/store information which is not 1596 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1597 address divisible by 4. On 32-bit ARM processors, these non-aligned 1598 fetch/store instructions will be emulated in software if you say 1599 here, which has a severe performance impact. This is necessary for 1600 correct operation of some network protocols. With an IP-only 1601 configuration it is safe to say N, otherwise say Y. 1602 1603config UACCESS_WITH_MEMCPY 1604 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1605 depends on MMU 1606 default y if CPU_FEROCEON 1607 help 1608 Implement faster copy_to_user and clear_user methods for CPU 1609 cores where a 8-word STM instruction give significantly higher 1610 memory write throughput than a sequence of individual 32bit stores. 1611 1612 A possible side effect is a slight increase in scheduling latency 1613 between threads sharing the same address space if they invoke 1614 such copy operations with large buffers. 1615 1616 However, if the CPU data cache is using a write-allocate mode, 1617 this option is unlikely to provide any performance gain. 1618 1619config PARAVIRT 1620 bool "Enable paravirtualization code" 1621 help 1622 This changes the kernel so it can modify itself when it is run 1623 under a hypervisor, potentially improving performance significantly 1624 over full virtualization. 1625 1626config PARAVIRT_TIME_ACCOUNTING 1627 bool "Paravirtual steal time accounting" 1628 select PARAVIRT 1629 help 1630 Select this option to enable fine granularity task steal time 1631 accounting. Time spent executing other tasks in parallel with 1632 the current vCPU is discounted from the vCPU power. To account for 1633 that, there can be a small performance impact. 1634 1635 If in doubt, say N here. 1636 1637config XEN_DOM0 1638 def_bool y 1639 depends on XEN 1640 1641config XEN 1642 bool "Xen guest support on ARM" 1643 depends on ARM && AEABI && OF 1644 depends on CPU_V7 && !CPU_V6 1645 depends on !GENERIC_ATOMIC64 1646 depends on MMU 1647 select ARCH_DMA_ADDR_T_64BIT 1648 select ARM_PSCI 1649 select SWIOTLB 1650 select SWIOTLB_XEN 1651 select PARAVIRT 1652 help 1653 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1654 1655config STACKPROTECTOR_PER_TASK 1656 bool "Use a unique stack canary value for each task" 1657 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1658 select GCC_PLUGIN_ARM_SSP_PER_TASK 1659 default y 1660 help 1661 Due to the fact that GCC uses an ordinary symbol reference from 1662 which to load the value of the stack canary, this value can only 1663 change at reboot time on SMP systems, and all tasks running in the 1664 kernel's address space are forced to use the same canary value for 1665 the entire duration that the system is up. 1666 1667 Enable this option to switch to a different method that uses a 1668 different canary value for each task. 1669 1670endmenu 1671 1672menu "Boot options" 1673 1674config USE_OF 1675 bool "Flattened Device Tree support" 1676 select IRQ_DOMAIN 1677 select OF 1678 help 1679 Include support for flattened device tree machine descriptions. 1680 1681config ATAGS 1682 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1683 default y 1684 help 1685 This is the traditional way of passing data to the kernel at boot 1686 time. If you are solely relying on the flattened device tree (or 1687 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1688 to remove ATAGS support from your kernel binary. If unsure, 1689 leave this to y. 1690 1691config DEPRECATED_PARAM_STRUCT 1692 bool "Provide old way to pass kernel parameters" 1693 depends on ATAGS 1694 help 1695 This was deprecated in 2001 and announced to live on for 5 years. 1696 Some old boot loaders still use this way. 1697 1698# Compressed boot loader in ROM. Yes, we really want to ask about 1699# TEXT and BSS so we preserve their values in the config files. 1700config ZBOOT_ROM_TEXT 1701 hex "Compressed ROM boot loader base address" 1702 default 0x0 1703 help 1704 The physical address at which the ROM-able zImage is to be 1705 placed in the target. Platforms which normally make use of 1706 ROM-able zImage formats normally set this to a suitable 1707 value in their defconfig file. 1708 1709 If ZBOOT_ROM is not enabled, this has no effect. 1710 1711config ZBOOT_ROM_BSS 1712 hex "Compressed ROM boot loader BSS address" 1713 default 0x0 1714 help 1715 The base address of an area of read/write memory in the target 1716 for the ROM-able zImage which must be available while the 1717 decompressor is running. It must be large enough to hold the 1718 entire decompressed kernel plus an additional 128 KiB. 1719 Platforms which normally make use of ROM-able zImage formats 1720 normally set this to a suitable value in their defconfig file. 1721 1722 If ZBOOT_ROM is not enabled, this has no effect. 1723 1724config ZBOOT_ROM 1725 bool "Compressed boot loader in ROM/flash" 1726 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1727 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1728 help 1729 Say Y here if you intend to execute your compressed kernel image 1730 (zImage) directly from ROM or flash. If unsure, say N. 1731 1732config ARM_APPENDED_DTB 1733 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1734 depends on OF 1735 help 1736 With this option, the boot code will look for a device tree binary 1737 (DTB) appended to zImage 1738 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1739 1740 This is meant as a backward compatibility convenience for those 1741 systems with a bootloader that can't be upgraded to accommodate 1742 the documented boot protocol using a device tree. 1743 1744 Beware that there is very little in terms of protection against 1745 this option being confused by leftover garbage in memory that might 1746 look like a DTB header after a reboot if no actual DTB is appended 1747 to zImage. Do not leave this option active in a production kernel 1748 if you don't intend to always append a DTB. Proper passing of the 1749 location into r2 of a bootloader provided DTB is always preferable 1750 to this option. 1751 1752config ARM_ATAG_DTB_COMPAT 1753 bool "Supplement the appended DTB with traditional ATAG information" 1754 depends on ARM_APPENDED_DTB 1755 help 1756 Some old bootloaders can't be updated to a DTB capable one, yet 1757 they provide ATAGs with memory configuration, the ramdisk address, 1758 the kernel cmdline string, etc. Such information is dynamically 1759 provided by the bootloader and can't always be stored in a static 1760 DTB. To allow a device tree enabled kernel to be used with such 1761 bootloaders, this option allows zImage to extract the information 1762 from the ATAG list and store it at run time into the appended DTB. 1763 1764choice 1765 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1766 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1767 1768config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1769 bool "Use bootloader kernel arguments if available" 1770 help 1771 Uses the command-line options passed by the boot loader instead of 1772 the device tree bootargs property. If the boot loader doesn't provide 1773 any, the device tree bootargs property will be used. 1774 1775config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1776 bool "Extend with bootloader kernel arguments" 1777 help 1778 The command-line arguments provided by the boot loader will be 1779 appended to the the device tree bootargs property. 1780 1781endchoice 1782 1783config CMDLINE 1784 string "Default kernel command string" 1785 default "" 1786 help 1787 On some architectures (EBSA110 and CATS), there is currently no way 1788 for the boot loader to pass arguments to the kernel. For these 1789 architectures, you should supply some command-line options at build 1790 time by entering them here. As a minimum, you should specify the 1791 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1792 1793choice 1794 prompt "Kernel command line type" if CMDLINE != "" 1795 default CMDLINE_FROM_BOOTLOADER 1796 depends on ATAGS 1797 1798config CMDLINE_FROM_BOOTLOADER 1799 bool "Use bootloader kernel arguments if available" 1800 help 1801 Uses the command-line options passed by the boot loader. If 1802 the boot loader doesn't provide any, the default kernel command 1803 string provided in CMDLINE will be used. 1804 1805config CMDLINE_EXTEND 1806 bool "Extend bootloader kernel arguments" 1807 help 1808 The command-line arguments provided by the boot loader will be 1809 appended to the default kernel command string. 1810 1811config CMDLINE_FORCE 1812 bool "Always use the default kernel command string" 1813 help 1814 Always use the default kernel command string, even if the boot 1815 loader passes other arguments to the kernel. 1816 This is useful if you cannot or don't want to change the 1817 command-line options your boot loader passes to the kernel. 1818endchoice 1819 1820config XIP_KERNEL 1821 bool "Kernel Execute-In-Place from ROM" 1822 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1823 help 1824 Execute-In-Place allows the kernel to run from non-volatile storage 1825 directly addressable by the CPU, such as NOR flash. This saves RAM 1826 space since the text section of the kernel is not loaded from flash 1827 to RAM. Read-write sections, such as the data section and stack, 1828 are still copied to RAM. The XIP kernel is not compressed since 1829 it has to run directly from flash, so it will take more space to 1830 store it. The flash address used to link the kernel object files, 1831 and for storing it, is configuration dependent. Therefore, if you 1832 say Y here, you must know the proper physical address where to 1833 store the kernel image depending on your own flash memory usage. 1834 1835 Also note that the make target becomes "make xipImage" rather than 1836 "make zImage" or "make Image". The final kernel binary to put in 1837 ROM memory will be arch/arm/boot/xipImage. 1838 1839 If unsure, say N. 1840 1841config XIP_PHYS_ADDR 1842 hex "XIP Kernel Physical Location" 1843 depends on XIP_KERNEL 1844 default "0x00080000" 1845 help 1846 This is the physical address in your flash memory the kernel will 1847 be linked for and stored to. This address is dependent on your 1848 own flash usage. 1849 1850config XIP_DEFLATED_DATA 1851 bool "Store kernel .data section compressed in ROM" 1852 depends on XIP_KERNEL 1853 select ZLIB_INFLATE 1854 help 1855 Before the kernel is actually executed, its .data section has to be 1856 copied to RAM from ROM. This option allows for storing that data 1857 in compressed form and decompressed to RAM rather than merely being 1858 copied, saving some precious ROM space. A possible drawback is a 1859 slightly longer boot delay. 1860 1861config KEXEC 1862 bool "Kexec system call (EXPERIMENTAL)" 1863 depends on (!SMP || PM_SLEEP_SMP) 1864 depends on MMU 1865 select KEXEC_CORE 1866 help 1867 kexec is a system call that implements the ability to shutdown your 1868 current kernel, and to start another kernel. It is like a reboot 1869 but it is independent of the system firmware. And like a reboot 1870 you can start any kernel with it, not just Linux. 1871 1872 It is an ongoing process to be certain the hardware in a machine 1873 is properly shutdown, so do not be surprised if this code does not 1874 initially work for you. 1875 1876config ATAGS_PROC 1877 bool "Export atags in procfs" 1878 depends on ATAGS && KEXEC 1879 default y 1880 help 1881 Should the atags used to boot the kernel be exported in an "atags" 1882 file in procfs. Useful with kexec. 1883 1884config CRASH_DUMP 1885 bool "Build kdump crash kernel (EXPERIMENTAL)" 1886 help 1887 Generate crash dump after being started by kexec. This should 1888 be normally only set in special crash dump kernels which are 1889 loaded in the main kernel with kexec-tools into a specially 1890 reserved region and then later executed after a crash by 1891 kdump/kexec. The crash dump kernel must be compiled to a 1892 memory address not used by the main kernel 1893 1894 For more details see Documentation/admin-guide/kdump/kdump.rst 1895 1896config AUTO_ZRELADDR 1897 bool "Auto calculation of the decompressed kernel image address" 1898 help 1899 ZRELADDR is the physical address where the decompressed kernel 1900 image will be placed. If AUTO_ZRELADDR is selected, the address 1901 will be determined at run-time by masking the current IP with 1902 0xf8000000. This assumes the zImage being placed in the first 128MB 1903 from start of memory. 1904 1905config EFI_STUB 1906 bool 1907 1908config EFI 1909 bool "UEFI runtime support" 1910 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1911 select UCS2_STRING 1912 select EFI_PARAMS_FROM_FDT 1913 select EFI_STUB 1914 select EFI_GENERIC_STUB 1915 select EFI_RUNTIME_WRAPPERS 1916 help 1917 This option provides support for runtime services provided 1918 by UEFI firmware (such as non-volatile variables, realtime 1919 clock, and platform reset). A UEFI stub is also provided to 1920 allow the kernel to be booted as an EFI application. This 1921 is only useful for kernels that may run on systems that have 1922 UEFI firmware. 1923 1924config DMI 1925 bool "Enable support for SMBIOS (DMI) tables" 1926 depends on EFI 1927 default y 1928 help 1929 This enables SMBIOS/DMI feature for systems. 1930 1931 This option is only useful on systems that have UEFI firmware. 1932 However, even with this option, the resultant kernel should 1933 continue to boot on existing non-UEFI platforms. 1934 1935 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1936 i.e., the the practice of identifying the platform via DMI to 1937 decide whether certain workarounds for buggy hardware and/or 1938 firmware need to be enabled. This would require the DMI subsystem 1939 to be enabled much earlier than we do on ARM, which is non-trivial. 1940 1941endmenu 1942 1943menu "CPU Power Management" 1944 1945source "drivers/cpufreq/Kconfig" 1946 1947source "drivers/cpuidle/Kconfig" 1948 1949endmenu 1950 1951menu "Floating point emulation" 1952 1953comment "At least one emulation must be selected" 1954 1955config FPE_NWFPE 1956 bool "NWFPE math emulation" 1957 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1958 help 1959 Say Y to include the NWFPE floating point emulator in the kernel. 1960 This is necessary to run most binaries. Linux does not currently 1961 support floating point hardware so you need to say Y here even if 1962 your machine has an FPA or floating point co-processor podule. 1963 1964 You may say N here if you are going to load the Acorn FPEmulator 1965 early in the bootup. 1966 1967config FPE_NWFPE_XP 1968 bool "Support extended precision" 1969 depends on FPE_NWFPE 1970 help 1971 Say Y to include 80-bit support in the kernel floating-point 1972 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1973 Note that gcc does not generate 80-bit operations by default, 1974 so in most cases this option only enlarges the size of the 1975 floating point emulator without any good reason. 1976 1977 You almost surely want to say N here. 1978 1979config FPE_FASTFPE 1980 bool "FastFPE math emulation (EXPERIMENTAL)" 1981 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1982 help 1983 Say Y here to include the FAST floating point emulator in the kernel. 1984 This is an experimental much faster emulator which now also has full 1985 precision for the mantissa. It does not support any exceptions. 1986 It is very simple, and approximately 3-6 times faster than NWFPE. 1987 1988 It should be sufficient for most programs. It may be not suitable 1989 for scientific calculations, but you have to check this for yourself. 1990 If you do not feel you need a faster FP emulation you should better 1991 choose NWFPE. 1992 1993config VFP 1994 bool "VFP-format floating point maths" 1995 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1996 help 1997 Say Y to include VFP support code in the kernel. This is needed 1998 if your hardware includes a VFP unit. 1999 2000 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2001 release notes and additional status information. 2002 2003 Say N if your target does not have VFP hardware. 2004 2005config VFPv3 2006 bool 2007 depends on VFP 2008 default y if CPU_V7 2009 2010config NEON 2011 bool "Advanced SIMD (NEON) Extension support" 2012 depends on VFPv3 && CPU_V7 2013 help 2014 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2015 Extension. 2016 2017config KERNEL_MODE_NEON 2018 bool "Support for NEON in kernel mode" 2019 depends on NEON && AEABI 2020 help 2021 Say Y to include support for NEON in kernel mode. 2022 2023endmenu 2024 2025menu "Power management options" 2026 2027source "kernel/power/Kconfig" 2028 2029config ARCH_SUSPEND_POSSIBLE 2030 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2031 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2032 def_bool y 2033 2034config ARM_CPU_SUSPEND 2035 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2036 depends on ARCH_SUSPEND_POSSIBLE 2037 2038config ARCH_HIBERNATION_POSSIBLE 2039 bool 2040 depends on MMU 2041 default y if ARCH_SUSPEND_POSSIBLE 2042 2043endmenu 2044 2045source "drivers/firmware/Kconfig" 2046 2047if CRYPTO 2048source "arch/arm/crypto/Kconfig" 2049endif 2050 2051source "arch/arm/Kconfig.assembler" 2052