1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CLOCKSOURCE_DATA 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_DEBUG_VIRTUAL if MMU 9 select ARCH_HAS_DEVMEM_IS_ALLOWED 10 select ARCH_HAS_DMA_COHERENT_TO_PFN if SWIOTLB 11 select ARCH_HAS_DMA_MMAP_PGPROT if SWIOTLB 12 select ARCH_HAS_ELF_RANDOMIZE 13 select ARCH_HAS_FORTIFY_SOURCE 14 select ARCH_HAS_KEEPINITRD 15 select ARCH_HAS_KCOV 16 select ARCH_HAS_MEMBARRIER_SYNC_CORE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_PHYS_TO_DMA 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAS_GCOV_PROFILE_ALL 29 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 30 select ARCH_MIGHT_HAVE_PC_PARPORT 31 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 32 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 33 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 34 select ARCH_SUPPORTS_ATOMIC_RMW 35 select ARCH_USE_BUILTIN_BSWAP 36 select ARCH_USE_CMPXCHG_LOCKREF 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 39 select BUILDTIME_EXTABLE_SORT if MMU 40 select CLONE_BACKWARDS 41 select CPU_PM if SUSPEND || CPU_IDLE 42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 43 select DMA_DECLARE_COHERENT 44 select DMA_REMAP if MMU 45 select EDAC_SUPPORT 46 select EDAC_ATOMIC_SCRUB 47 select GENERIC_ALLOCATOR 48 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 49 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 50 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 51 select GENERIC_CPU_AUTOPROBE 52 select GENERIC_EARLY_IOREMAP 53 select GENERIC_IDLE_POLL_SETUP 54 select GENERIC_IRQ_PROBE 55 select GENERIC_IRQ_SHOW 56 select GENERIC_IRQ_SHOW_LEVEL 57 select GENERIC_PCI_IOMAP 58 select GENERIC_SCHED_CLOCK 59 select GENERIC_SMP_IDLE_THREAD 60 select GENERIC_STRNCPY_FROM_USER 61 select GENERIC_STRNLEN_USER 62 select HANDLE_DOMAIN_IRQ 63 select HARDIRQS_SW_RESEND 64 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 65 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 66 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 67 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 68 select HAVE_ARCH_MMAP_RND_BITS if MMU 69 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 70 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 71 select HAVE_ARCH_TRACEHOOK 72 select HAVE_ARM_SMCCC if CPU_V7 73 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 74 select HAVE_CONTEXT_TRACKING 75 select HAVE_C_RECORDMCOUNT 76 select HAVE_DEBUG_KMEMLEAK 77 select HAVE_DMA_CONTIGUOUS if MMU 78 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 79 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 80 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 81 select HAVE_EXIT_THREAD 82 select HAVE_FAST_GUP if ARM_LPAE 83 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 84 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 85 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 86 select HAVE_GCC_PLUGINS 87 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 88 select HAVE_IDE if PCI || ISA || PCMCIA 89 select HAVE_IRQ_TIME_ACCOUNTING 90 select HAVE_KERNEL_GZIP 91 select HAVE_KERNEL_LZ4 92 select HAVE_KERNEL_LZMA 93 select HAVE_KERNEL_LZO 94 select HAVE_KERNEL_XZ 95 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 96 select HAVE_KRETPROBES if HAVE_KPROBES 97 select HAVE_MOD_ARCH_SPECIFIC 98 select HAVE_NMI 99 select HAVE_OPROFILE if HAVE_PERF_EVENTS 100 select HAVE_OPTPROBES if !THUMB2_KERNEL 101 select HAVE_PERF_EVENTS 102 select HAVE_PERF_REGS 103 select HAVE_PERF_USER_STACK_DUMP 104 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE 105 select HAVE_REGS_AND_STACK_ACCESS_API 106 select HAVE_RSEQ 107 select HAVE_STACKPROTECTOR 108 select HAVE_SYSCALL_TRACEPOINTS 109 select HAVE_UID16 110 select HAVE_VIRT_CPU_ACCOUNTING_GEN 111 select IRQ_FORCED_THREADING 112 select MODULES_USE_ELF_REL 113 select NEED_DMA_MAP_STATE 114 select OF_EARLY_FLATTREE if OF 115 select OLD_SIGACTION 116 select OLD_SIGSUSPEND3 117 select PCI_SYSCALL if PCI 118 select PERF_USE_VMALLOC 119 select REFCOUNT_FULL 120 select RTC_LIB 121 select SYS_SUPPORTS_APM_EMULATION 122 # Above selects are sorted alphabetically; please add new ones 123 # according to that. Thanks. 124 help 125 The ARM series is a line of low-power-consumption RISC chip designs 126 licensed by ARM Ltd and targeted at embedded applications and 127 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 128 manufactured, but legacy ARM-based PC hardware remains popular in 129 Europe. There is an ARM Linux project with a web page at 130 <http://www.arm.linux.org.uk/>. 131 132config ARM_HAS_SG_CHAIN 133 bool 134 135config ARM_DMA_USE_IOMMU 136 bool 137 select ARM_HAS_SG_CHAIN 138 select NEED_SG_DMA_LENGTH 139 140if ARM_DMA_USE_IOMMU 141 142config ARM_DMA_IOMMU_ALIGNMENT 143 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 144 range 4 9 145 default 8 146 help 147 DMA mapping framework by default aligns all buffers to the smallest 148 PAGE_SIZE order which is greater than or equal to the requested buffer 149 size. This works well for buffers up to a few hundreds kilobytes, but 150 for larger buffers it just a waste of address space. Drivers which has 151 relatively small addressing window (like 64Mib) might run out of 152 virtual space with just a few allocations. 153 154 With this parameter you can specify the maximum PAGE_SIZE order for 155 DMA IOMMU buffers. Larger buffers will be aligned only to this 156 specified order. The order is expressed as a power of two multiplied 157 by the PAGE_SIZE. 158 159endif 160 161config SYS_SUPPORTS_APM_EMULATION 162 bool 163 164config HAVE_TCM 165 bool 166 select GENERIC_ALLOCATOR 167 168config HAVE_PROC_CPU 169 bool 170 171config NO_IOPORT_MAP 172 bool 173 174config SBUS 175 bool 176 177config STACKTRACE_SUPPORT 178 bool 179 default y 180 181config LOCKDEP_SUPPORT 182 bool 183 default y 184 185config TRACE_IRQFLAGS_SUPPORT 186 bool 187 default !CPU_V7M 188 189config ARCH_HAS_ILOG2_U32 190 bool 191 192config ARCH_HAS_ILOG2_U64 193 bool 194 195config ARCH_HAS_BANDGAP 196 bool 197 198config FIX_EARLYCON_MEM 199 def_bool y if MMU 200 201config GENERIC_HWEIGHT 202 bool 203 default y 204 205config GENERIC_CALIBRATE_DELAY 206 bool 207 default y 208 209config ARCH_MAY_HAVE_PC_FDC 210 bool 211 212config ZONE_DMA 213 bool 214 215config ARCH_SUPPORTS_UPROBES 216 def_bool y 217 218config ARCH_HAS_DMA_SET_COHERENT_MASK 219 bool 220 221config GENERIC_ISA_DMA 222 bool 223 224config FIQ 225 bool 226 227config NEED_RET_TO_USER 228 bool 229 230config ARCH_MTD_XIP 231 bool 232 233config ARM_PATCH_PHYS_VIRT 234 bool "Patch physical to virtual translations at runtime" if EMBEDDED 235 default y 236 depends on !XIP_KERNEL && MMU 237 help 238 Patch phys-to-virt and virt-to-phys translation functions at 239 boot and module load time according to the position of the 240 kernel in system memory. 241 242 This can only be used with non-XIP MMU kernels where the base 243 of physical memory is at a 16MB boundary. 244 245 Only disable this option if you know that you do not require 246 this feature (eg, building a kernel for a single machine) and 247 you need to shrink the kernel to the minimal size. 248 249config NEED_MACH_IO_H 250 bool 251 help 252 Select this when mach/io.h is required to provide special 253 definitions for this platform. The need for mach/io.h should 254 be avoided when possible. 255 256config NEED_MACH_MEMORY_H 257 bool 258 help 259 Select this when mach/memory.h is required to provide special 260 definitions for this platform. The need for mach/memory.h should 261 be avoided when possible. 262 263config PHYS_OFFSET 264 hex "Physical address of main memory" if MMU 265 depends on !ARM_PATCH_PHYS_VIRT 266 default DRAM_BASE if !MMU 267 default 0x00000000 if ARCH_EBSA110 || \ 268 ARCH_FOOTBRIDGE || \ 269 ARCH_INTEGRATOR || \ 270 ARCH_IOP13XX || \ 271 ARCH_KS8695 || \ 272 ARCH_REALVIEW 273 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 274 default 0x20000000 if ARCH_S5PV210 275 default 0xc0000000 if ARCH_SA1100 276 help 277 Please provide the physical address corresponding to the 278 location of main memory in your system. 279 280config GENERIC_BUG 281 def_bool y 282 depends on BUG 283 284config PGTABLE_LEVELS 285 int 286 default 3 if ARM_LPAE 287 default 2 288 289menu "System Type" 290 291config MMU 292 bool "MMU-based Paged Memory Management Support" 293 default y 294 help 295 Select if you want MMU-based virtualised addressing space 296 support by paged memory management. If unsure, say 'Y'. 297 298config ARCH_MMAP_RND_BITS_MIN 299 default 8 300 301config ARCH_MMAP_RND_BITS_MAX 302 default 14 if PAGE_OFFSET=0x40000000 303 default 15 if PAGE_OFFSET=0x80000000 304 default 16 305 306# 307# The "ARM system type" choice list is ordered alphabetically by option 308# text. Please add new entries in the option alphabetic order. 309# 310choice 311 prompt "ARM system type" 312 default ARM_SINGLE_ARMV7M if !MMU 313 default ARCH_MULTIPLATFORM if MMU 314 315config ARCH_MULTIPLATFORM 316 bool "Allow multiple platforms to be selected" 317 depends on MMU 318 select ARM_HAS_SG_CHAIN 319 select ARM_PATCH_PHYS_VIRT 320 select AUTO_ZRELADDR 321 select TIMER_OF 322 select COMMON_CLK 323 select GENERIC_CLOCKEVENTS 324 select GENERIC_IRQ_MULTI_HANDLER 325 select HAVE_PCI 326 select PCI_DOMAINS_GENERIC if PCI 327 select SPARSE_IRQ 328 select USE_OF 329 330config ARM_SINGLE_ARMV7M 331 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 332 depends on !MMU 333 select ARM_NVIC 334 select AUTO_ZRELADDR 335 select TIMER_OF 336 select COMMON_CLK 337 select CPU_V7M 338 select GENERIC_CLOCKEVENTS 339 select NO_IOPORT_MAP 340 select SPARSE_IRQ 341 select USE_OF 342 343config ARCH_EBSA110 344 bool "EBSA-110" 345 select ARCH_USES_GETTIMEOFFSET 346 select CPU_SA110 347 select ISA 348 select NEED_MACH_IO_H 349 select NEED_MACH_MEMORY_H 350 select NO_IOPORT_MAP 351 help 352 This is an evaluation board for the StrongARM processor available 353 from Digital. It has limited hardware on-board, including an 354 Ethernet interface, two PCMCIA sockets, two serial ports and a 355 parallel port. 356 357config ARCH_EP93XX 358 bool "EP93xx-based" 359 select ARCH_SPARSEMEM_ENABLE 360 select ARM_AMBA 361 imply ARM_PATCH_PHYS_VIRT 362 select ARM_VIC 363 select AUTO_ZRELADDR 364 select CLKDEV_LOOKUP 365 select CLKSRC_MMIO 366 select CPU_ARM920T 367 select GENERIC_CLOCKEVENTS 368 select GPIOLIB 369 help 370 This enables support for the Cirrus EP93xx series of CPUs. 371 372config ARCH_FOOTBRIDGE 373 bool "FootBridge" 374 select CPU_SA110 375 select FOOTBRIDGE 376 select GENERIC_CLOCKEVENTS 377 select HAVE_IDE 378 select NEED_MACH_IO_H if !MMU 379 select NEED_MACH_MEMORY_H 380 help 381 Support for systems based on the DC21285 companion chip 382 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 383 384config ARCH_IOP13XX 385 bool "IOP13xx-based" 386 depends on MMU 387 select CPU_XSC3 388 select NEED_MACH_MEMORY_H 389 select NEED_RET_TO_USER 390 select FORCE_PCI 391 select PLAT_IOP 392 select VMSPLIT_1G 393 select SPARSE_IRQ 394 help 395 Support for Intel's IOP13XX (XScale) family of processors. 396 397config ARCH_IOP32X 398 bool "IOP32x-based" 399 depends on MMU 400 select CPU_XSCALE 401 select GPIO_IOP 402 select GPIOLIB 403 select NEED_RET_TO_USER 404 select FORCE_PCI 405 select PLAT_IOP 406 help 407 Support for Intel's 80219 and IOP32X (XScale) family of 408 processors. 409 410config ARCH_IOP33X 411 bool "IOP33x-based" 412 depends on MMU 413 select CPU_XSCALE 414 select GPIO_IOP 415 select GPIOLIB 416 select NEED_RET_TO_USER 417 select FORCE_PCI 418 select PLAT_IOP 419 help 420 Support for Intel's IOP33X (XScale) family of processors. 421 422config ARCH_IXP4XX 423 bool "IXP4xx-based" 424 depends on MMU 425 select ARCH_HAS_DMA_SET_COHERENT_MASK 426 select ARCH_SUPPORTS_BIG_ENDIAN 427 select CPU_XSCALE 428 select DMABOUNCE if PCI 429 select GENERIC_CLOCKEVENTS 430 select GENERIC_IRQ_MULTI_HANDLER 431 select GPIO_IXP4XX 432 select GPIOLIB 433 select HAVE_PCI 434 select IXP4XX_IRQ 435 select IXP4XX_TIMER 436 select NEED_MACH_IO_H 437 select USB_EHCI_BIG_ENDIAN_DESC 438 select USB_EHCI_BIG_ENDIAN_MMIO 439 help 440 Support for Intel's IXP4XX (XScale) family of processors. 441 442config ARCH_DOVE 443 bool "Marvell Dove" 444 select CPU_PJ4 445 select GENERIC_CLOCKEVENTS 446 select GENERIC_IRQ_MULTI_HANDLER 447 select GPIOLIB 448 select HAVE_PCI 449 select MVEBU_MBUS 450 select PINCTRL 451 select PINCTRL_DOVE 452 select PLAT_ORION_LEGACY 453 select SPARSE_IRQ 454 select PM_GENERIC_DOMAINS if PM 455 help 456 Support for the Marvell Dove SoC 88AP510 457 458config ARCH_KS8695 459 bool "Micrel/Kendin KS8695" 460 select CLKSRC_MMIO 461 select CPU_ARM922T 462 select GENERIC_CLOCKEVENTS 463 select GPIOLIB 464 select NEED_MACH_MEMORY_H 465 help 466 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 467 System-on-Chip devices. 468 469config ARCH_W90X900 470 bool "Nuvoton W90X900 CPU" 471 select CLKDEV_LOOKUP 472 select CLKSRC_MMIO 473 select CPU_ARM926T 474 select GENERIC_CLOCKEVENTS 475 select GPIOLIB 476 help 477 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 478 At present, the w90x900 has been renamed nuc900, regarding 479 the ARM series product line, you can login the following 480 link address to know more. 481 482 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 483 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 484 485config ARCH_LPC32XX 486 bool "NXP LPC32XX" 487 select ARM_AMBA 488 select CLKDEV_LOOKUP 489 select CLKSRC_LPC32XX 490 select COMMON_CLK 491 select CPU_ARM926T 492 select GENERIC_CLOCKEVENTS 493 select GENERIC_IRQ_MULTI_HANDLER 494 select GPIOLIB 495 select SPARSE_IRQ 496 select USE_OF 497 help 498 Support for the NXP LPC32XX family of processors 499 500config ARCH_PXA 501 bool "PXA2xx/PXA3xx-based" 502 depends on MMU 503 select ARCH_MTD_XIP 504 select ARM_CPU_SUSPEND if PM 505 select AUTO_ZRELADDR 506 select COMMON_CLK 507 select CLKDEV_LOOKUP 508 select CLKSRC_PXA 509 select CLKSRC_MMIO 510 select TIMER_OF 511 select CPU_XSCALE if !CPU_XSC3 512 select GENERIC_CLOCKEVENTS 513 select GENERIC_IRQ_MULTI_HANDLER 514 select GPIO_PXA 515 select GPIOLIB 516 select HAVE_IDE 517 select IRQ_DOMAIN 518 select PLAT_PXA 519 select SPARSE_IRQ 520 help 521 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 522 523config ARCH_RPC 524 bool "RiscPC" 525 depends on MMU 526 select ARCH_ACORN 527 select ARCH_MAY_HAVE_PC_FDC 528 select ARCH_SPARSEMEM_ENABLE 529 select ARM_HAS_SG_CHAIN 530 select CPU_SA110 531 select FIQ 532 select HAVE_IDE 533 select HAVE_PATA_PLATFORM 534 select ISA_DMA_API 535 select NEED_MACH_IO_H 536 select NEED_MACH_MEMORY_H 537 select NO_IOPORT_MAP 538 help 539 On the Acorn Risc-PC, Linux can support the internal IDE disk and 540 CD-ROM interface, serial and parallel port, and the floppy drive. 541 542config ARCH_SA1100 543 bool "SA1100-based" 544 select ARCH_MTD_XIP 545 select ARCH_SPARSEMEM_ENABLE 546 select CLKDEV_LOOKUP 547 select CLKSRC_MMIO 548 select CLKSRC_PXA 549 select TIMER_OF if OF 550 select COMMON_CLK 551 select CPU_FREQ 552 select CPU_SA1100 553 select GENERIC_CLOCKEVENTS 554 select GENERIC_IRQ_MULTI_HANDLER 555 select GPIOLIB 556 select HAVE_IDE 557 select IRQ_DOMAIN 558 select ISA 559 select NEED_MACH_MEMORY_H 560 select SPARSE_IRQ 561 help 562 Support for StrongARM 11x0 based boards. 563 564config ARCH_S3C24XX 565 bool "Samsung S3C24XX SoCs" 566 select ATAGS 567 select CLKDEV_LOOKUP 568 select CLKSRC_SAMSUNG_PWM 569 select GENERIC_CLOCKEVENTS 570 select GPIO_SAMSUNG 571 select GPIOLIB 572 select GENERIC_IRQ_MULTI_HANDLER 573 select HAVE_S3C2410_I2C if I2C 574 select HAVE_S3C2410_WATCHDOG if WATCHDOG 575 select HAVE_S3C_RTC if RTC_CLASS 576 select NEED_MACH_IO_H 577 select SAMSUNG_ATAGS 578 select USE_OF 579 help 580 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 581 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 582 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 583 Samsung SMDK2410 development board (and derivatives). 584 585config ARCH_DAVINCI 586 bool "TI DaVinci" 587 select ARCH_HAS_HOLES_MEMORYMODEL 588 select COMMON_CLK 589 select CPU_ARM926T 590 select GENERIC_ALLOCATOR 591 select GENERIC_CLOCKEVENTS 592 select GENERIC_IRQ_CHIP 593 select GENERIC_IRQ_MULTI_HANDLER 594 select GPIOLIB 595 select HAVE_IDE 596 select PM_GENERIC_DOMAINS if PM 597 select PM_GENERIC_DOMAINS_OF if PM && OF 598 select REGMAP_MMIO 599 select RESET_CONTROLLER 600 select SPARSE_IRQ 601 select USE_OF 602 select ZONE_DMA 603 help 604 Support for TI's DaVinci platform. 605 606config ARCH_OMAP1 607 bool "TI OMAP1" 608 depends on MMU 609 select ARCH_HAS_HOLES_MEMORYMODEL 610 select ARCH_OMAP 611 select CLKDEV_LOOKUP 612 select CLKSRC_MMIO 613 select GENERIC_CLOCKEVENTS 614 select GENERIC_IRQ_CHIP 615 select GENERIC_IRQ_MULTI_HANDLER 616 select GPIOLIB 617 select HAVE_IDE 618 select IRQ_DOMAIN 619 select NEED_MACH_IO_H if PCCARD 620 select NEED_MACH_MEMORY_H 621 select SPARSE_IRQ 622 help 623 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 624 625endchoice 626 627menu "Multiple platform selection" 628 depends on ARCH_MULTIPLATFORM 629 630comment "CPU Core family selection" 631 632config ARCH_MULTI_V4 633 bool "ARMv4 based platforms (FA526)" 634 depends on !ARCH_MULTI_V6_V7 635 select ARCH_MULTI_V4_V5 636 select CPU_FA526 637 638config ARCH_MULTI_V4T 639 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 640 depends on !ARCH_MULTI_V6_V7 641 select ARCH_MULTI_V4_V5 642 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 643 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 644 CPU_ARM925T || CPU_ARM940T) 645 646config ARCH_MULTI_V5 647 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 648 depends on !ARCH_MULTI_V6_V7 649 select ARCH_MULTI_V4_V5 650 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 651 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 652 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 653 654config ARCH_MULTI_V4_V5 655 bool 656 657config ARCH_MULTI_V6 658 bool "ARMv6 based platforms (ARM11)" 659 select ARCH_MULTI_V6_V7 660 select CPU_V6K 661 662config ARCH_MULTI_V7 663 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 664 default y 665 select ARCH_MULTI_V6_V7 666 select CPU_V7 667 select HAVE_SMP 668 669config ARCH_MULTI_V6_V7 670 bool 671 select MIGHT_HAVE_CACHE_L2X0 672 673config ARCH_MULTI_CPU_AUTO 674 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 675 select ARCH_MULTI_V5 676 677endmenu 678 679config ARCH_VIRT 680 bool "Dummy Virtual Machine" 681 depends on ARCH_MULTI_V7 682 select ARM_AMBA 683 select ARM_GIC 684 select ARM_GIC_V2M if PCI 685 select ARM_GIC_V3 686 select ARM_GIC_V3_ITS if PCI 687 select ARM_PSCI 688 select HAVE_ARM_ARCH_TIMER 689 select ARCH_SUPPORTS_BIG_ENDIAN 690 691# 692# This is sorted alphabetically by mach-* pathname. However, plat-* 693# Kconfigs may be included either alphabetically (according to the 694# plat- suffix) or along side the corresponding mach-* source. 695# 696source "arch/arm/mach-actions/Kconfig" 697 698source "arch/arm/mach-alpine/Kconfig" 699 700source "arch/arm/mach-artpec/Kconfig" 701 702source "arch/arm/mach-asm9260/Kconfig" 703 704source "arch/arm/mach-aspeed/Kconfig" 705 706source "arch/arm/mach-at91/Kconfig" 707 708source "arch/arm/mach-axxia/Kconfig" 709 710source "arch/arm/mach-bcm/Kconfig" 711 712source "arch/arm/mach-berlin/Kconfig" 713 714source "arch/arm/mach-clps711x/Kconfig" 715 716source "arch/arm/mach-cns3xxx/Kconfig" 717 718source "arch/arm/mach-davinci/Kconfig" 719 720source "arch/arm/mach-digicolor/Kconfig" 721 722source "arch/arm/mach-dove/Kconfig" 723 724source "arch/arm/mach-ep93xx/Kconfig" 725 726source "arch/arm/mach-exynos/Kconfig" 727source "arch/arm/plat-samsung/Kconfig" 728 729source "arch/arm/mach-footbridge/Kconfig" 730 731source "arch/arm/mach-gemini/Kconfig" 732 733source "arch/arm/mach-highbank/Kconfig" 734 735source "arch/arm/mach-hisi/Kconfig" 736 737source "arch/arm/mach-imx/Kconfig" 738 739source "arch/arm/mach-integrator/Kconfig" 740 741source "arch/arm/mach-iop13xx/Kconfig" 742 743source "arch/arm/mach-iop32x/Kconfig" 744 745source "arch/arm/mach-iop33x/Kconfig" 746 747source "arch/arm/mach-ixp4xx/Kconfig" 748 749source "arch/arm/mach-keystone/Kconfig" 750 751source "arch/arm/mach-ks8695/Kconfig" 752 753source "arch/arm/mach-mediatek/Kconfig" 754 755source "arch/arm/mach-meson/Kconfig" 756 757source "arch/arm/mach-milbeaut/Kconfig" 758 759source "arch/arm/mach-mmp/Kconfig" 760 761source "arch/arm/mach-moxart/Kconfig" 762 763source "arch/arm/mach-mv78xx0/Kconfig" 764 765source "arch/arm/mach-mvebu/Kconfig" 766 767source "arch/arm/mach-mxs/Kconfig" 768 769source "arch/arm/mach-nomadik/Kconfig" 770 771source "arch/arm/mach-npcm/Kconfig" 772 773source "arch/arm/mach-nspire/Kconfig" 774 775source "arch/arm/plat-omap/Kconfig" 776 777source "arch/arm/mach-omap1/Kconfig" 778 779source "arch/arm/mach-omap2/Kconfig" 780 781source "arch/arm/mach-orion5x/Kconfig" 782 783source "arch/arm/mach-oxnas/Kconfig" 784 785source "arch/arm/mach-picoxcell/Kconfig" 786 787source "arch/arm/mach-prima2/Kconfig" 788 789source "arch/arm/mach-pxa/Kconfig" 790source "arch/arm/plat-pxa/Kconfig" 791 792source "arch/arm/mach-qcom/Kconfig" 793 794source "arch/arm/mach-rda/Kconfig" 795 796source "arch/arm/mach-realview/Kconfig" 797 798source "arch/arm/mach-rockchip/Kconfig" 799 800source "arch/arm/mach-s3c24xx/Kconfig" 801 802source "arch/arm/mach-s3c64xx/Kconfig" 803 804source "arch/arm/mach-s5pv210/Kconfig" 805 806source "arch/arm/mach-sa1100/Kconfig" 807 808source "arch/arm/mach-shmobile/Kconfig" 809 810source "arch/arm/mach-socfpga/Kconfig" 811 812source "arch/arm/mach-spear/Kconfig" 813 814source "arch/arm/mach-sti/Kconfig" 815 816source "arch/arm/mach-stm32/Kconfig" 817 818source "arch/arm/mach-sunxi/Kconfig" 819 820source "arch/arm/mach-tango/Kconfig" 821 822source "arch/arm/mach-tegra/Kconfig" 823 824source "arch/arm/mach-u300/Kconfig" 825 826source "arch/arm/mach-uniphier/Kconfig" 827 828source "arch/arm/mach-ux500/Kconfig" 829 830source "arch/arm/mach-versatile/Kconfig" 831 832source "arch/arm/mach-vexpress/Kconfig" 833source "arch/arm/plat-versatile/Kconfig" 834 835source "arch/arm/mach-vt8500/Kconfig" 836 837source "arch/arm/mach-w90x900/Kconfig" 838 839source "arch/arm/mach-zx/Kconfig" 840 841source "arch/arm/mach-zynq/Kconfig" 842 843# ARMv7-M architecture 844config ARCH_EFM32 845 bool "Energy Micro efm32" 846 depends on ARM_SINGLE_ARMV7M 847 select GPIOLIB 848 help 849 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 850 processors. 851 852config ARCH_LPC18XX 853 bool "NXP LPC18xx/LPC43xx" 854 depends on ARM_SINGLE_ARMV7M 855 select ARCH_HAS_RESET_CONTROLLER 856 select ARM_AMBA 857 select CLKSRC_LPC32XX 858 select PINCTRL 859 help 860 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 861 high performance microcontrollers. 862 863config ARCH_MPS2 864 bool "ARM MPS2 platform" 865 depends on ARM_SINGLE_ARMV7M 866 select ARM_AMBA 867 select CLKSRC_MPS2 868 help 869 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 870 with a range of available cores like Cortex-M3/M4/M7. 871 872 Please, note that depends which Application Note is used memory map 873 for the platform may vary, so adjustment of RAM base might be needed. 874 875# Definitions to make life easier 876config ARCH_ACORN 877 bool 878 879config PLAT_IOP 880 bool 881 select GENERIC_CLOCKEVENTS 882 883config PLAT_ORION 884 bool 885 select CLKSRC_MMIO 886 select COMMON_CLK 887 select GENERIC_IRQ_CHIP 888 select IRQ_DOMAIN 889 890config PLAT_ORION_LEGACY 891 bool 892 select PLAT_ORION 893 894config PLAT_PXA 895 bool 896 897config PLAT_VERSATILE 898 bool 899 900source "arch/arm/mm/Kconfig" 901 902config IWMMXT 903 bool "Enable iWMMXt support" 904 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 905 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 906 help 907 Enable support for iWMMXt context switching at run time if 908 running on a CPU that supports it. 909 910if !MMU 911source "arch/arm/Kconfig-nommu" 912endif 913 914config PJ4B_ERRATA_4742 915 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 916 depends on CPU_PJ4B && MACH_ARMADA_370 917 default y 918 help 919 When coming out of either a Wait for Interrupt (WFI) or a Wait for 920 Event (WFE) IDLE states, a specific timing sensitivity exists between 921 the retiring WFI/WFE instructions and the newly issued subsequent 922 instructions. This sensitivity can result in a CPU hang scenario. 923 Workaround: 924 The software must insert either a Data Synchronization Barrier (DSB) 925 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 926 instruction 927 928config ARM_ERRATA_326103 929 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 930 depends on CPU_V6 931 help 932 Executing a SWP instruction to read-only memory does not set bit 11 933 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 934 treat the access as a read, preventing a COW from occurring and 935 causing the faulting task to livelock. 936 937config ARM_ERRATA_411920 938 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 939 depends on CPU_V6 || CPU_V6K 940 help 941 Invalidation of the Instruction Cache operation can 942 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 943 It does not affect the MPCore. This option enables the ARM Ltd. 944 recommended workaround. 945 946config ARM_ERRATA_430973 947 bool "ARM errata: Stale prediction on replaced interworking branch" 948 depends on CPU_V7 949 help 950 This option enables the workaround for the 430973 Cortex-A8 951 r1p* erratum. If a code sequence containing an ARM/Thumb 952 interworking branch is replaced with another code sequence at the 953 same virtual address, whether due to self-modifying code or virtual 954 to physical address re-mapping, Cortex-A8 does not recover from the 955 stale interworking branch prediction. This results in Cortex-A8 956 executing the new code sequence in the incorrect ARM or Thumb state. 957 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 958 and also flushes the branch target cache at every context switch. 959 Note that setting specific bits in the ACTLR register may not be 960 available in non-secure mode. 961 962config ARM_ERRATA_458693 963 bool "ARM errata: Processor deadlock when a false hazard is created" 964 depends on CPU_V7 965 depends on !ARCH_MULTIPLATFORM 966 help 967 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 968 erratum. For very specific sequences of memory operations, it is 969 possible for a hazard condition intended for a cache line to instead 970 be incorrectly associated with a different cache line. This false 971 hazard might then cause a processor deadlock. The workaround enables 972 the L1 caching of the NEON accesses and disables the PLD instruction 973 in the ACTLR register. Note that setting specific bits in the ACTLR 974 register may not be available in non-secure mode. 975 976config ARM_ERRATA_460075 977 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 978 depends on CPU_V7 979 depends on !ARCH_MULTIPLATFORM 980 help 981 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 982 erratum. Any asynchronous access to the L2 cache may encounter a 983 situation in which recent store transactions to the L2 cache are lost 984 and overwritten with stale memory contents from external memory. The 985 workaround disables the write-allocate mode for the L2 cache via the 986 ACTLR register. Note that setting specific bits in the ACTLR register 987 may not be available in non-secure mode. 988 989config ARM_ERRATA_742230 990 bool "ARM errata: DMB operation may be faulty" 991 depends on CPU_V7 && SMP 992 depends on !ARCH_MULTIPLATFORM 993 help 994 This option enables the workaround for the 742230 Cortex-A9 995 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 996 between two write operations may not ensure the correct visibility 997 ordering of the two writes. This workaround sets a specific bit in 998 the diagnostic register of the Cortex-A9 which causes the DMB 999 instruction to behave as a DSB, ensuring the correct behaviour of 1000 the two writes. 1001 1002config ARM_ERRATA_742231 1003 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1004 depends on CPU_V7 && SMP 1005 depends on !ARCH_MULTIPLATFORM 1006 help 1007 This option enables the workaround for the 742231 Cortex-A9 1008 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1009 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1010 accessing some data located in the same cache line, may get corrupted 1011 data due to bad handling of the address hazard when the line gets 1012 replaced from one of the CPUs at the same time as another CPU is 1013 accessing it. This workaround sets specific bits in the diagnostic 1014 register of the Cortex-A9 which reduces the linefill issuing 1015 capabilities of the processor. 1016 1017config ARM_ERRATA_643719 1018 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1019 depends on CPU_V7 && SMP 1020 default y 1021 help 1022 This option enables the workaround for the 643719 Cortex-A9 (prior to 1023 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1024 register returns zero when it should return one. The workaround 1025 corrects this value, ensuring cache maintenance operations which use 1026 it behave as intended and avoiding data corruption. 1027 1028config ARM_ERRATA_720789 1029 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1030 depends on CPU_V7 1031 help 1032 This option enables the workaround for the 720789 Cortex-A9 (prior to 1033 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1034 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1035 As a consequence of this erratum, some TLB entries which should be 1036 invalidated are not, resulting in an incoherency in the system page 1037 tables. The workaround changes the TLB flushing routines to invalidate 1038 entries regardless of the ASID. 1039 1040config ARM_ERRATA_743622 1041 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1042 depends on CPU_V7 1043 depends on !ARCH_MULTIPLATFORM 1044 help 1045 This option enables the workaround for the 743622 Cortex-A9 1046 (r2p*) erratum. Under very rare conditions, a faulty 1047 optimisation in the Cortex-A9 Store Buffer may lead to data 1048 corruption. This workaround sets a specific bit in the diagnostic 1049 register of the Cortex-A9 which disables the Store Buffer 1050 optimisation, preventing the defect from occurring. This has no 1051 visible impact on the overall performance or power consumption of the 1052 processor. 1053 1054config ARM_ERRATA_751472 1055 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1056 depends on CPU_V7 1057 depends on !ARCH_MULTIPLATFORM 1058 help 1059 This option enables the workaround for the 751472 Cortex-A9 (prior 1060 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1061 completion of a following broadcasted operation if the second 1062 operation is received by a CPU before the ICIALLUIS has completed, 1063 potentially leading to corrupted entries in the cache or TLB. 1064 1065config ARM_ERRATA_754322 1066 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1067 depends on CPU_V7 1068 help 1069 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1070 r3p*) erratum. A speculative memory access may cause a page table walk 1071 which starts prior to an ASID switch but completes afterwards. This 1072 can populate the micro-TLB with a stale entry which may be hit with 1073 the new ASID. This workaround places two dsb instructions in the mm 1074 switching code so that no page table walks can cross the ASID switch. 1075 1076config ARM_ERRATA_754327 1077 bool "ARM errata: no automatic Store Buffer drain" 1078 depends on CPU_V7 && SMP 1079 help 1080 This option enables the workaround for the 754327 Cortex-A9 (prior to 1081 r2p0) erratum. The Store Buffer does not have any automatic draining 1082 mechanism and therefore a livelock may occur if an external agent 1083 continuously polls a memory location waiting to observe an update. 1084 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1085 written polling loops from denying visibility of updates to memory. 1086 1087config ARM_ERRATA_364296 1088 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1089 depends on CPU_V6 1090 help 1091 This options enables the workaround for the 364296 ARM1136 1092 r0p2 erratum (possible cache data corruption with 1093 hit-under-miss enabled). It sets the undocumented bit 31 in 1094 the auxiliary control register and the FI bit in the control 1095 register, thus disabling hit-under-miss without putting the 1096 processor into full low interrupt latency mode. ARM11MPCore 1097 is not affected. 1098 1099config ARM_ERRATA_764369 1100 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1101 depends on CPU_V7 && SMP 1102 help 1103 This option enables the workaround for erratum 764369 1104 affecting Cortex-A9 MPCore with two or more processors (all 1105 current revisions). Under certain timing circumstances, a data 1106 cache line maintenance operation by MVA targeting an Inner 1107 Shareable memory region may fail to proceed up to either the 1108 Point of Coherency or to the Point of Unification of the 1109 system. This workaround adds a DSB instruction before the 1110 relevant cache maintenance functions and sets a specific bit 1111 in the diagnostic control register of the SCU. 1112 1113config ARM_ERRATA_775420 1114 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1115 depends on CPU_V7 1116 help 1117 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1118 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1119 operation aborts with MMU exception, it might cause the processor 1120 to deadlock. This workaround puts DSB before executing ISB if 1121 an abort may occur on cache maintenance. 1122 1123config ARM_ERRATA_798181 1124 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1125 depends on CPU_V7 && SMP 1126 help 1127 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1128 adequately shooting down all use of the old entries. This 1129 option enables the Linux kernel workaround for this erratum 1130 which sends an IPI to the CPUs that are running the same ASID 1131 as the one being invalidated. 1132 1133config ARM_ERRATA_773022 1134 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1135 depends on CPU_V7 1136 help 1137 This option enables the workaround for the 773022 Cortex-A15 1138 (up to r0p4) erratum. In certain rare sequences of code, the 1139 loop buffer may deliver incorrect instructions. This 1140 workaround disables the loop buffer to avoid the erratum. 1141 1142config ARM_ERRATA_818325_852422 1143 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1144 depends on CPU_V7 1145 help 1146 This option enables the workaround for: 1147 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1148 instruction might deadlock. Fixed in r0p1. 1149 - Cortex-A12 852422: Execution of a sequence of instructions might 1150 lead to either a data corruption or a CPU deadlock. Not fixed in 1151 any Cortex-A12 cores yet. 1152 This workaround for all both errata involves setting bit[12] of the 1153 Feature Register. This bit disables an optimisation applied to a 1154 sequence of 2 instructions that use opposing condition codes. 1155 1156config ARM_ERRATA_821420 1157 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1158 depends on CPU_V7 1159 help 1160 This option enables the workaround for the 821420 Cortex-A12 1161 (all revs) erratum. In very rare timing conditions, a sequence 1162 of VMOV to Core registers instructions, for which the second 1163 one is in the shadow of a branch or abort, can lead to a 1164 deadlock when the VMOV instructions are issued out-of-order. 1165 1166config ARM_ERRATA_825619 1167 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1168 depends on CPU_V7 1169 help 1170 This option enables the workaround for the 825619 Cortex-A12 1171 (all revs) erratum. Within rare timing constraints, executing a 1172 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1173 and Device/Strongly-Ordered loads and stores might cause deadlock 1174 1175config ARM_ERRATA_857271 1176 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1177 depends on CPU_V7 1178 help 1179 This option enables the workaround for the 857271 Cortex-A12 1180 (all revs) erratum. Under very rare timing conditions, the CPU might 1181 hang. The workaround is expected to have a < 1% performance impact. 1182 1183config ARM_ERRATA_852421 1184 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1185 depends on CPU_V7 1186 help 1187 This option enables the workaround for the 852421 Cortex-A17 1188 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1189 execution of a DMB ST instruction might fail to properly order 1190 stores from GroupA and stores from GroupB. 1191 1192config ARM_ERRATA_852423 1193 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1194 depends on CPU_V7 1195 help 1196 This option enables the workaround for: 1197 - Cortex-A17 852423: Execution of a sequence of instructions might 1198 lead to either a data corruption or a CPU deadlock. Not fixed in 1199 any Cortex-A17 cores yet. 1200 This is identical to Cortex-A12 erratum 852422. It is a separate 1201 config option from the A12 erratum due to the way errata are checked 1202 for and handled. 1203 1204config ARM_ERRATA_857272 1205 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1206 depends on CPU_V7 1207 help 1208 This option enables the workaround for the 857272 Cortex-A17 erratum. 1209 This erratum is not known to be fixed in any A17 revision. 1210 This is identical to Cortex-A12 erratum 857271. It is a separate 1211 config option from the A12 erratum due to the way errata are checked 1212 for and handled. 1213 1214endmenu 1215 1216source "arch/arm/common/Kconfig" 1217 1218menu "Bus support" 1219 1220config ISA 1221 bool 1222 help 1223 Find out whether you have ISA slots on your motherboard. ISA is the 1224 name of a bus system, i.e. the way the CPU talks to the other stuff 1225 inside your box. Other bus systems are PCI, EISA, MicroChannel 1226 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1227 newer boards don't support it. If you have ISA, say Y, otherwise N. 1228 1229# Select ISA DMA controller support 1230config ISA_DMA 1231 bool 1232 select ISA_DMA_API 1233 1234# Select ISA DMA interface 1235config ISA_DMA_API 1236 bool 1237 1238config PCI_NANOENGINE 1239 bool "BSE nanoEngine PCI support" 1240 depends on SA1100_NANOENGINE 1241 help 1242 Enable PCI on the BSE nanoEngine board. 1243 1244config PCI_HOST_ITE8152 1245 bool 1246 depends on PCI && MACH_ARMCORE 1247 default y 1248 select DMABOUNCE 1249 1250config ARM_ERRATA_814220 1251 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1252 depends on CPU_V7 1253 help 1254 The v7 ARM states that all cache and branch predictor maintenance 1255 operations that do not specify an address execute, relative to 1256 each other, in program order. 1257 However, because of this erratum, an L2 set/way cache maintenance 1258 operation can overtake an L1 set/way cache maintenance operation. 1259 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1260 r0p4, r0p5. 1261 1262endmenu 1263 1264menu "Kernel Features" 1265 1266config HAVE_SMP 1267 bool 1268 help 1269 This option should be selected by machines which have an SMP- 1270 capable CPU. 1271 1272 The only effect of this option is to make the SMP-related 1273 options available to the user for configuration. 1274 1275config SMP 1276 bool "Symmetric Multi-Processing" 1277 depends on CPU_V6K || CPU_V7 1278 depends on GENERIC_CLOCKEVENTS 1279 depends on HAVE_SMP 1280 depends on MMU || ARM_MPU 1281 select IRQ_WORK 1282 help 1283 This enables support for systems with more than one CPU. If you have 1284 a system with only one CPU, say N. If you have a system with more 1285 than one CPU, say Y. 1286 1287 If you say N here, the kernel will run on uni- and multiprocessor 1288 machines, but will use only one CPU of a multiprocessor machine. If 1289 you say Y here, the kernel will run on many, but not all, 1290 uniprocessor machines. On a uniprocessor machine, the kernel 1291 will run faster if you say N here. 1292 1293 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1294 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1295 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1296 1297 If you don't know what to do here, say N. 1298 1299config SMP_ON_UP 1300 bool "Allow booting SMP kernel on uniprocessor systems" 1301 depends on SMP && !XIP_KERNEL && MMU 1302 default y 1303 help 1304 SMP kernels contain instructions which fail on non-SMP processors. 1305 Enabling this option allows the kernel to modify itself to make 1306 these instructions safe. Disabling it allows about 1K of space 1307 savings. 1308 1309 If you don't know what to do here, say Y. 1310 1311config ARM_CPU_TOPOLOGY 1312 bool "Support cpu topology definition" 1313 depends on SMP && CPU_V7 1314 default y 1315 help 1316 Support ARM cpu topology definition. The MPIDR register defines 1317 affinity between processors which is then used to describe the cpu 1318 topology of an ARM System. 1319 1320config SCHED_MC 1321 bool "Multi-core scheduler support" 1322 depends on ARM_CPU_TOPOLOGY 1323 help 1324 Multi-core scheduler support improves the CPU scheduler's decision 1325 making when dealing with multi-core CPU chips at a cost of slightly 1326 increased overhead in some places. If unsure say N here. 1327 1328config SCHED_SMT 1329 bool "SMT scheduler support" 1330 depends on ARM_CPU_TOPOLOGY 1331 help 1332 Improves the CPU scheduler's decision making when dealing with 1333 MultiThreading at a cost of slightly increased overhead in some 1334 places. If unsure say N here. 1335 1336config HAVE_ARM_SCU 1337 bool 1338 help 1339 This option enables support for the ARM snoop control unit 1340 1341config HAVE_ARM_ARCH_TIMER 1342 bool "Architected timer support" 1343 depends on CPU_V7 1344 select ARM_ARCH_TIMER 1345 select GENERIC_CLOCKEVENTS 1346 help 1347 This option enables support for the ARM architected timer 1348 1349config HAVE_ARM_TWD 1350 bool 1351 help 1352 This options enables support for the ARM timer and watchdog unit 1353 1354config MCPM 1355 bool "Multi-Cluster Power Management" 1356 depends on CPU_V7 && SMP 1357 help 1358 This option provides the common power management infrastructure 1359 for (multi-)cluster based systems, such as big.LITTLE based 1360 systems. 1361 1362config MCPM_QUAD_CLUSTER 1363 bool 1364 depends on MCPM 1365 help 1366 To avoid wasting resources unnecessarily, MCPM only supports up 1367 to 2 clusters by default. 1368 Platforms with 3 or 4 clusters that use MCPM must select this 1369 option to allow the additional clusters to be managed. 1370 1371config BIG_LITTLE 1372 bool "big.LITTLE support (Experimental)" 1373 depends on CPU_V7 && SMP 1374 select MCPM 1375 help 1376 This option enables support selections for the big.LITTLE 1377 system architecture. 1378 1379config BL_SWITCHER 1380 bool "big.LITTLE switcher support" 1381 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1382 select CPU_PM 1383 help 1384 The big.LITTLE "switcher" provides the core functionality to 1385 transparently handle transition between a cluster of A15's 1386 and a cluster of A7's in a big.LITTLE system. 1387 1388config BL_SWITCHER_DUMMY_IF 1389 tristate "Simple big.LITTLE switcher user interface" 1390 depends on BL_SWITCHER && DEBUG_KERNEL 1391 help 1392 This is a simple and dummy char dev interface to control 1393 the big.LITTLE switcher core code. It is meant for 1394 debugging purposes only. 1395 1396choice 1397 prompt "Memory split" 1398 depends on MMU 1399 default VMSPLIT_3G 1400 help 1401 Select the desired split between kernel and user memory. 1402 1403 If you are not absolutely sure what you are doing, leave this 1404 option alone! 1405 1406 config VMSPLIT_3G 1407 bool "3G/1G user/kernel split" 1408 config VMSPLIT_3G_OPT 1409 depends on !ARM_LPAE 1410 bool "3G/1G user/kernel split (for full 1G low memory)" 1411 config VMSPLIT_2G 1412 bool "2G/2G user/kernel split" 1413 config VMSPLIT_1G 1414 bool "1G/3G user/kernel split" 1415endchoice 1416 1417config PAGE_OFFSET 1418 hex 1419 default PHYS_OFFSET if !MMU 1420 default 0x40000000 if VMSPLIT_1G 1421 default 0x80000000 if VMSPLIT_2G 1422 default 0xB0000000 if VMSPLIT_3G_OPT 1423 default 0xC0000000 1424 1425config NR_CPUS 1426 int "Maximum number of CPUs (2-32)" 1427 range 2 32 1428 depends on SMP 1429 default "4" 1430 1431config HOTPLUG_CPU 1432 bool "Support for hot-pluggable CPUs" 1433 depends on SMP 1434 select GENERIC_IRQ_MIGRATION 1435 help 1436 Say Y here to experiment with turning CPUs off and on. CPUs 1437 can be controlled through /sys/devices/system/cpu. 1438 1439config ARM_PSCI 1440 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1441 depends on HAVE_ARM_SMCCC 1442 select ARM_PSCI_FW 1443 help 1444 Say Y here if you want Linux to communicate with system firmware 1445 implementing the PSCI specification for CPU-centric power 1446 management operations described in ARM document number ARM DEN 1447 0022A ("Power State Coordination Interface System Software on 1448 ARM processors"). 1449 1450# The GPIO number here must be sorted by descending number. In case of 1451# a multiplatform kernel, we just want the highest value required by the 1452# selected platforms. 1453config ARCH_NR_GPIO 1454 int 1455 default 2048 if ARCH_SOCFPGA 1456 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1457 ARCH_ZYNQ 1458 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1459 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1460 default 416 if ARCH_SUNXI 1461 default 392 if ARCH_U8500 1462 default 352 if ARCH_VT8500 1463 default 288 if ARCH_ROCKCHIP 1464 default 264 if MACH_H4700 1465 default 0 1466 help 1467 Maximum number of GPIOs in the system. 1468 1469 If unsure, leave the default value. 1470 1471config HZ_FIXED 1472 int 1473 default 200 if ARCH_EBSA110 1474 default 128 if SOC_AT91RM9200 1475 default 0 1476 1477choice 1478 depends on HZ_FIXED = 0 1479 prompt "Timer frequency" 1480 1481config HZ_100 1482 bool "100 Hz" 1483 1484config HZ_200 1485 bool "200 Hz" 1486 1487config HZ_250 1488 bool "250 Hz" 1489 1490config HZ_300 1491 bool "300 Hz" 1492 1493config HZ_500 1494 bool "500 Hz" 1495 1496config HZ_1000 1497 bool "1000 Hz" 1498 1499endchoice 1500 1501config HZ 1502 int 1503 default HZ_FIXED if HZ_FIXED != 0 1504 default 100 if HZ_100 1505 default 200 if HZ_200 1506 default 250 if HZ_250 1507 default 300 if HZ_300 1508 default 500 if HZ_500 1509 default 1000 1510 1511config SCHED_HRTICK 1512 def_bool HIGH_RES_TIMERS 1513 1514config THUMB2_KERNEL 1515 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1516 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1517 default y if CPU_THUMBONLY 1518 select ARM_UNWIND 1519 help 1520 By enabling this option, the kernel will be compiled in 1521 Thumb-2 mode. 1522 1523 If unsure, say N. 1524 1525config THUMB2_AVOID_R_ARM_THM_JUMP11 1526 bool "Work around buggy Thumb-2 short branch relocations in gas" 1527 depends on THUMB2_KERNEL && MODULES 1528 default y 1529 help 1530 Various binutils versions can resolve Thumb-2 branches to 1531 locally-defined, preemptible global symbols as short-range "b.n" 1532 branch instructions. 1533 1534 This is a problem, because there's no guarantee the final 1535 destination of the symbol, or any candidate locations for a 1536 trampoline, are within range of the branch. For this reason, the 1537 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1538 relocation in modules at all, and it makes little sense to add 1539 support. 1540 1541 The symptom is that the kernel fails with an "unsupported 1542 relocation" error when loading some modules. 1543 1544 Until fixed tools are available, passing 1545 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1546 code which hits this problem, at the cost of a bit of extra runtime 1547 stack usage in some cases. 1548 1549 The problem is described in more detail at: 1550 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1551 1552 Only Thumb-2 kernels are affected. 1553 1554 Unless you are sure your tools don't have this problem, say Y. 1555 1556config ARM_PATCH_IDIV 1557 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1558 depends on CPU_32v7 && !XIP_KERNEL 1559 default y 1560 help 1561 The ARM compiler inserts calls to __aeabi_idiv() and 1562 __aeabi_uidiv() when it needs to perform division on signed 1563 and unsigned integers. Some v7 CPUs have support for the sdiv 1564 and udiv instructions that can be used to implement those 1565 functions. 1566 1567 Enabling this option allows the kernel to modify itself to 1568 replace the first two instructions of these library functions 1569 with the sdiv or udiv plus "bx lr" instructions when the CPU 1570 it is running on supports them. Typically this will be faster 1571 and less power intensive than running the original library 1572 code to do integer division. 1573 1574config AEABI 1575 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K 1576 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K 1577 help 1578 This option allows for the kernel to be compiled using the latest 1579 ARM ABI (aka EABI). This is only useful if you are using a user 1580 space environment that is also compiled with EABI. 1581 1582 Since there are major incompatibilities between the legacy ABI and 1583 EABI, especially with regard to structure member alignment, this 1584 option also changes the kernel syscall calling convention to 1585 disambiguate both ABIs and allow for backward compatibility support 1586 (selected with CONFIG_OABI_COMPAT). 1587 1588 To use this you need GCC version 4.0.0 or later. 1589 1590config OABI_COMPAT 1591 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1592 depends on AEABI && !THUMB2_KERNEL 1593 help 1594 This option preserves the old syscall interface along with the 1595 new (ARM EABI) one. It also provides a compatibility layer to 1596 intercept syscalls that have structure arguments which layout 1597 in memory differs between the legacy ABI and the new ARM EABI 1598 (only for non "thumb" binaries). This option adds a tiny 1599 overhead to all syscalls and produces a slightly larger kernel. 1600 1601 The seccomp filter system will not be available when this is 1602 selected, since there is no way yet to sensibly distinguish 1603 between calling conventions during filtering. 1604 1605 If you know you'll be using only pure EABI user space then you 1606 can say N here. If this option is not selected and you attempt 1607 to execute a legacy ABI binary then the result will be 1608 UNPREDICTABLE (in fact it can be predicted that it won't work 1609 at all). If in doubt say N. 1610 1611config ARCH_HAS_HOLES_MEMORYMODEL 1612 bool 1613 1614config ARCH_SPARSEMEM_ENABLE 1615 bool 1616 1617config ARCH_SPARSEMEM_DEFAULT 1618 def_bool ARCH_SPARSEMEM_ENABLE 1619 1620config HAVE_ARCH_PFN_VALID 1621 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1622 1623config HIGHMEM 1624 bool "High Memory Support" 1625 depends on MMU 1626 help 1627 The address space of ARM processors is only 4 Gigabytes large 1628 and it has to accommodate user address space, kernel address 1629 space as well as some memory mapped IO. That means that, if you 1630 have a large amount of physical memory and/or IO, not all of the 1631 memory can be "permanently mapped" by the kernel. The physical 1632 memory that is not permanently mapped is called "high memory". 1633 1634 Depending on the selected kernel/user memory split, minimum 1635 vmalloc space and actual amount of RAM, you may not need this 1636 option which should result in a slightly faster kernel. 1637 1638 If unsure, say n. 1639 1640config HIGHPTE 1641 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1642 depends on HIGHMEM 1643 default y 1644 help 1645 The VM uses one page of physical memory for each page table. 1646 For systems with a lot of processes, this can use a lot of 1647 precious low memory, eventually leading to low memory being 1648 consumed by page tables. Setting this option will allow 1649 user-space 2nd level page tables to reside in high memory. 1650 1651config CPU_SW_DOMAIN_PAN 1652 bool "Enable use of CPU domains to implement privileged no-access" 1653 depends on MMU && !ARM_LPAE 1654 default y 1655 help 1656 Increase kernel security by ensuring that normal kernel accesses 1657 are unable to access userspace addresses. This can help prevent 1658 use-after-free bugs becoming an exploitable privilege escalation 1659 by ensuring that magic values (such as LIST_POISON) will always 1660 fault when dereferenced. 1661 1662 CPUs with low-vector mappings use a best-efforts implementation. 1663 Their lower 1MB needs to remain accessible for the vectors, but 1664 the remainder of userspace will become appropriately inaccessible. 1665 1666config HW_PERF_EVENTS 1667 def_bool y 1668 depends on ARM_PMU 1669 1670config SYS_SUPPORTS_HUGETLBFS 1671 def_bool y 1672 depends on ARM_LPAE 1673 1674config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1675 def_bool y 1676 depends on ARM_LPAE 1677 1678config ARCH_WANT_GENERAL_HUGETLB 1679 def_bool y 1680 1681config ARM_MODULE_PLTS 1682 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1683 depends on MODULES 1684 default y 1685 help 1686 Allocate PLTs when loading modules so that jumps and calls whose 1687 targets are too far away for their relative offsets to be encoded 1688 in the instructions themselves can be bounced via veneers in the 1689 module's PLT. This allows modules to be allocated in the generic 1690 vmalloc area after the dedicated module memory area has been 1691 exhausted. The modules will use slightly more memory, but after 1692 rounding up to page size, the actual memory footprint is usually 1693 the same. 1694 1695 Disabling this is usually safe for small single-platform 1696 configurations. If unsure, say y. 1697 1698config FORCE_MAX_ZONEORDER 1699 int "Maximum zone order" 1700 default "12" if SOC_AM33XX 1701 default "9" if SA1111 || ARCH_EFM32 1702 default "11" 1703 help 1704 The kernel memory allocator divides physically contiguous memory 1705 blocks into "zones", where each zone is a power of two number of 1706 pages. This option selects the largest power of two that the kernel 1707 keeps in the memory allocator. If you need to allocate very large 1708 blocks of physically contiguous memory, then you may need to 1709 increase this value. 1710 1711 This config option is actually maximum order plus one. For example, 1712 a value of 11 means that the largest free memory block is 2^10 pages. 1713 1714config ALIGNMENT_TRAP 1715 bool 1716 depends on CPU_CP15_MMU 1717 default y if !ARCH_EBSA110 1718 select HAVE_PROC_CPU if PROC_FS 1719 help 1720 ARM processors cannot fetch/store information which is not 1721 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1722 address divisible by 4. On 32-bit ARM processors, these non-aligned 1723 fetch/store instructions will be emulated in software if you say 1724 here, which has a severe performance impact. This is necessary for 1725 correct operation of some network protocols. With an IP-only 1726 configuration it is safe to say N, otherwise say Y. 1727 1728config UACCESS_WITH_MEMCPY 1729 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1730 depends on MMU 1731 default y if CPU_FEROCEON 1732 help 1733 Implement faster copy_to_user and clear_user methods for CPU 1734 cores where a 8-word STM instruction give significantly higher 1735 memory write throughput than a sequence of individual 32bit stores. 1736 1737 A possible side effect is a slight increase in scheduling latency 1738 between threads sharing the same address space if they invoke 1739 such copy operations with large buffers. 1740 1741 However, if the CPU data cache is using a write-allocate mode, 1742 this option is unlikely to provide any performance gain. 1743 1744config SECCOMP 1745 bool 1746 prompt "Enable seccomp to safely compute untrusted bytecode" 1747 ---help--- 1748 This kernel feature is useful for number crunching applications 1749 that may need to compute untrusted bytecode during their 1750 execution. By using pipes or other transports made available to 1751 the process as file descriptors supporting the read/write 1752 syscalls, it's possible to isolate those applications in 1753 their own address space using seccomp. Once seccomp is 1754 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1755 and the task is only allowed to execute a few safe syscalls 1756 defined by each seccomp mode. 1757 1758config PARAVIRT 1759 bool "Enable paravirtualization code" 1760 help 1761 This changes the kernel so it can modify itself when it is run 1762 under a hypervisor, potentially improving performance significantly 1763 over full virtualization. 1764 1765config PARAVIRT_TIME_ACCOUNTING 1766 bool "Paravirtual steal time accounting" 1767 select PARAVIRT 1768 help 1769 Select this option to enable fine granularity task steal time 1770 accounting. Time spent executing other tasks in parallel with 1771 the current vCPU is discounted from the vCPU power. To account for 1772 that, there can be a small performance impact. 1773 1774 If in doubt, say N here. 1775 1776config XEN_DOM0 1777 def_bool y 1778 depends on XEN 1779 1780config XEN 1781 bool "Xen guest support on ARM" 1782 depends on ARM && AEABI && OF 1783 depends on CPU_V7 && !CPU_V6 1784 depends on !GENERIC_ATOMIC64 1785 depends on MMU 1786 select ARCH_DMA_ADDR_T_64BIT 1787 select ARM_PSCI 1788 select SWIOTLB 1789 select SWIOTLB_XEN 1790 select PARAVIRT 1791 help 1792 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1793 1794config STACKPROTECTOR_PER_TASK 1795 bool "Use a unique stack canary value for each task" 1796 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1797 select GCC_PLUGIN_ARM_SSP_PER_TASK 1798 default y 1799 help 1800 Due to the fact that GCC uses an ordinary symbol reference from 1801 which to load the value of the stack canary, this value can only 1802 change at reboot time on SMP systems, and all tasks running in the 1803 kernel's address space are forced to use the same canary value for 1804 the entire duration that the system is up. 1805 1806 Enable this option to switch to a different method that uses a 1807 different canary value for each task. 1808 1809endmenu 1810 1811menu "Boot options" 1812 1813config USE_OF 1814 bool "Flattened Device Tree support" 1815 select IRQ_DOMAIN 1816 select OF 1817 help 1818 Include support for flattened device tree machine descriptions. 1819 1820config ATAGS 1821 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1822 default y 1823 help 1824 This is the traditional way of passing data to the kernel at boot 1825 time. If you are solely relying on the flattened device tree (or 1826 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1827 to remove ATAGS support from your kernel binary. If unsure, 1828 leave this to y. 1829 1830config DEPRECATED_PARAM_STRUCT 1831 bool "Provide old way to pass kernel parameters" 1832 depends on ATAGS 1833 help 1834 This was deprecated in 2001 and announced to live on for 5 years. 1835 Some old boot loaders still use this way. 1836 1837# Compressed boot loader in ROM. Yes, we really want to ask about 1838# TEXT and BSS so we preserve their values in the config files. 1839config ZBOOT_ROM_TEXT 1840 hex "Compressed ROM boot loader base address" 1841 default "0" 1842 help 1843 The physical address at which the ROM-able zImage is to be 1844 placed in the target. Platforms which normally make use of 1845 ROM-able zImage formats normally set this to a suitable 1846 value in their defconfig file. 1847 1848 If ZBOOT_ROM is not enabled, this has no effect. 1849 1850config ZBOOT_ROM_BSS 1851 hex "Compressed ROM boot loader BSS address" 1852 default "0" 1853 help 1854 The base address of an area of read/write memory in the target 1855 for the ROM-able zImage which must be available while the 1856 decompressor is running. It must be large enough to hold the 1857 entire decompressed kernel plus an additional 128 KiB. 1858 Platforms which normally make use of ROM-able zImage formats 1859 normally set this to a suitable value in their defconfig file. 1860 1861 If ZBOOT_ROM is not enabled, this has no effect. 1862 1863config ZBOOT_ROM 1864 bool "Compressed boot loader in ROM/flash" 1865 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1866 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1867 help 1868 Say Y here if you intend to execute your compressed kernel image 1869 (zImage) directly from ROM or flash. If unsure, say N. 1870 1871config ARM_APPENDED_DTB 1872 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1873 depends on OF 1874 help 1875 With this option, the boot code will look for a device tree binary 1876 (DTB) appended to zImage 1877 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1878 1879 This is meant as a backward compatibility convenience for those 1880 systems with a bootloader that can't be upgraded to accommodate 1881 the documented boot protocol using a device tree. 1882 1883 Beware that there is very little in terms of protection against 1884 this option being confused by leftover garbage in memory that might 1885 look like a DTB header after a reboot if no actual DTB is appended 1886 to zImage. Do not leave this option active in a production kernel 1887 if you don't intend to always append a DTB. Proper passing of the 1888 location into r2 of a bootloader provided DTB is always preferable 1889 to this option. 1890 1891config ARM_ATAG_DTB_COMPAT 1892 bool "Supplement the appended DTB with traditional ATAG information" 1893 depends on ARM_APPENDED_DTB 1894 help 1895 Some old bootloaders can't be updated to a DTB capable one, yet 1896 they provide ATAGs with memory configuration, the ramdisk address, 1897 the kernel cmdline string, etc. Such information is dynamically 1898 provided by the bootloader and can't always be stored in a static 1899 DTB. To allow a device tree enabled kernel to be used with such 1900 bootloaders, this option allows zImage to extract the information 1901 from the ATAG list and store it at run time into the appended DTB. 1902 1903choice 1904 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1905 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1906 1907config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1908 bool "Use bootloader kernel arguments if available" 1909 help 1910 Uses the command-line options passed by the boot loader instead of 1911 the device tree bootargs property. If the boot loader doesn't provide 1912 any, the device tree bootargs property will be used. 1913 1914config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1915 bool "Extend with bootloader kernel arguments" 1916 help 1917 The command-line arguments provided by the boot loader will be 1918 appended to the the device tree bootargs property. 1919 1920endchoice 1921 1922config CMDLINE 1923 string "Default kernel command string" 1924 default "" 1925 help 1926 On some architectures (EBSA110 and CATS), there is currently no way 1927 for the boot loader to pass arguments to the kernel. For these 1928 architectures, you should supply some command-line options at build 1929 time by entering them here. As a minimum, you should specify the 1930 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1931 1932choice 1933 prompt "Kernel command line type" if CMDLINE != "" 1934 default CMDLINE_FROM_BOOTLOADER 1935 depends on ATAGS 1936 1937config CMDLINE_FROM_BOOTLOADER 1938 bool "Use bootloader kernel arguments if available" 1939 help 1940 Uses the command-line options passed by the boot loader. If 1941 the boot loader doesn't provide any, the default kernel command 1942 string provided in CMDLINE will be used. 1943 1944config CMDLINE_EXTEND 1945 bool "Extend bootloader kernel arguments" 1946 help 1947 The command-line arguments provided by the boot loader will be 1948 appended to the default kernel command string. 1949 1950config CMDLINE_FORCE 1951 bool "Always use the default kernel command string" 1952 help 1953 Always use the default kernel command string, even if the boot 1954 loader passes other arguments to the kernel. 1955 This is useful if you cannot or don't want to change the 1956 command-line options your boot loader passes to the kernel. 1957endchoice 1958 1959config XIP_KERNEL 1960 bool "Kernel Execute-In-Place from ROM" 1961 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1962 help 1963 Execute-In-Place allows the kernel to run from non-volatile storage 1964 directly addressable by the CPU, such as NOR flash. This saves RAM 1965 space since the text section of the kernel is not loaded from flash 1966 to RAM. Read-write sections, such as the data section and stack, 1967 are still copied to RAM. The XIP kernel is not compressed since 1968 it has to run directly from flash, so it will take more space to 1969 store it. The flash address used to link the kernel object files, 1970 and for storing it, is configuration dependent. Therefore, if you 1971 say Y here, you must know the proper physical address where to 1972 store the kernel image depending on your own flash memory usage. 1973 1974 Also note that the make target becomes "make xipImage" rather than 1975 "make zImage" or "make Image". The final kernel binary to put in 1976 ROM memory will be arch/arm/boot/xipImage. 1977 1978 If unsure, say N. 1979 1980config XIP_PHYS_ADDR 1981 hex "XIP Kernel Physical Location" 1982 depends on XIP_KERNEL 1983 default "0x00080000" 1984 help 1985 This is the physical address in your flash memory the kernel will 1986 be linked for and stored to. This address is dependent on your 1987 own flash usage. 1988 1989config XIP_DEFLATED_DATA 1990 bool "Store kernel .data section compressed in ROM" 1991 depends on XIP_KERNEL 1992 select ZLIB_INFLATE 1993 help 1994 Before the kernel is actually executed, its .data section has to be 1995 copied to RAM from ROM. This option allows for storing that data 1996 in compressed form and decompressed to RAM rather than merely being 1997 copied, saving some precious ROM space. A possible drawback is a 1998 slightly longer boot delay. 1999 2000config KEXEC 2001 bool "Kexec system call (EXPERIMENTAL)" 2002 depends on (!SMP || PM_SLEEP_SMP) 2003 depends on !CPU_V7M 2004 select KEXEC_CORE 2005 help 2006 kexec is a system call that implements the ability to shutdown your 2007 current kernel, and to start another kernel. It is like a reboot 2008 but it is independent of the system firmware. And like a reboot 2009 you can start any kernel with it, not just Linux. 2010 2011 It is an ongoing process to be certain the hardware in a machine 2012 is properly shutdown, so do not be surprised if this code does not 2013 initially work for you. 2014 2015config ATAGS_PROC 2016 bool "Export atags in procfs" 2017 depends on ATAGS && KEXEC 2018 default y 2019 help 2020 Should the atags used to boot the kernel be exported in an "atags" 2021 file in procfs. Useful with kexec. 2022 2023config CRASH_DUMP 2024 bool "Build kdump crash kernel (EXPERIMENTAL)" 2025 help 2026 Generate crash dump after being started by kexec. This should 2027 be normally only set in special crash dump kernels which are 2028 loaded in the main kernel with kexec-tools into a specially 2029 reserved region and then later executed after a crash by 2030 kdump/kexec. The crash dump kernel must be compiled to a 2031 memory address not used by the main kernel 2032 2033 For more details see Documentation/admin-guide/kdump/kdump.rst 2034 2035config AUTO_ZRELADDR 2036 bool "Auto calculation of the decompressed kernel image address" 2037 help 2038 ZRELADDR is the physical address where the decompressed kernel 2039 image will be placed. If AUTO_ZRELADDR is selected, the address 2040 will be determined at run-time by masking the current IP with 2041 0xf8000000. This assumes the zImage being placed in the first 128MB 2042 from start of memory. 2043 2044config EFI_STUB 2045 bool 2046 2047config EFI 2048 bool "UEFI runtime support" 2049 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2050 select UCS2_STRING 2051 select EFI_PARAMS_FROM_FDT 2052 select EFI_STUB 2053 select EFI_ARMSTUB 2054 select EFI_RUNTIME_WRAPPERS 2055 ---help--- 2056 This option provides support for runtime services provided 2057 by UEFI firmware (such as non-volatile variables, realtime 2058 clock, and platform reset). A UEFI stub is also provided to 2059 allow the kernel to be booted as an EFI application. This 2060 is only useful for kernels that may run on systems that have 2061 UEFI firmware. 2062 2063config DMI 2064 bool "Enable support for SMBIOS (DMI) tables" 2065 depends on EFI 2066 default y 2067 help 2068 This enables SMBIOS/DMI feature for systems. 2069 2070 This option is only useful on systems that have UEFI firmware. 2071 However, even with this option, the resultant kernel should 2072 continue to boot on existing non-UEFI platforms. 2073 2074 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2075 i.e., the the practice of identifying the platform via DMI to 2076 decide whether certain workarounds for buggy hardware and/or 2077 firmware need to be enabled. This would require the DMI subsystem 2078 to be enabled much earlier than we do on ARM, which is non-trivial. 2079 2080endmenu 2081 2082menu "CPU Power Management" 2083 2084source "drivers/cpufreq/Kconfig" 2085 2086source "drivers/cpuidle/Kconfig" 2087 2088endmenu 2089 2090menu "Floating point emulation" 2091 2092comment "At least one emulation must be selected" 2093 2094config FPE_NWFPE 2095 bool "NWFPE math emulation" 2096 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2097 ---help--- 2098 Say Y to include the NWFPE floating point emulator in the kernel. 2099 This is necessary to run most binaries. Linux does not currently 2100 support floating point hardware so you need to say Y here even if 2101 your machine has an FPA or floating point co-processor podule. 2102 2103 You may say N here if you are going to load the Acorn FPEmulator 2104 early in the bootup. 2105 2106config FPE_NWFPE_XP 2107 bool "Support extended precision" 2108 depends on FPE_NWFPE 2109 help 2110 Say Y to include 80-bit support in the kernel floating-point 2111 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2112 Note that gcc does not generate 80-bit operations by default, 2113 so in most cases this option only enlarges the size of the 2114 floating point emulator without any good reason. 2115 2116 You almost surely want to say N here. 2117 2118config FPE_FASTFPE 2119 bool "FastFPE math emulation (EXPERIMENTAL)" 2120 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2121 ---help--- 2122 Say Y here to include the FAST floating point emulator in the kernel. 2123 This is an experimental much faster emulator which now also has full 2124 precision for the mantissa. It does not support any exceptions. 2125 It is very simple, and approximately 3-6 times faster than NWFPE. 2126 2127 It should be sufficient for most programs. It may be not suitable 2128 for scientific calculations, but you have to check this for yourself. 2129 If you do not feel you need a faster FP emulation you should better 2130 choose NWFPE. 2131 2132config VFP 2133 bool "VFP-format floating point maths" 2134 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2135 help 2136 Say Y to include VFP support code in the kernel. This is needed 2137 if your hardware includes a VFP unit. 2138 2139 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2140 release notes and additional status information. 2141 2142 Say N if your target does not have VFP hardware. 2143 2144config VFPv3 2145 bool 2146 depends on VFP 2147 default y if CPU_V7 2148 2149config NEON 2150 bool "Advanced SIMD (NEON) Extension support" 2151 depends on VFPv3 && CPU_V7 2152 help 2153 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2154 Extension. 2155 2156config KERNEL_MODE_NEON 2157 bool "Support for NEON in kernel mode" 2158 depends on NEON && AEABI 2159 help 2160 Say Y to include support for NEON in kernel mode. 2161 2162endmenu 2163 2164menu "Power management options" 2165 2166source "kernel/power/Kconfig" 2167 2168config ARCH_SUSPEND_POSSIBLE 2169 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2170 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2171 def_bool y 2172 2173config ARM_CPU_SUSPEND 2174 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2175 depends on ARCH_SUSPEND_POSSIBLE 2176 2177config ARCH_HIBERNATION_POSSIBLE 2178 bool 2179 depends on MMU 2180 default y if ARCH_SUSPEND_POSSIBLE 2181 2182endmenu 2183 2184source "drivers/firmware/Kconfig" 2185 2186if CRYPTO 2187source "arch/arm/crypto/Kconfig" 2188endif 2189 2190source "arch/arm/kvm/Kconfig" 2191