1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_PHYS_TO_DMA 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_MIGHT_HAVE_PC_PARPORT 32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select CLONE_BACKWARDS 47 select CPU_PM if SUSPEND || CPU_IDLE 48 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 49 select DMA_DECLARE_COHERENT 50 select DMA_GLOBAL_POOL if !MMU 51 select DMA_OPS 52 select DMA_NONCOHERENT_MMAP if MMU 53 select EDAC_SUPPORT 54 select EDAC_ATOMIC_SCRUB 55 select GENERIC_ALLOCATOR 56 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 57 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 58 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 59 select GENERIC_IRQ_IPI if SMP 60 select GENERIC_CPU_AUTOPROBE 61 select GENERIC_EARLY_IOREMAP 62 select GENERIC_IDLE_POLL_SETUP 63 select GENERIC_IRQ_MULTI_HANDLER 64 select GENERIC_IRQ_PROBE 65 select GENERIC_IRQ_SHOW 66 select GENERIC_IRQ_SHOW_LEVEL 67 select GENERIC_LIB_DEVMEM_IS_ALLOWED 68 select GENERIC_PCI_IOMAP 69 select GENERIC_SCHED_CLOCK 70 select GENERIC_SMP_IDLE_THREAD 71 select HARDIRQS_SW_RESEND 72 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 73 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 74 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 75 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 76 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 77 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 78 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 79 select HAVE_ARCH_MMAP_RND_BITS if MMU 80 select HAVE_ARCH_PFN_VALID 81 select HAVE_ARCH_SECCOMP 82 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 83 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 84 select HAVE_ARCH_TRACEHOOK 85 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 86 select HAVE_ARM_SMCCC if CPU_V7 87 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 88 select HAVE_CONTEXT_TRACKING_USER 89 select HAVE_C_RECORDMCOUNT 90 select HAVE_BUILDTIME_MCOUNT_SORT 91 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 92 select HAVE_DMA_CONTIGUOUS if MMU 93 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 94 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 95 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 96 select HAVE_EXIT_THREAD 97 select HAVE_FAST_GUP if ARM_LPAE 98 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 99 select HAVE_FUNCTION_GRAPH_TRACER 100 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 101 select HAVE_GCC_PLUGINS 102 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 103 select HAVE_IRQ_TIME_ACCOUNTING 104 select HAVE_KERNEL_GZIP 105 select HAVE_KERNEL_LZ4 106 select HAVE_KERNEL_LZMA 107 select HAVE_KERNEL_LZO 108 select HAVE_KERNEL_XZ 109 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 110 select HAVE_KRETPROBES if HAVE_KPROBES 111 select HAVE_MOD_ARCH_SPECIFIC 112 select HAVE_NMI 113 select HAVE_OPTPROBES if !THUMB2_KERNEL 114 select HAVE_PERF_EVENTS 115 select HAVE_PERF_REGS 116 select HAVE_PERF_USER_STACK_DUMP 117 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 118 select HAVE_REGS_AND_STACK_ACCESS_API 119 select HAVE_RSEQ 120 select HAVE_STACKPROTECTOR 121 select HAVE_SYSCALL_TRACEPOINTS 122 select HAVE_UID16 123 select HAVE_VIRT_CPU_ACCOUNTING_GEN 124 select IRQ_FORCED_THREADING 125 select MODULES_USE_ELF_REL 126 select NEED_DMA_MAP_STATE 127 select OF_EARLY_FLATTREE if OF 128 select OLD_SIGACTION 129 select OLD_SIGSUSPEND3 130 select PCI_SYSCALL if PCI 131 select PERF_USE_VMALLOC 132 select RTC_LIB 133 select SYS_SUPPORTS_APM_EMULATION 134 select THREAD_INFO_IN_TASK 135 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 136 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 137 # Above selects are sorted alphabetically; please add new ones 138 # according to that. Thanks. 139 help 140 The ARM series is a line of low-power-consumption RISC chip designs 141 licensed by ARM Ltd and targeted at embedded applications and 142 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 143 manufactured, but legacy ARM-based PC hardware remains popular in 144 Europe. There is an ARM Linux project with a web page at 145 <http://www.arm.linux.org.uk/>. 146 147config ARM_HAS_GROUP_RELOCS 148 def_bool y 149 depends on !LD_IS_LLD || LLD_VERSION >= 140000 150 depends on !COMPILE_TEST 151 help 152 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 153 relocations, which have been around for a long time, but were not 154 supported in LLD until version 14. The combined range is -/+ 256 MiB, 155 which is usually sufficient, but not for allyesconfig, so we disable 156 this feature when doing compile testing. 157 158config ARM_HAS_SG_CHAIN 159 bool 160 161config ARM_DMA_USE_IOMMU 162 bool 163 select ARM_HAS_SG_CHAIN 164 select NEED_SG_DMA_LENGTH 165 166if ARM_DMA_USE_IOMMU 167 168config ARM_DMA_IOMMU_ALIGNMENT 169 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 170 range 4 9 171 default 8 172 help 173 DMA mapping framework by default aligns all buffers to the smallest 174 PAGE_SIZE order which is greater than or equal to the requested buffer 175 size. This works well for buffers up to a few hundreds kilobytes, but 176 for larger buffers it just a waste of address space. Drivers which has 177 relatively small addressing window (like 64Mib) might run out of 178 virtual space with just a few allocations. 179 180 With this parameter you can specify the maximum PAGE_SIZE order for 181 DMA IOMMU buffers. Larger buffers will be aligned only to this 182 specified order. The order is expressed as a power of two multiplied 183 by the PAGE_SIZE. 184 185endif 186 187config SYS_SUPPORTS_APM_EMULATION 188 bool 189 190config HAVE_TCM 191 bool 192 select GENERIC_ALLOCATOR 193 194config HAVE_PROC_CPU 195 bool 196 197config NO_IOPORT_MAP 198 bool 199 200config SBUS 201 bool 202 203config STACKTRACE_SUPPORT 204 bool 205 default y 206 207config LOCKDEP_SUPPORT 208 bool 209 default y 210 211config ARCH_HAS_ILOG2_U32 212 bool 213 214config ARCH_HAS_ILOG2_U64 215 bool 216 217config ARCH_HAS_BANDGAP 218 bool 219 220config FIX_EARLYCON_MEM 221 def_bool y if MMU 222 223config GENERIC_HWEIGHT 224 bool 225 default y 226 227config GENERIC_CALIBRATE_DELAY 228 bool 229 default y 230 231config ARCH_MAY_HAVE_PC_FDC 232 bool 233 234config ARCH_SUPPORTS_UPROBES 235 def_bool y 236 237config GENERIC_ISA_DMA 238 bool 239 240config FIQ 241 bool 242 243config ARCH_MTD_XIP 244 bool 245 246config ARM_PATCH_PHYS_VIRT 247 bool "Patch physical to virtual translations at runtime" if EMBEDDED 248 default y 249 depends on !XIP_KERNEL && MMU 250 help 251 Patch phys-to-virt and virt-to-phys translation functions at 252 boot and module load time according to the position of the 253 kernel in system memory. 254 255 This can only be used with non-XIP MMU kernels where the base 256 of physical memory is at a 2 MiB boundary. 257 258 Only disable this option if you know that you do not require 259 this feature (eg, building a kernel for a single machine) and 260 you need to shrink the kernel to the minimal size. 261 262config NEED_MACH_IO_H 263 bool 264 help 265 Select this when mach/io.h is required to provide special 266 definitions for this platform. The need for mach/io.h should 267 be avoided when possible. 268 269config NEED_MACH_MEMORY_H 270 bool 271 help 272 Select this when mach/memory.h is required to provide special 273 definitions for this platform. The need for mach/memory.h should 274 be avoided when possible. 275 276config PHYS_OFFSET 277 hex "Physical address of main memory" if MMU 278 depends on !ARM_PATCH_PHYS_VIRT 279 default DRAM_BASE if !MMU 280 default 0x00000000 if ARCH_FOOTBRIDGE 281 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 282 default 0x30000000 if ARCH_S3C24XX 283 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 284 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 285 default 0 286 help 287 Please provide the physical address corresponding to the 288 location of main memory in your system. 289 290config GENERIC_BUG 291 def_bool y 292 depends on BUG 293 294config PGTABLE_LEVELS 295 int 296 default 3 if ARM_LPAE 297 default 2 298 299menu "System Type" 300 301config MMU 302 bool "MMU-based Paged Memory Management Support" 303 default y 304 help 305 Select if you want MMU-based virtualised addressing space 306 support by paged memory management. If unsure, say 'Y'. 307 308config ARM_SINGLE_ARMV7M 309 def_bool !MMU 310 select ARM_NVIC 311 select AUTO_ZRELADDR 312 select TIMER_OF 313 select COMMON_CLK 314 select CPU_V7M 315 select NO_IOPORT_MAP 316 select SPARSE_IRQ 317 select USE_OF 318 319config ARCH_MMAP_RND_BITS_MIN 320 default 8 321 322config ARCH_MMAP_RND_BITS_MAX 323 default 14 if PAGE_OFFSET=0x40000000 324 default 15 if PAGE_OFFSET=0x80000000 325 default 16 326 327# 328# The "ARM system type" choice list is ordered alphabetically by option 329# text. Please add new entries in the option alphabetic order. 330# 331choice 332 prompt "ARM system type" 333 depends on MMU 334 default ARCH_MULTIPLATFORM 335 336config ARCH_MULTIPLATFORM 337 bool "Allow multiple platforms to be selected" 338 select ARCH_FLATMEM_ENABLE 339 select ARCH_SPARSEMEM_ENABLE 340 select ARCH_SELECT_MEMORY_MODEL 341 select ARM_HAS_SG_CHAIN 342 select ARM_PATCH_PHYS_VIRT 343 select AUTO_ZRELADDR 344 select TIMER_OF 345 select COMMON_CLK 346 select HAVE_PCI 347 select PCI_DOMAINS_GENERIC if PCI 348 select SPARSE_IRQ 349 select USE_OF 350 351config ARCH_FOOTBRIDGE 352 bool "FootBridge" 353 depends on CPU_LITTLE_ENDIAN 354 depends on ATAGS 355 select CPU_SA110 356 select FOOTBRIDGE 357 select NEED_MACH_MEMORY_H 358 help 359 Support for systems based on the DC21285 companion chip 360 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 361 362config ARCH_RPC 363 bool "RiscPC" 364 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 365 depends on CPU_LITTLE_ENDIAN 366 depends on ATAGS 367 select ARCH_ACORN 368 select ARCH_MAY_HAVE_PC_FDC 369 select ARCH_SPARSEMEM_ENABLE 370 select ARM_HAS_SG_CHAIN 371 select CPU_SA110 372 select FIQ 373 select HAVE_PATA_PLATFORM 374 select ISA_DMA_API 375 select LEGACY_TIMER_TICK 376 select NEED_MACH_IO_H 377 select NEED_MACH_MEMORY_H 378 select NO_IOPORT_MAP 379 help 380 On the Acorn Risc-PC, Linux can support the internal IDE disk and 381 CD-ROM interface, serial and parallel port, and the floppy drive. 382 383config ARCH_SA1100 384 bool "SA1100-based" 385 depends on CPU_LITTLE_ENDIAN 386 depends on ATAGS 387 select ARCH_MTD_XIP 388 select ARCH_SPARSEMEM_ENABLE 389 select CLKSRC_MMIO 390 select CLKSRC_PXA 391 select TIMER_OF if OF 392 select COMMON_CLK 393 select CPU_FREQ 394 select CPU_SA1100 395 select GPIOLIB 396 select IRQ_DOMAIN 397 select ISA 398 select NEED_MACH_MEMORY_H 399 select SPARSE_IRQ 400 help 401 Support for StrongARM 11x0 based boards. 402 403endchoice 404 405menu "Multiple platform selection" 406 depends on ARCH_MULTIPLATFORM 407 408comment "CPU Core family selection" 409 410config ARCH_MULTI_V4 411 bool "ARMv4 based platforms (FA526)" 412 depends on !ARCH_MULTI_V6_V7 413 select ARCH_MULTI_V4_V5 414 select CPU_FA526 415 416config ARCH_MULTI_V4T 417 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 418 depends on !ARCH_MULTI_V6_V7 419 select ARCH_MULTI_V4_V5 420 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 421 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 422 CPU_ARM925T || CPU_ARM940T) 423 424config ARCH_MULTI_V5 425 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 426 depends on !ARCH_MULTI_V6_V7 427 select ARCH_MULTI_V4_V5 428 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 429 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 430 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 431 432config ARCH_MULTI_V4_V5 433 bool 434 435config ARCH_MULTI_V6 436 bool "ARMv6 based platforms (ARM11)" 437 select ARCH_MULTI_V6_V7 438 select CPU_V6K 439 440config ARCH_MULTI_V7 441 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 442 default y 443 select ARCH_MULTI_V6_V7 444 select CPU_V7 445 select HAVE_SMP 446 447config ARCH_MULTI_V6_V7 448 bool 449 select MIGHT_HAVE_CACHE_L2X0 450 451config ARCH_MULTI_CPU_AUTO 452 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 453 select ARCH_MULTI_V5 454 455endmenu 456 457config ARCH_VIRT 458 bool "Dummy Virtual Machine" 459 depends on ARCH_MULTI_V7 460 select ARM_AMBA 461 select ARM_GIC 462 select ARM_GIC_V2M if PCI 463 select ARM_GIC_V3 464 select ARM_GIC_V3_ITS if PCI 465 select ARM_PSCI 466 select HAVE_ARM_ARCH_TIMER 467 468config ARCH_AIROHA 469 bool "Airoha SoC Support" 470 depends on ARCH_MULTI_V7 471 select ARM_AMBA 472 select ARM_GIC 473 select ARM_GIC_V3 474 select ARM_PSCI 475 select HAVE_ARM_ARCH_TIMER 476 select COMMON_CLK 477 help 478 Support for Airoha EN7523 SoCs 479 480# 481# This is sorted alphabetically by mach-* pathname. However, plat-* 482# Kconfigs may be included either alphabetically (according to the 483# plat- suffix) or along side the corresponding mach-* source. 484# 485source "arch/arm/mach-actions/Kconfig" 486 487source "arch/arm/mach-alpine/Kconfig" 488 489source "arch/arm/mach-artpec/Kconfig" 490 491source "arch/arm/mach-asm9260/Kconfig" 492 493source "arch/arm/mach-aspeed/Kconfig" 494 495source "arch/arm/mach-at91/Kconfig" 496 497source "arch/arm/mach-axxia/Kconfig" 498 499source "arch/arm/mach-bcm/Kconfig" 500 501source "arch/arm/mach-berlin/Kconfig" 502 503source "arch/arm/mach-clps711x/Kconfig" 504 505source "arch/arm/mach-cns3xxx/Kconfig" 506 507source "arch/arm/mach-davinci/Kconfig" 508 509source "arch/arm/mach-digicolor/Kconfig" 510 511source "arch/arm/mach-dove/Kconfig" 512 513source "arch/arm/mach-ep93xx/Kconfig" 514 515source "arch/arm/mach-exynos/Kconfig" 516 517source "arch/arm/mach-footbridge/Kconfig" 518 519source "arch/arm/mach-gemini/Kconfig" 520 521source "arch/arm/mach-highbank/Kconfig" 522 523source "arch/arm/mach-hisi/Kconfig" 524 525source "arch/arm/mach-hpe/Kconfig" 526 527source "arch/arm/mach-imx/Kconfig" 528 529source "arch/arm/mach-iop32x/Kconfig" 530 531source "arch/arm/mach-ixp4xx/Kconfig" 532 533source "arch/arm/mach-keystone/Kconfig" 534 535source "arch/arm/mach-lpc32xx/Kconfig" 536 537source "arch/arm/mach-mediatek/Kconfig" 538 539source "arch/arm/mach-meson/Kconfig" 540 541source "arch/arm/mach-milbeaut/Kconfig" 542 543source "arch/arm/mach-mmp/Kconfig" 544 545source "arch/arm/mach-moxart/Kconfig" 546 547source "arch/arm/mach-mstar/Kconfig" 548 549source "arch/arm/mach-mv78xx0/Kconfig" 550 551source "arch/arm/mach-mvebu/Kconfig" 552 553source "arch/arm/mach-mxs/Kconfig" 554 555source "arch/arm/mach-nomadik/Kconfig" 556 557source "arch/arm/mach-npcm/Kconfig" 558 559source "arch/arm/mach-nspire/Kconfig" 560 561source "arch/arm/mach-omap1/Kconfig" 562 563source "arch/arm/mach-omap2/Kconfig" 564 565source "arch/arm/mach-orion5x/Kconfig" 566 567source "arch/arm/mach-oxnas/Kconfig" 568 569source "arch/arm/mach-pxa/Kconfig" 570 571source "arch/arm/mach-qcom/Kconfig" 572 573source "arch/arm/mach-rda/Kconfig" 574 575source "arch/arm/mach-realtek/Kconfig" 576 577source "arch/arm/mach-rockchip/Kconfig" 578 579source "arch/arm/mach-s3c/Kconfig" 580 581source "arch/arm/mach-s5pv210/Kconfig" 582 583source "arch/arm/mach-sa1100/Kconfig" 584 585source "arch/arm/mach-shmobile/Kconfig" 586 587source "arch/arm/mach-socfpga/Kconfig" 588 589source "arch/arm/mach-spear/Kconfig" 590 591source "arch/arm/mach-sti/Kconfig" 592 593source "arch/arm/mach-stm32/Kconfig" 594 595source "arch/arm/mach-sunplus/Kconfig" 596 597source "arch/arm/mach-sunxi/Kconfig" 598 599source "arch/arm/mach-tegra/Kconfig" 600 601source "arch/arm/mach-uniphier/Kconfig" 602 603source "arch/arm/mach-ux500/Kconfig" 604 605source "arch/arm/mach-versatile/Kconfig" 606 607source "arch/arm/mach-vt8500/Kconfig" 608 609source "arch/arm/mach-zynq/Kconfig" 610 611# ARMv7-M architecture 612config ARCH_LPC18XX 613 bool "NXP LPC18xx/LPC43xx" 614 depends on ARM_SINGLE_ARMV7M 615 select ARCH_HAS_RESET_CONTROLLER 616 select ARM_AMBA 617 select CLKSRC_LPC32XX 618 select PINCTRL 619 help 620 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 621 high performance microcontrollers. 622 623config ARCH_MPS2 624 bool "ARM MPS2 platform" 625 depends on ARM_SINGLE_ARMV7M 626 select ARM_AMBA 627 select CLKSRC_MPS2 628 help 629 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 630 with a range of available cores like Cortex-M3/M4/M7. 631 632 Please, note that depends which Application Note is used memory map 633 for the platform may vary, so adjustment of RAM base might be needed. 634 635# Definitions to make life easier 636config ARCH_ACORN 637 bool 638 639config PLAT_ORION 640 bool 641 select CLKSRC_MMIO 642 select COMMON_CLK 643 select GENERIC_IRQ_CHIP 644 select IRQ_DOMAIN 645 646config PLAT_ORION_LEGACY 647 bool 648 select PLAT_ORION 649 650config PLAT_VERSATILE 651 bool 652 653source "arch/arm/mm/Kconfig" 654 655config IWMMXT 656 bool "Enable iWMMXt support" 657 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 658 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 659 help 660 Enable support for iWMMXt context switching at run time if 661 running on a CPU that supports it. 662 663if !MMU 664source "arch/arm/Kconfig-nommu" 665endif 666 667config PJ4B_ERRATA_4742 668 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 669 depends on CPU_PJ4B && MACH_ARMADA_370 670 default y 671 help 672 When coming out of either a Wait for Interrupt (WFI) or a Wait for 673 Event (WFE) IDLE states, a specific timing sensitivity exists between 674 the retiring WFI/WFE instructions and the newly issued subsequent 675 instructions. This sensitivity can result in a CPU hang scenario. 676 Workaround: 677 The software must insert either a Data Synchronization Barrier (DSB) 678 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 679 instruction 680 681config ARM_ERRATA_326103 682 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 683 depends on CPU_V6 684 help 685 Executing a SWP instruction to read-only memory does not set bit 11 686 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 687 treat the access as a read, preventing a COW from occurring and 688 causing the faulting task to livelock. 689 690config ARM_ERRATA_411920 691 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 692 depends on CPU_V6 || CPU_V6K 693 help 694 Invalidation of the Instruction Cache operation can 695 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 696 It does not affect the MPCore. This option enables the ARM Ltd. 697 recommended workaround. 698 699config ARM_ERRATA_430973 700 bool "ARM errata: Stale prediction on replaced interworking branch" 701 depends on CPU_V7 702 help 703 This option enables the workaround for the 430973 Cortex-A8 704 r1p* erratum. If a code sequence containing an ARM/Thumb 705 interworking branch is replaced with another code sequence at the 706 same virtual address, whether due to self-modifying code or virtual 707 to physical address re-mapping, Cortex-A8 does not recover from the 708 stale interworking branch prediction. This results in Cortex-A8 709 executing the new code sequence in the incorrect ARM or Thumb state. 710 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 711 and also flushes the branch target cache at every context switch. 712 Note that setting specific bits in the ACTLR register may not be 713 available in non-secure mode. 714 715config ARM_ERRATA_458693 716 bool "ARM errata: Processor deadlock when a false hazard is created" 717 depends on CPU_V7 718 depends on !ARCH_MULTIPLATFORM 719 help 720 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 721 erratum. For very specific sequences of memory operations, it is 722 possible for a hazard condition intended for a cache line to instead 723 be incorrectly associated with a different cache line. This false 724 hazard might then cause a processor deadlock. The workaround enables 725 the L1 caching of the NEON accesses and disables the PLD instruction 726 in the ACTLR register. Note that setting specific bits in the ACTLR 727 register may not be available in non-secure mode. 728 729config ARM_ERRATA_460075 730 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 731 depends on CPU_V7 732 depends on !ARCH_MULTIPLATFORM 733 help 734 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 735 erratum. Any asynchronous access to the L2 cache may encounter a 736 situation in which recent store transactions to the L2 cache are lost 737 and overwritten with stale memory contents from external memory. The 738 workaround disables the write-allocate mode for the L2 cache via the 739 ACTLR register. Note that setting specific bits in the ACTLR register 740 may not be available in non-secure mode. 741 742config ARM_ERRATA_742230 743 bool "ARM errata: DMB operation may be faulty" 744 depends on CPU_V7 && SMP 745 depends on !ARCH_MULTIPLATFORM 746 help 747 This option enables the workaround for the 742230 Cortex-A9 748 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 749 between two write operations may not ensure the correct visibility 750 ordering of the two writes. This workaround sets a specific bit in 751 the diagnostic register of the Cortex-A9 which causes the DMB 752 instruction to behave as a DSB, ensuring the correct behaviour of 753 the two writes. 754 755config ARM_ERRATA_742231 756 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 757 depends on CPU_V7 && SMP 758 depends on !ARCH_MULTIPLATFORM 759 help 760 This option enables the workaround for the 742231 Cortex-A9 761 (r2p0..r2p2) erratum. Under certain conditions, specific to the 762 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 763 accessing some data located in the same cache line, may get corrupted 764 data due to bad handling of the address hazard when the line gets 765 replaced from one of the CPUs at the same time as another CPU is 766 accessing it. This workaround sets specific bits in the diagnostic 767 register of the Cortex-A9 which reduces the linefill issuing 768 capabilities of the processor. 769 770config ARM_ERRATA_643719 771 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 772 depends on CPU_V7 && SMP 773 default y 774 help 775 This option enables the workaround for the 643719 Cortex-A9 (prior to 776 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 777 register returns zero when it should return one. The workaround 778 corrects this value, ensuring cache maintenance operations which use 779 it behave as intended and avoiding data corruption. 780 781config ARM_ERRATA_720789 782 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 783 depends on CPU_V7 784 help 785 This option enables the workaround for the 720789 Cortex-A9 (prior to 786 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 787 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 788 As a consequence of this erratum, some TLB entries which should be 789 invalidated are not, resulting in an incoherency in the system page 790 tables. The workaround changes the TLB flushing routines to invalidate 791 entries regardless of the ASID. 792 793config ARM_ERRATA_743622 794 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 795 depends on CPU_V7 796 depends on !ARCH_MULTIPLATFORM 797 help 798 This option enables the workaround for the 743622 Cortex-A9 799 (r2p*) erratum. Under very rare conditions, a faulty 800 optimisation in the Cortex-A9 Store Buffer may lead to data 801 corruption. This workaround sets a specific bit in the diagnostic 802 register of the Cortex-A9 which disables the Store Buffer 803 optimisation, preventing the defect from occurring. This has no 804 visible impact on the overall performance or power consumption of the 805 processor. 806 807config ARM_ERRATA_751472 808 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 809 depends on CPU_V7 810 depends on !ARCH_MULTIPLATFORM 811 help 812 This option enables the workaround for the 751472 Cortex-A9 (prior 813 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 814 completion of a following broadcasted operation if the second 815 operation is received by a CPU before the ICIALLUIS has completed, 816 potentially leading to corrupted entries in the cache or TLB. 817 818config ARM_ERRATA_754322 819 bool "ARM errata: possible faulty MMU translations following an ASID switch" 820 depends on CPU_V7 821 help 822 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 823 r3p*) erratum. A speculative memory access may cause a page table walk 824 which starts prior to an ASID switch but completes afterwards. This 825 can populate the micro-TLB with a stale entry which may be hit with 826 the new ASID. This workaround places two dsb instructions in the mm 827 switching code so that no page table walks can cross the ASID switch. 828 829config ARM_ERRATA_754327 830 bool "ARM errata: no automatic Store Buffer drain" 831 depends on CPU_V7 && SMP 832 help 833 This option enables the workaround for the 754327 Cortex-A9 (prior to 834 r2p0) erratum. The Store Buffer does not have any automatic draining 835 mechanism and therefore a livelock may occur if an external agent 836 continuously polls a memory location waiting to observe an update. 837 This workaround defines cpu_relax() as smp_mb(), preventing correctly 838 written polling loops from denying visibility of updates to memory. 839 840config ARM_ERRATA_364296 841 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 842 depends on CPU_V6 843 help 844 This options enables the workaround for the 364296 ARM1136 845 r0p2 erratum (possible cache data corruption with 846 hit-under-miss enabled). It sets the undocumented bit 31 in 847 the auxiliary control register and the FI bit in the control 848 register, thus disabling hit-under-miss without putting the 849 processor into full low interrupt latency mode. ARM11MPCore 850 is not affected. 851 852config ARM_ERRATA_764369 853 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 854 depends on CPU_V7 && SMP 855 help 856 This option enables the workaround for erratum 764369 857 affecting Cortex-A9 MPCore with two or more processors (all 858 current revisions). Under certain timing circumstances, a data 859 cache line maintenance operation by MVA targeting an Inner 860 Shareable memory region may fail to proceed up to either the 861 Point of Coherency or to the Point of Unification of the 862 system. This workaround adds a DSB instruction before the 863 relevant cache maintenance functions and sets a specific bit 864 in the diagnostic control register of the SCU. 865 866config ARM_ERRATA_764319 867 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 868 depends on CPU_V7 869 help 870 This option enables the workaround for the 764319 Cortex A-9 erratum. 871 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 872 unexpected Undefined Instruction exception when the DBGSWENABLE 873 external pin is set to 0, even when the CP14 accesses are performed 874 from a privileged mode. This work around catches the exception in a 875 way the kernel does not stop execution. 876 877config ARM_ERRATA_775420 878 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 879 depends on CPU_V7 880 help 881 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 882 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 883 operation aborts with MMU exception, it might cause the processor 884 to deadlock. This workaround puts DSB before executing ISB if 885 an abort may occur on cache maintenance. 886 887config ARM_ERRATA_798181 888 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 889 depends on CPU_V7 && SMP 890 help 891 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 892 adequately shooting down all use of the old entries. This 893 option enables the Linux kernel workaround for this erratum 894 which sends an IPI to the CPUs that are running the same ASID 895 as the one being invalidated. 896 897config ARM_ERRATA_773022 898 bool "ARM errata: incorrect instructions may be executed from loop buffer" 899 depends on CPU_V7 900 help 901 This option enables the workaround for the 773022 Cortex-A15 902 (up to r0p4) erratum. In certain rare sequences of code, the 903 loop buffer may deliver incorrect instructions. This 904 workaround disables the loop buffer to avoid the erratum. 905 906config ARM_ERRATA_818325_852422 907 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 908 depends on CPU_V7 909 help 910 This option enables the workaround for: 911 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 912 instruction might deadlock. Fixed in r0p1. 913 - Cortex-A12 852422: Execution of a sequence of instructions might 914 lead to either a data corruption or a CPU deadlock. Not fixed in 915 any Cortex-A12 cores yet. 916 This workaround for all both errata involves setting bit[12] of the 917 Feature Register. This bit disables an optimisation applied to a 918 sequence of 2 instructions that use opposing condition codes. 919 920config ARM_ERRATA_821420 921 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 922 depends on CPU_V7 923 help 924 This option enables the workaround for the 821420 Cortex-A12 925 (all revs) erratum. In very rare timing conditions, a sequence 926 of VMOV to Core registers instructions, for which the second 927 one is in the shadow of a branch or abort, can lead to a 928 deadlock when the VMOV instructions are issued out-of-order. 929 930config ARM_ERRATA_825619 931 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 932 depends on CPU_V7 933 help 934 This option enables the workaround for the 825619 Cortex-A12 935 (all revs) erratum. Within rare timing constraints, executing a 936 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 937 and Device/Strongly-Ordered loads and stores might cause deadlock 938 939config ARM_ERRATA_857271 940 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 941 depends on CPU_V7 942 help 943 This option enables the workaround for the 857271 Cortex-A12 944 (all revs) erratum. Under very rare timing conditions, the CPU might 945 hang. The workaround is expected to have a < 1% performance impact. 946 947config ARM_ERRATA_852421 948 bool "ARM errata: A17: DMB ST might fail to create order between stores" 949 depends on CPU_V7 950 help 951 This option enables the workaround for the 852421 Cortex-A17 952 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 953 execution of a DMB ST instruction might fail to properly order 954 stores from GroupA and stores from GroupB. 955 956config ARM_ERRATA_852423 957 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 958 depends on CPU_V7 959 help 960 This option enables the workaround for: 961 - Cortex-A17 852423: Execution of a sequence of instructions might 962 lead to either a data corruption or a CPU deadlock. Not fixed in 963 any Cortex-A17 cores yet. 964 This is identical to Cortex-A12 erratum 852422. It is a separate 965 config option from the A12 erratum due to the way errata are checked 966 for and handled. 967 968config ARM_ERRATA_857272 969 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 970 depends on CPU_V7 971 help 972 This option enables the workaround for the 857272 Cortex-A17 erratum. 973 This erratum is not known to be fixed in any A17 revision. 974 This is identical to Cortex-A12 erratum 857271. It is a separate 975 config option from the A12 erratum due to the way errata are checked 976 for and handled. 977 978endmenu 979 980source "arch/arm/common/Kconfig" 981 982menu "Bus support" 983 984config ISA 985 bool 986 help 987 Find out whether you have ISA slots on your motherboard. ISA is the 988 name of a bus system, i.e. the way the CPU talks to the other stuff 989 inside your box. Other bus systems are PCI, EISA, MicroChannel 990 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 991 newer boards don't support it. If you have ISA, say Y, otherwise N. 992 993# Select ISA DMA controller support 994config ISA_DMA 995 bool 996 select ISA_DMA_API 997 998# Select ISA DMA interface 999config ISA_DMA_API 1000 bool 1001 1002config PCI_NANOENGINE 1003 bool "BSE nanoEngine PCI support" 1004 depends on SA1100_NANOENGINE 1005 help 1006 Enable PCI on the BSE nanoEngine board. 1007 1008config ARM_ERRATA_814220 1009 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1010 depends on CPU_V7 1011 help 1012 The v7 ARM states that all cache and branch predictor maintenance 1013 operations that do not specify an address execute, relative to 1014 each other, in program order. 1015 However, because of this erratum, an L2 set/way cache maintenance 1016 operation can overtake an L1 set/way cache maintenance operation. 1017 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1018 r0p4, r0p5. 1019 1020endmenu 1021 1022menu "Kernel Features" 1023 1024config HAVE_SMP 1025 bool 1026 help 1027 This option should be selected by machines which have an SMP- 1028 capable CPU. 1029 1030 The only effect of this option is to make the SMP-related 1031 options available to the user for configuration. 1032 1033config SMP 1034 bool "Symmetric Multi-Processing" 1035 depends on CPU_V6K || CPU_V7 1036 depends on HAVE_SMP 1037 depends on MMU || ARM_MPU 1038 select IRQ_WORK 1039 help 1040 This enables support for systems with more than one CPU. If you have 1041 a system with only one CPU, say N. If you have a system with more 1042 than one CPU, say Y. 1043 1044 If you say N here, the kernel will run on uni- and multiprocessor 1045 machines, but will use only one CPU of a multiprocessor machine. If 1046 you say Y here, the kernel will run on many, but not all, 1047 uniprocessor machines. On a uniprocessor machine, the kernel 1048 will run faster if you say N here. 1049 1050 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1051 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1052 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1053 1054 If you don't know what to do here, say N. 1055 1056config SMP_ON_UP 1057 bool "Allow booting SMP kernel on uniprocessor systems" 1058 depends on SMP && !XIP_KERNEL && MMU 1059 default y 1060 help 1061 SMP kernels contain instructions which fail on non-SMP processors. 1062 Enabling this option allows the kernel to modify itself to make 1063 these instructions safe. Disabling it allows about 1K of space 1064 savings. 1065 1066 If you don't know what to do here, say Y. 1067 1068 1069config CURRENT_POINTER_IN_TPIDRURO 1070 def_bool y 1071 depends on CPU_32v6K && !CPU_V6 1072 1073config IRQSTACKS 1074 def_bool y 1075 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1076 select HAVE_SOFTIRQ_ON_OWN_STACK 1077 1078config ARM_CPU_TOPOLOGY 1079 bool "Support cpu topology definition" 1080 depends on SMP && CPU_V7 1081 default y 1082 help 1083 Support ARM cpu topology definition. The MPIDR register defines 1084 affinity between processors which is then used to describe the cpu 1085 topology of an ARM System. 1086 1087config SCHED_MC 1088 bool "Multi-core scheduler support" 1089 depends on ARM_CPU_TOPOLOGY 1090 help 1091 Multi-core scheduler support improves the CPU scheduler's decision 1092 making when dealing with multi-core CPU chips at a cost of slightly 1093 increased overhead in some places. If unsure say N here. 1094 1095config SCHED_SMT 1096 bool "SMT scheduler support" 1097 depends on ARM_CPU_TOPOLOGY 1098 help 1099 Improves the CPU scheduler's decision making when dealing with 1100 MultiThreading at a cost of slightly increased overhead in some 1101 places. If unsure say N here. 1102 1103config HAVE_ARM_SCU 1104 bool 1105 help 1106 This option enables support for the ARM snoop control unit 1107 1108config HAVE_ARM_ARCH_TIMER 1109 bool "Architected timer support" 1110 depends on CPU_V7 1111 select ARM_ARCH_TIMER 1112 help 1113 This option enables support for the ARM architected timer 1114 1115config HAVE_ARM_TWD 1116 bool 1117 help 1118 This options enables support for the ARM timer and watchdog unit 1119 1120config MCPM 1121 bool "Multi-Cluster Power Management" 1122 depends on CPU_V7 && SMP 1123 help 1124 This option provides the common power management infrastructure 1125 for (multi-)cluster based systems, such as big.LITTLE based 1126 systems. 1127 1128config MCPM_QUAD_CLUSTER 1129 bool 1130 depends on MCPM 1131 help 1132 To avoid wasting resources unnecessarily, MCPM only supports up 1133 to 2 clusters by default. 1134 Platforms with 3 or 4 clusters that use MCPM must select this 1135 option to allow the additional clusters to be managed. 1136 1137config BIG_LITTLE 1138 bool "big.LITTLE support (Experimental)" 1139 depends on CPU_V7 && SMP 1140 select MCPM 1141 help 1142 This option enables support selections for the big.LITTLE 1143 system architecture. 1144 1145config BL_SWITCHER 1146 bool "big.LITTLE switcher support" 1147 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1148 select CPU_PM 1149 help 1150 The big.LITTLE "switcher" provides the core functionality to 1151 transparently handle transition between a cluster of A15's 1152 and a cluster of A7's in a big.LITTLE system. 1153 1154config BL_SWITCHER_DUMMY_IF 1155 tristate "Simple big.LITTLE switcher user interface" 1156 depends on BL_SWITCHER && DEBUG_KERNEL 1157 help 1158 This is a simple and dummy char dev interface to control 1159 the big.LITTLE switcher core code. It is meant for 1160 debugging purposes only. 1161 1162choice 1163 prompt "Memory split" 1164 depends on MMU 1165 default VMSPLIT_3G 1166 help 1167 Select the desired split between kernel and user memory. 1168 1169 If you are not absolutely sure what you are doing, leave this 1170 option alone! 1171 1172 config VMSPLIT_3G 1173 bool "3G/1G user/kernel split" 1174 config VMSPLIT_3G_OPT 1175 depends on !ARM_LPAE 1176 bool "3G/1G user/kernel split (for full 1G low memory)" 1177 config VMSPLIT_2G 1178 bool "2G/2G user/kernel split" 1179 config VMSPLIT_1G 1180 bool "1G/3G user/kernel split" 1181endchoice 1182 1183config PAGE_OFFSET 1184 hex 1185 default PHYS_OFFSET if !MMU 1186 default 0x40000000 if VMSPLIT_1G 1187 default 0x80000000 if VMSPLIT_2G 1188 default 0xB0000000 if VMSPLIT_3G_OPT 1189 default 0xC0000000 1190 1191config KASAN_SHADOW_OFFSET 1192 hex 1193 depends on KASAN 1194 default 0x1f000000 if PAGE_OFFSET=0x40000000 1195 default 0x5f000000 if PAGE_OFFSET=0x80000000 1196 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1197 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1198 default 0xffffffff 1199 1200config NR_CPUS 1201 int "Maximum number of CPUs (2-32)" 1202 range 2 16 if DEBUG_KMAP_LOCAL 1203 range 2 32 if !DEBUG_KMAP_LOCAL 1204 depends on SMP 1205 default "4" 1206 help 1207 The maximum number of CPUs that the kernel can support. 1208 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1209 debugging is enabled, which uses half of the per-CPU fixmap 1210 slots as guard regions. 1211 1212config HOTPLUG_CPU 1213 bool "Support for hot-pluggable CPUs" 1214 depends on SMP 1215 select GENERIC_IRQ_MIGRATION 1216 help 1217 Say Y here to experiment with turning CPUs off and on. CPUs 1218 can be controlled through /sys/devices/system/cpu. 1219 1220config ARM_PSCI 1221 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1222 depends on HAVE_ARM_SMCCC 1223 select ARM_PSCI_FW 1224 help 1225 Say Y here if you want Linux to communicate with system firmware 1226 implementing the PSCI specification for CPU-centric power 1227 management operations described in ARM document number ARM DEN 1228 0022A ("Power State Coordination Interface System Software on 1229 ARM processors"). 1230 1231# The GPIO number here must be sorted by descending number. In case of 1232# a multiplatform kernel, we just want the highest value required by the 1233# selected platforms. 1234config ARCH_NR_GPIO 1235 int 1236 default 2048 if ARCH_INTEL_SOCFPGA 1237 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1238 ARCH_ZYNQ || ARCH_ASPEED 1239 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1240 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1241 default 416 if ARCH_SUNXI 1242 default 392 if ARCH_U8500 1243 default 352 if ARCH_VT8500 1244 default 288 if ARCH_ROCKCHIP 1245 default 264 if MACH_H4700 1246 default 0 1247 help 1248 Maximum number of GPIOs in the system. 1249 1250 If unsure, leave the default value. 1251 1252config HZ_FIXED 1253 int 1254 default 128 if SOC_AT91RM9200 1255 default 0 1256 1257choice 1258 depends on HZ_FIXED = 0 1259 prompt "Timer frequency" 1260 1261config HZ_100 1262 bool "100 Hz" 1263 1264config HZ_200 1265 bool "200 Hz" 1266 1267config HZ_250 1268 bool "250 Hz" 1269 1270config HZ_300 1271 bool "300 Hz" 1272 1273config HZ_500 1274 bool "500 Hz" 1275 1276config HZ_1000 1277 bool "1000 Hz" 1278 1279endchoice 1280 1281config HZ 1282 int 1283 default HZ_FIXED if HZ_FIXED != 0 1284 default 100 if HZ_100 1285 default 200 if HZ_200 1286 default 250 if HZ_250 1287 default 300 if HZ_300 1288 default 500 if HZ_500 1289 default 1000 1290 1291config SCHED_HRTICK 1292 def_bool HIGH_RES_TIMERS 1293 1294config THUMB2_KERNEL 1295 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1296 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1297 default y if CPU_THUMBONLY 1298 select ARM_UNWIND 1299 help 1300 By enabling this option, the kernel will be compiled in 1301 Thumb-2 mode. 1302 1303 If unsure, say N. 1304 1305config ARM_PATCH_IDIV 1306 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1307 depends on CPU_32v7 && !XIP_KERNEL 1308 default y 1309 help 1310 The ARM compiler inserts calls to __aeabi_idiv() and 1311 __aeabi_uidiv() when it needs to perform division on signed 1312 and unsigned integers. Some v7 CPUs have support for the sdiv 1313 and udiv instructions that can be used to implement those 1314 functions. 1315 1316 Enabling this option allows the kernel to modify itself to 1317 replace the first two instructions of these library functions 1318 with the sdiv or udiv plus "bx lr" instructions when the CPU 1319 it is running on supports them. Typically this will be faster 1320 and less power intensive than running the original library 1321 code to do integer division. 1322 1323config AEABI 1324 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1325 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1326 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1327 help 1328 This option allows for the kernel to be compiled using the latest 1329 ARM ABI (aka EABI). This is only useful if you are using a user 1330 space environment that is also compiled with EABI. 1331 1332 Since there are major incompatibilities between the legacy ABI and 1333 EABI, especially with regard to structure member alignment, this 1334 option also changes the kernel syscall calling convention to 1335 disambiguate both ABIs and allow for backward compatibility support 1336 (selected with CONFIG_OABI_COMPAT). 1337 1338 To use this you need GCC version 4.0.0 or later. 1339 1340config OABI_COMPAT 1341 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1342 depends on AEABI && !THUMB2_KERNEL 1343 help 1344 This option preserves the old syscall interface along with the 1345 new (ARM EABI) one. It also provides a compatibility layer to 1346 intercept syscalls that have structure arguments which layout 1347 in memory differs between the legacy ABI and the new ARM EABI 1348 (only for non "thumb" binaries). This option adds a tiny 1349 overhead to all syscalls and produces a slightly larger kernel. 1350 1351 The seccomp filter system will not be available when this is 1352 selected, since there is no way yet to sensibly distinguish 1353 between calling conventions during filtering. 1354 1355 If you know you'll be using only pure EABI user space then you 1356 can say N here. If this option is not selected and you attempt 1357 to execute a legacy ABI binary then the result will be 1358 UNPREDICTABLE (in fact it can be predicted that it won't work 1359 at all). If in doubt say N. 1360 1361config ARCH_SELECT_MEMORY_MODEL 1362 bool 1363 1364config ARCH_FLATMEM_ENABLE 1365 bool 1366 1367config ARCH_SPARSEMEM_ENABLE 1368 bool 1369 select SPARSEMEM_STATIC if SPARSEMEM 1370 1371config HIGHMEM 1372 bool "High Memory Support" 1373 depends on MMU 1374 select KMAP_LOCAL 1375 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1376 help 1377 The address space of ARM processors is only 4 Gigabytes large 1378 and it has to accommodate user address space, kernel address 1379 space as well as some memory mapped IO. That means that, if you 1380 have a large amount of physical memory and/or IO, not all of the 1381 memory can be "permanently mapped" by the kernel. The physical 1382 memory that is not permanently mapped is called "high memory". 1383 1384 Depending on the selected kernel/user memory split, minimum 1385 vmalloc space and actual amount of RAM, you may not need this 1386 option which should result in a slightly faster kernel. 1387 1388 If unsure, say n. 1389 1390config HIGHPTE 1391 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1392 depends on HIGHMEM 1393 default y 1394 help 1395 The VM uses one page of physical memory for each page table. 1396 For systems with a lot of processes, this can use a lot of 1397 precious low memory, eventually leading to low memory being 1398 consumed by page tables. Setting this option will allow 1399 user-space 2nd level page tables to reside in high memory. 1400 1401config CPU_SW_DOMAIN_PAN 1402 bool "Enable use of CPU domains to implement privileged no-access" 1403 depends on MMU && !ARM_LPAE 1404 default y 1405 help 1406 Increase kernel security by ensuring that normal kernel accesses 1407 are unable to access userspace addresses. This can help prevent 1408 use-after-free bugs becoming an exploitable privilege escalation 1409 by ensuring that magic values (such as LIST_POISON) will always 1410 fault when dereferenced. 1411 1412 CPUs with low-vector mappings use a best-efforts implementation. 1413 Their lower 1MB needs to remain accessible for the vectors, but 1414 the remainder of userspace will become appropriately inaccessible. 1415 1416config HW_PERF_EVENTS 1417 def_bool y 1418 depends on ARM_PMU 1419 1420config ARM_MODULE_PLTS 1421 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1422 depends on MODULES 1423 select KASAN_VMALLOC if KASAN 1424 default y 1425 help 1426 Allocate PLTs when loading modules so that jumps and calls whose 1427 targets are too far away for their relative offsets to be encoded 1428 in the instructions themselves can be bounced via veneers in the 1429 module's PLT. This allows modules to be allocated in the generic 1430 vmalloc area after the dedicated module memory area has been 1431 exhausted. The modules will use slightly more memory, but after 1432 rounding up to page size, the actual memory footprint is usually 1433 the same. 1434 1435 Disabling this is usually safe for small single-platform 1436 configurations. If unsure, say y. 1437 1438config FORCE_MAX_ZONEORDER 1439 int "Maximum zone order" 1440 default "12" if SOC_AM33XX 1441 default "9" if SA1111 1442 default "11" 1443 help 1444 The kernel memory allocator divides physically contiguous memory 1445 blocks into "zones", where each zone is a power of two number of 1446 pages. This option selects the largest power of two that the kernel 1447 keeps in the memory allocator. If you need to allocate very large 1448 blocks of physically contiguous memory, then you may need to 1449 increase this value. 1450 1451 This config option is actually maximum order plus one. For example, 1452 a value of 11 means that the largest free memory block is 2^10 pages. 1453 1454config ALIGNMENT_TRAP 1455 def_bool CPU_CP15_MMU 1456 select HAVE_PROC_CPU if PROC_FS 1457 help 1458 ARM processors cannot fetch/store information which is not 1459 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1460 address divisible by 4. On 32-bit ARM processors, these non-aligned 1461 fetch/store instructions will be emulated in software if you say 1462 here, which has a severe performance impact. This is necessary for 1463 correct operation of some network protocols. With an IP-only 1464 configuration it is safe to say N, otherwise say Y. 1465 1466config UACCESS_WITH_MEMCPY 1467 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1468 depends on MMU 1469 default y if CPU_FEROCEON 1470 help 1471 Implement faster copy_to_user and clear_user methods for CPU 1472 cores where a 8-word STM instruction give significantly higher 1473 memory write throughput than a sequence of individual 32bit stores. 1474 1475 A possible side effect is a slight increase in scheduling latency 1476 between threads sharing the same address space if they invoke 1477 such copy operations with large buffers. 1478 1479 However, if the CPU data cache is using a write-allocate mode, 1480 this option is unlikely to provide any performance gain. 1481 1482config PARAVIRT 1483 bool "Enable paravirtualization code" 1484 help 1485 This changes the kernel so it can modify itself when it is run 1486 under a hypervisor, potentially improving performance significantly 1487 over full virtualization. 1488 1489config PARAVIRT_TIME_ACCOUNTING 1490 bool "Paravirtual steal time accounting" 1491 select PARAVIRT 1492 help 1493 Select this option to enable fine granularity task steal time 1494 accounting. Time spent executing other tasks in parallel with 1495 the current vCPU is discounted from the vCPU power. To account for 1496 that, there can be a small performance impact. 1497 1498 If in doubt, say N here. 1499 1500config XEN_DOM0 1501 def_bool y 1502 depends on XEN 1503 1504config XEN 1505 bool "Xen guest support on ARM" 1506 depends on ARM && AEABI && OF 1507 depends on CPU_V7 && !CPU_V6 1508 depends on !GENERIC_ATOMIC64 1509 depends on MMU 1510 select ARCH_DMA_ADDR_T_64BIT 1511 select ARM_PSCI 1512 select SWIOTLB 1513 select SWIOTLB_XEN 1514 select PARAVIRT 1515 help 1516 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1517 1518config CC_HAVE_STACKPROTECTOR_TLS 1519 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1520 1521config STACKPROTECTOR_PER_TASK 1522 bool "Use a unique stack canary value for each task" 1523 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1524 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1525 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1526 default y 1527 help 1528 Due to the fact that GCC uses an ordinary symbol reference from 1529 which to load the value of the stack canary, this value can only 1530 change at reboot time on SMP systems, and all tasks running in the 1531 kernel's address space are forced to use the same canary value for 1532 the entire duration that the system is up. 1533 1534 Enable this option to switch to a different method that uses a 1535 different canary value for each task. 1536 1537endmenu 1538 1539menu "Boot options" 1540 1541config USE_OF 1542 bool "Flattened Device Tree support" 1543 select IRQ_DOMAIN 1544 select OF 1545 help 1546 Include support for flattened device tree machine descriptions. 1547 1548config ATAGS 1549 bool "Support for the traditional ATAGS boot data passing" 1550 default y 1551 help 1552 This is the traditional way of passing data to the kernel at boot 1553 time. If you are solely relying on the flattened device tree (or 1554 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1555 to remove ATAGS support from your kernel binary. 1556 1557config UNUSED_BOARD_FILES 1558 bool "Board support for machines without known users" 1559 depends on ATAGS 1560 help 1561 Most ATAGS based board files are completely unused and are 1562 scheduled for removal in early 2023, and left out of kernels 1563 by default now. If you are using a board file that is marked 1564 as unused, turn on this option to build support into the kernel. 1565 1566 To keep support for your individual board from being removed, 1567 send a reply to the email discussion at 1568 https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/ 1569 1570config DEPRECATED_PARAM_STRUCT 1571 bool "Provide old way to pass kernel parameters" 1572 depends on ATAGS 1573 help 1574 This was deprecated in 2001 and announced to live on for 5 years. 1575 Some old boot loaders still use this way. 1576 1577# Compressed boot loader in ROM. Yes, we really want to ask about 1578# TEXT and BSS so we preserve their values in the config files. 1579config ZBOOT_ROM_TEXT 1580 hex "Compressed ROM boot loader base address" 1581 default 0x0 1582 help 1583 The physical address at which the ROM-able zImage is to be 1584 placed in the target. Platforms which normally make use of 1585 ROM-able zImage formats normally set this to a suitable 1586 value in their defconfig file. 1587 1588 If ZBOOT_ROM is not enabled, this has no effect. 1589 1590config ZBOOT_ROM_BSS 1591 hex "Compressed ROM boot loader BSS address" 1592 default 0x0 1593 help 1594 The base address of an area of read/write memory in the target 1595 for the ROM-able zImage which must be available while the 1596 decompressor is running. It must be large enough to hold the 1597 entire decompressed kernel plus an additional 128 KiB. 1598 Platforms which normally make use of ROM-able zImage formats 1599 normally set this to a suitable value in their defconfig file. 1600 1601 If ZBOOT_ROM is not enabled, this has no effect. 1602 1603config ZBOOT_ROM 1604 bool "Compressed boot loader in ROM/flash" 1605 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1606 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1607 help 1608 Say Y here if you intend to execute your compressed kernel image 1609 (zImage) directly from ROM or flash. If unsure, say N. 1610 1611config ARM_APPENDED_DTB 1612 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1613 depends on OF 1614 help 1615 With this option, the boot code will look for a device tree binary 1616 (DTB) appended to zImage 1617 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1618 1619 This is meant as a backward compatibility convenience for those 1620 systems with a bootloader that can't be upgraded to accommodate 1621 the documented boot protocol using a device tree. 1622 1623 Beware that there is very little in terms of protection against 1624 this option being confused by leftover garbage in memory that might 1625 look like a DTB header after a reboot if no actual DTB is appended 1626 to zImage. Do not leave this option active in a production kernel 1627 if you don't intend to always append a DTB. Proper passing of the 1628 location into r2 of a bootloader provided DTB is always preferable 1629 to this option. 1630 1631config ARM_ATAG_DTB_COMPAT 1632 bool "Supplement the appended DTB with traditional ATAG information" 1633 depends on ARM_APPENDED_DTB 1634 help 1635 Some old bootloaders can't be updated to a DTB capable one, yet 1636 they provide ATAGs with memory configuration, the ramdisk address, 1637 the kernel cmdline string, etc. Such information is dynamically 1638 provided by the bootloader and can't always be stored in a static 1639 DTB. To allow a device tree enabled kernel to be used with such 1640 bootloaders, this option allows zImage to extract the information 1641 from the ATAG list and store it at run time into the appended DTB. 1642 1643choice 1644 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1645 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1646 1647config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1648 bool "Use bootloader kernel arguments if available" 1649 help 1650 Uses the command-line options passed by the boot loader instead of 1651 the device tree bootargs property. If the boot loader doesn't provide 1652 any, the device tree bootargs property will be used. 1653 1654config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1655 bool "Extend with bootloader kernel arguments" 1656 help 1657 The command-line arguments provided by the boot loader will be 1658 appended to the the device tree bootargs property. 1659 1660endchoice 1661 1662config CMDLINE 1663 string "Default kernel command string" 1664 default "" 1665 help 1666 On some architectures (e.g. CATS), there is currently no way 1667 for the boot loader to pass arguments to the kernel. For these 1668 architectures, you should supply some command-line options at build 1669 time by entering them here. As a minimum, you should specify the 1670 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1671 1672choice 1673 prompt "Kernel command line type" if CMDLINE != "" 1674 default CMDLINE_FROM_BOOTLOADER 1675 depends on ATAGS 1676 1677config CMDLINE_FROM_BOOTLOADER 1678 bool "Use bootloader kernel arguments if available" 1679 help 1680 Uses the command-line options passed by the boot loader. If 1681 the boot loader doesn't provide any, the default kernel command 1682 string provided in CMDLINE will be used. 1683 1684config CMDLINE_EXTEND 1685 bool "Extend bootloader kernel arguments" 1686 help 1687 The command-line arguments provided by the boot loader will be 1688 appended to the default kernel command string. 1689 1690config CMDLINE_FORCE 1691 bool "Always use the default kernel command string" 1692 help 1693 Always use the default kernel command string, even if the boot 1694 loader passes other arguments to the kernel. 1695 This is useful if you cannot or don't want to change the 1696 command-line options your boot loader passes to the kernel. 1697endchoice 1698 1699config XIP_KERNEL 1700 bool "Kernel Execute-In-Place from ROM" 1701 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1702 help 1703 Execute-In-Place allows the kernel to run from non-volatile storage 1704 directly addressable by the CPU, such as NOR flash. This saves RAM 1705 space since the text section of the kernel is not loaded from flash 1706 to RAM. Read-write sections, such as the data section and stack, 1707 are still copied to RAM. The XIP kernel is not compressed since 1708 it has to run directly from flash, so it will take more space to 1709 store it. The flash address used to link the kernel object files, 1710 and for storing it, is configuration dependent. Therefore, if you 1711 say Y here, you must know the proper physical address where to 1712 store the kernel image depending on your own flash memory usage. 1713 1714 Also note that the make target becomes "make xipImage" rather than 1715 "make zImage" or "make Image". The final kernel binary to put in 1716 ROM memory will be arch/arm/boot/xipImage. 1717 1718 If unsure, say N. 1719 1720config XIP_PHYS_ADDR 1721 hex "XIP Kernel Physical Location" 1722 depends on XIP_KERNEL 1723 default "0x00080000" 1724 help 1725 This is the physical address in your flash memory the kernel will 1726 be linked for and stored to. This address is dependent on your 1727 own flash usage. 1728 1729config XIP_DEFLATED_DATA 1730 bool "Store kernel .data section compressed in ROM" 1731 depends on XIP_KERNEL 1732 select ZLIB_INFLATE 1733 help 1734 Before the kernel is actually executed, its .data section has to be 1735 copied to RAM from ROM. This option allows for storing that data 1736 in compressed form and decompressed to RAM rather than merely being 1737 copied, saving some precious ROM space. A possible drawback is a 1738 slightly longer boot delay. 1739 1740config KEXEC 1741 bool "Kexec system call (EXPERIMENTAL)" 1742 depends on (!SMP || PM_SLEEP_SMP) 1743 depends on MMU 1744 select KEXEC_CORE 1745 help 1746 kexec is a system call that implements the ability to shutdown your 1747 current kernel, and to start another kernel. It is like a reboot 1748 but it is independent of the system firmware. And like a reboot 1749 you can start any kernel with it, not just Linux. 1750 1751 It is an ongoing process to be certain the hardware in a machine 1752 is properly shutdown, so do not be surprised if this code does not 1753 initially work for you. 1754 1755config ATAGS_PROC 1756 bool "Export atags in procfs" 1757 depends on ATAGS && KEXEC 1758 default y 1759 help 1760 Should the atags used to boot the kernel be exported in an "atags" 1761 file in procfs. Useful with kexec. 1762 1763config CRASH_DUMP 1764 bool "Build kdump crash kernel (EXPERIMENTAL)" 1765 help 1766 Generate crash dump after being started by kexec. This should 1767 be normally only set in special crash dump kernels which are 1768 loaded in the main kernel with kexec-tools into a specially 1769 reserved region and then later executed after a crash by 1770 kdump/kexec. The crash dump kernel must be compiled to a 1771 memory address not used by the main kernel 1772 1773 For more details see Documentation/admin-guide/kdump/kdump.rst 1774 1775config AUTO_ZRELADDR 1776 bool "Auto calculation of the decompressed kernel image address" 1777 help 1778 ZRELADDR is the physical address where the decompressed kernel 1779 image will be placed. If AUTO_ZRELADDR is selected, the address 1780 will be determined at run-time, either by masking the current IP 1781 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1782 This assumes the zImage being placed in the first 128MB from 1783 start of memory. 1784 1785config EFI_STUB 1786 bool 1787 1788config EFI 1789 bool "UEFI runtime support" 1790 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1791 select UCS2_STRING 1792 select EFI_PARAMS_FROM_FDT 1793 select EFI_STUB 1794 select EFI_GENERIC_STUB 1795 select EFI_RUNTIME_WRAPPERS 1796 help 1797 This option provides support for runtime services provided 1798 by UEFI firmware (such as non-volatile variables, realtime 1799 clock, and platform reset). A UEFI stub is also provided to 1800 allow the kernel to be booted as an EFI application. This 1801 is only useful for kernels that may run on systems that have 1802 UEFI firmware. 1803 1804config DMI 1805 bool "Enable support for SMBIOS (DMI) tables" 1806 depends on EFI 1807 default y 1808 help 1809 This enables SMBIOS/DMI feature for systems. 1810 1811 This option is only useful on systems that have UEFI firmware. 1812 However, even with this option, the resultant kernel should 1813 continue to boot on existing non-UEFI platforms. 1814 1815 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1816 i.e., the the practice of identifying the platform via DMI to 1817 decide whether certain workarounds for buggy hardware and/or 1818 firmware need to be enabled. This would require the DMI subsystem 1819 to be enabled much earlier than we do on ARM, which is non-trivial. 1820 1821endmenu 1822 1823menu "CPU Power Management" 1824 1825source "drivers/cpufreq/Kconfig" 1826 1827source "drivers/cpuidle/Kconfig" 1828 1829endmenu 1830 1831menu "Floating point emulation" 1832 1833comment "At least one emulation must be selected" 1834 1835config FPE_NWFPE 1836 bool "NWFPE math emulation" 1837 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1838 help 1839 Say Y to include the NWFPE floating point emulator in the kernel. 1840 This is necessary to run most binaries. Linux does not currently 1841 support floating point hardware so you need to say Y here even if 1842 your machine has an FPA or floating point co-processor podule. 1843 1844 You may say N here if you are going to load the Acorn FPEmulator 1845 early in the bootup. 1846 1847config FPE_NWFPE_XP 1848 bool "Support extended precision" 1849 depends on FPE_NWFPE 1850 help 1851 Say Y to include 80-bit support in the kernel floating-point 1852 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1853 Note that gcc does not generate 80-bit operations by default, 1854 so in most cases this option only enlarges the size of the 1855 floating point emulator without any good reason. 1856 1857 You almost surely want to say N here. 1858 1859config FPE_FASTFPE 1860 bool "FastFPE math emulation (EXPERIMENTAL)" 1861 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1862 help 1863 Say Y here to include the FAST floating point emulator in the kernel. 1864 This is an experimental much faster emulator which now also has full 1865 precision for the mantissa. It does not support any exceptions. 1866 It is very simple, and approximately 3-6 times faster than NWFPE. 1867 1868 It should be sufficient for most programs. It may be not suitable 1869 for scientific calculations, but you have to check this for yourself. 1870 If you do not feel you need a faster FP emulation you should better 1871 choose NWFPE. 1872 1873config VFP 1874 bool "VFP-format floating point maths" 1875 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1876 help 1877 Say Y to include VFP support code in the kernel. This is needed 1878 if your hardware includes a VFP unit. 1879 1880 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1881 release notes and additional status information. 1882 1883 Say N if your target does not have VFP hardware. 1884 1885config VFPv3 1886 bool 1887 depends on VFP 1888 default y if CPU_V7 1889 1890config NEON 1891 bool "Advanced SIMD (NEON) Extension support" 1892 depends on VFPv3 && CPU_V7 1893 help 1894 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1895 Extension. 1896 1897config KERNEL_MODE_NEON 1898 bool "Support for NEON in kernel mode" 1899 depends on NEON && AEABI 1900 help 1901 Say Y to include support for NEON in kernel mode. 1902 1903endmenu 1904 1905menu "Power management options" 1906 1907source "kernel/power/Kconfig" 1908 1909config ARCH_SUSPEND_POSSIBLE 1910 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1911 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1912 def_bool y 1913 1914config ARM_CPU_SUSPEND 1915 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1916 depends on ARCH_SUSPEND_POSSIBLE 1917 1918config ARCH_HIBERNATION_POSSIBLE 1919 bool 1920 depends on MMU 1921 default y if ARCH_SUSPEND_POSSIBLE 1922 1923endmenu 1924 1925if CRYPTO 1926source "arch/arm/crypto/Kconfig" 1927endif 1928 1929source "arch/arm/Kconfig.assembler" 1930