1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_DEBUG_VIRTUAL if MMU 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 28 select ARCH_HAS_GCOV_PROFILE_ALL 29 select ARCH_KEEP_MEMBLOCK 30 select ARCH_MIGHT_HAVE_PC_PARPORT 31 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 32 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 33 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 34 select ARCH_SUPPORTS_ATOMIC_RMW 35 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 36 select ARCH_USE_BUILTIN_BSWAP 37 select ARCH_USE_CMPXCHG_LOCKREF 38 select ARCH_USE_MEMTEST 39 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 40 select ARCH_WANT_IPC_PARSE_VERSION 41 select ARCH_WANT_LD_ORPHAN_WARN 42 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 43 select BUILDTIME_TABLE_SORT if MMU 44 select CLONE_BACKWARDS 45 select CPU_PM if SUSPEND || CPU_IDLE 46 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 47 select DMA_DECLARE_COHERENT 48 select DMA_GLOBAL_POOL if !MMU 49 select DMA_OPS 50 select DMA_REMAP if MMU 51 select EDAC_SUPPORT 52 select EDAC_ATOMIC_SCRUB 53 select GENERIC_ALLOCATOR 54 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 55 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 56 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 57 select GENERIC_IRQ_IPI if SMP 58 select GENERIC_CPU_AUTOPROBE 59 select GENERIC_EARLY_IOREMAP 60 select GENERIC_IDLE_POLL_SETUP 61 select GENERIC_IRQ_PROBE 62 select GENERIC_IRQ_SHOW 63 select GENERIC_IRQ_SHOW_LEVEL 64 select GENERIC_LIB_DEVMEM_IS_ALLOWED 65 select GENERIC_PCI_IOMAP 66 select GENERIC_SCHED_CLOCK 67 select GENERIC_SMP_IDLE_THREAD 68 select HARDIRQS_SW_RESEND 69 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 70 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 71 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 72 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 73 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 74 select HAVE_ARCH_MMAP_RND_BITS if MMU 75 select HAVE_ARCH_PFN_VALID 76 select HAVE_ARCH_SECCOMP 77 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 78 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 79 select HAVE_ARCH_TRACEHOOK 80 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 81 select HAVE_ARM_SMCCC if CPU_V7 82 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 83 select HAVE_CONTEXT_TRACKING 84 select HAVE_C_RECORDMCOUNT 85 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 86 select HAVE_DMA_CONTIGUOUS if MMU 87 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 88 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 89 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 90 select HAVE_EXIT_THREAD 91 select HAVE_FAST_GUP if ARM_LPAE 92 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 93 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 94 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && !(THUMB2_KERNEL && CC_IS_CLANG) 95 select HAVE_FUTEX_CMPXCHG if FUTEX 96 select HAVE_GCC_PLUGINS 97 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 98 select HAVE_IRQ_TIME_ACCOUNTING 99 select HAVE_KERNEL_GZIP 100 select HAVE_KERNEL_LZ4 101 select HAVE_KERNEL_LZMA 102 select HAVE_KERNEL_LZO 103 select HAVE_KERNEL_XZ 104 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 105 select HAVE_KRETPROBES if HAVE_KPROBES 106 select HAVE_MOD_ARCH_SPECIFIC 107 select HAVE_NMI 108 select HAVE_OPTPROBES if !THUMB2_KERNEL 109 select HAVE_PERF_EVENTS 110 select HAVE_PERF_REGS 111 select HAVE_PERF_USER_STACK_DUMP 112 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 113 select HAVE_REGS_AND_STACK_ACCESS_API 114 select HAVE_RSEQ 115 select HAVE_STACKPROTECTOR 116 select HAVE_SYSCALL_TRACEPOINTS 117 select HAVE_UID16 118 select HAVE_VIRT_CPU_ACCOUNTING_GEN 119 select IRQ_FORCED_THREADING 120 select MODULES_USE_ELF_REL 121 select NEED_DMA_MAP_STATE 122 select OF_EARLY_FLATTREE if OF 123 select OLD_SIGACTION 124 select OLD_SIGSUSPEND3 125 select PCI_SYSCALL if PCI 126 select PERF_USE_VMALLOC 127 select RTC_LIB 128 select SYS_SUPPORTS_APM_EMULATION 129 select THREAD_INFO_IN_TASK if CURRENT_POINTER_IN_TPIDRURO 130 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 131 # Above selects are sorted alphabetically; please add new ones 132 # according to that. Thanks. 133 help 134 The ARM series is a line of low-power-consumption RISC chip designs 135 licensed by ARM Ltd and targeted at embedded applications and 136 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 137 manufactured, but legacy ARM-based PC hardware remains popular in 138 Europe. There is an ARM Linux project with a web page at 139 <http://www.arm.linux.org.uk/>. 140 141config ARM_HAS_SG_CHAIN 142 bool 143 144config ARM_DMA_USE_IOMMU 145 bool 146 select ARM_HAS_SG_CHAIN 147 select NEED_SG_DMA_LENGTH 148 149if ARM_DMA_USE_IOMMU 150 151config ARM_DMA_IOMMU_ALIGNMENT 152 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 153 range 4 9 154 default 8 155 help 156 DMA mapping framework by default aligns all buffers to the smallest 157 PAGE_SIZE order which is greater than or equal to the requested buffer 158 size. This works well for buffers up to a few hundreds kilobytes, but 159 for larger buffers it just a waste of address space. Drivers which has 160 relatively small addressing window (like 64Mib) might run out of 161 virtual space with just a few allocations. 162 163 With this parameter you can specify the maximum PAGE_SIZE order for 164 DMA IOMMU buffers. Larger buffers will be aligned only to this 165 specified order. The order is expressed as a power of two multiplied 166 by the PAGE_SIZE. 167 168endif 169 170config SYS_SUPPORTS_APM_EMULATION 171 bool 172 173config HAVE_TCM 174 bool 175 select GENERIC_ALLOCATOR 176 177config HAVE_PROC_CPU 178 bool 179 180config NO_IOPORT_MAP 181 bool 182 183config SBUS 184 bool 185 186config STACKTRACE_SUPPORT 187 bool 188 default y 189 190config LOCKDEP_SUPPORT 191 bool 192 default y 193 194config ARCH_HAS_ILOG2_U32 195 bool 196 197config ARCH_HAS_ILOG2_U64 198 bool 199 200config ARCH_HAS_BANDGAP 201 bool 202 203config FIX_EARLYCON_MEM 204 def_bool y if MMU 205 206config GENERIC_HWEIGHT 207 bool 208 default y 209 210config GENERIC_CALIBRATE_DELAY 211 bool 212 default y 213 214config ARCH_MAY_HAVE_PC_FDC 215 bool 216 217config ARCH_SUPPORTS_UPROBES 218 def_bool y 219 220config ARCH_HAS_DMA_SET_COHERENT_MASK 221 bool 222 223config GENERIC_ISA_DMA 224 bool 225 226config FIQ 227 bool 228 229config NEED_RET_TO_USER 230 bool 231 232config ARCH_MTD_XIP 233 bool 234 235config ARM_PATCH_PHYS_VIRT 236 bool "Patch physical to virtual translations at runtime" if EMBEDDED 237 default y 238 depends on !XIP_KERNEL && MMU 239 help 240 Patch phys-to-virt and virt-to-phys translation functions at 241 boot and module load time according to the position of the 242 kernel in system memory. 243 244 This can only be used with non-XIP MMU kernels where the base 245 of physical memory is at a 2 MiB boundary. 246 247 Only disable this option if you know that you do not require 248 this feature (eg, building a kernel for a single machine) and 249 you need to shrink the kernel to the minimal size. 250 251config NEED_MACH_IO_H 252 bool 253 help 254 Select this when mach/io.h is required to provide special 255 definitions for this platform. The need for mach/io.h should 256 be avoided when possible. 257 258config NEED_MACH_MEMORY_H 259 bool 260 help 261 Select this when mach/memory.h is required to provide special 262 definitions for this platform. The need for mach/memory.h should 263 be avoided when possible. 264 265config PHYS_OFFSET 266 hex "Physical address of main memory" if MMU 267 depends on !ARM_PATCH_PHYS_VIRT 268 default DRAM_BASE if !MMU 269 default 0x00000000 if ARCH_FOOTBRIDGE || ARCH_IXP4XX 270 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 271 default 0x30000000 if ARCH_S3C24XX 272 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 273 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 274 default 0 275 help 276 Please provide the physical address corresponding to the 277 location of main memory in your system. 278 279config GENERIC_BUG 280 def_bool y 281 depends on BUG 282 283config PGTABLE_LEVELS 284 int 285 default 3 if ARM_LPAE 286 default 2 287 288menu "System Type" 289 290config MMU 291 bool "MMU-based Paged Memory Management Support" 292 default y 293 help 294 Select if you want MMU-based virtualised addressing space 295 support by paged memory management. If unsure, say 'Y'. 296 297config ARCH_MMAP_RND_BITS_MIN 298 default 8 299 300config ARCH_MMAP_RND_BITS_MAX 301 default 14 if PAGE_OFFSET=0x40000000 302 default 15 if PAGE_OFFSET=0x80000000 303 default 16 304 305# 306# The "ARM system type" choice list is ordered alphabetically by option 307# text. Please add new entries in the option alphabetic order. 308# 309choice 310 prompt "ARM system type" 311 default ARM_SINGLE_ARMV7M if !MMU 312 default ARCH_MULTIPLATFORM if MMU 313 314config ARCH_MULTIPLATFORM 315 bool "Allow multiple platforms to be selected" 316 depends on MMU 317 select ARCH_FLATMEM_ENABLE 318 select ARCH_SPARSEMEM_ENABLE 319 select ARCH_SELECT_MEMORY_MODEL 320 select ARM_HAS_SG_CHAIN 321 select ARM_PATCH_PHYS_VIRT 322 select AUTO_ZRELADDR 323 select TIMER_OF 324 select COMMON_CLK 325 select GENERIC_IRQ_MULTI_HANDLER 326 select HAVE_PCI 327 select PCI_DOMAINS_GENERIC if PCI 328 select SPARSE_IRQ 329 select USE_OF 330 331config ARM_SINGLE_ARMV7M 332 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 333 depends on !MMU 334 select ARM_NVIC 335 select AUTO_ZRELADDR 336 select TIMER_OF 337 select COMMON_CLK 338 select CPU_V7M 339 select NO_IOPORT_MAP 340 select SPARSE_IRQ 341 select USE_OF 342 343config ARCH_EP93XX 344 bool "EP93xx-based" 345 select ARCH_SPARSEMEM_ENABLE 346 select ARM_AMBA 347 imply ARM_PATCH_PHYS_VIRT 348 select ARM_VIC 349 select GENERIC_IRQ_MULTI_HANDLER 350 select AUTO_ZRELADDR 351 select CLKSRC_MMIO 352 select CPU_ARM920T 353 select GPIOLIB 354 select COMMON_CLK 355 help 356 This enables support for the Cirrus EP93xx series of CPUs. 357 358config ARCH_FOOTBRIDGE 359 bool "FootBridge" 360 select CPU_SA110 361 select FOOTBRIDGE 362 select NEED_MACH_IO_H if !MMU 363 select NEED_MACH_MEMORY_H 364 help 365 Support for systems based on the DC21285 companion chip 366 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 367 368config ARCH_IOP32X 369 bool "IOP32x-based" 370 depends on MMU 371 select CPU_XSCALE 372 select GPIO_IOP 373 select GPIOLIB 374 select NEED_RET_TO_USER 375 select FORCE_PCI 376 select PLAT_IOP 377 help 378 Support for Intel's 80219 and IOP32X (XScale) family of 379 processors. 380 381config ARCH_IXP4XX 382 bool "IXP4xx-based" 383 depends on MMU 384 select ARCH_HAS_DMA_SET_COHERENT_MASK 385 select ARCH_SUPPORTS_BIG_ENDIAN 386 select CPU_XSCALE 387 select DMABOUNCE if PCI 388 select GENERIC_IRQ_MULTI_HANDLER 389 select GPIO_IXP4XX 390 select GPIOLIB 391 select HAVE_PCI 392 select IXP4XX_IRQ 393 select IXP4XX_TIMER 394 # With the new PCI driver this is not needed 395 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY 396 select USB_EHCI_BIG_ENDIAN_DESC 397 select USB_EHCI_BIG_ENDIAN_MMIO 398 help 399 Support for Intel's IXP4XX (XScale) family of processors. 400 401config ARCH_DOVE 402 bool "Marvell Dove" 403 select CPU_PJ4 404 select GENERIC_IRQ_MULTI_HANDLER 405 select GPIOLIB 406 select HAVE_PCI 407 select MVEBU_MBUS 408 select PINCTRL 409 select PINCTRL_DOVE 410 select PLAT_ORION_LEGACY 411 select SPARSE_IRQ 412 select PM_GENERIC_DOMAINS if PM 413 help 414 Support for the Marvell Dove SoC 88AP510 415 416config ARCH_PXA 417 bool "PXA2xx/PXA3xx-based" 418 depends on MMU 419 select ARCH_MTD_XIP 420 select ARM_CPU_SUSPEND if PM 421 select AUTO_ZRELADDR 422 select COMMON_CLK 423 select CLKSRC_PXA 424 select CLKSRC_MMIO 425 select TIMER_OF 426 select CPU_XSCALE if !CPU_XSC3 427 select GENERIC_IRQ_MULTI_HANDLER 428 select GPIO_PXA 429 select GPIOLIB 430 select IRQ_DOMAIN 431 select PLAT_PXA 432 select SPARSE_IRQ 433 help 434 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 435 436config ARCH_RPC 437 bool "RiscPC" 438 depends on MMU 439 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 440 select ARCH_ACORN 441 select ARCH_MAY_HAVE_PC_FDC 442 select ARCH_SPARSEMEM_ENABLE 443 select ARM_HAS_SG_CHAIN 444 select CPU_SA110 445 select FIQ 446 select HAVE_PATA_PLATFORM 447 select ISA_DMA_API 448 select LEGACY_TIMER_TICK 449 select NEED_MACH_IO_H 450 select NEED_MACH_MEMORY_H 451 select NO_IOPORT_MAP 452 help 453 On the Acorn Risc-PC, Linux can support the internal IDE disk and 454 CD-ROM interface, serial and parallel port, and the floppy drive. 455 456config ARCH_SA1100 457 bool "SA1100-based" 458 select ARCH_MTD_XIP 459 select ARCH_SPARSEMEM_ENABLE 460 select CLKSRC_MMIO 461 select CLKSRC_PXA 462 select TIMER_OF if OF 463 select COMMON_CLK 464 select CPU_FREQ 465 select CPU_SA1100 466 select GENERIC_IRQ_MULTI_HANDLER 467 select GPIOLIB 468 select IRQ_DOMAIN 469 select ISA 470 select NEED_MACH_MEMORY_H 471 select SPARSE_IRQ 472 help 473 Support for StrongARM 11x0 based boards. 474 475config ARCH_S3C24XX 476 bool "Samsung S3C24XX SoCs" 477 select ATAGS 478 select CLKSRC_SAMSUNG_PWM 479 select GPIO_SAMSUNG 480 select GPIOLIB 481 select GENERIC_IRQ_MULTI_HANDLER 482 select HAVE_S3C2410_I2C if I2C 483 select NEED_MACH_IO_H 484 select S3C2410_WATCHDOG 485 select SAMSUNG_ATAGS 486 select USE_OF 487 select WATCHDOG 488 help 489 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 490 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 491 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 492 Samsung SMDK2410 development board (and derivatives). 493 494config ARCH_OMAP1 495 bool "TI OMAP1" 496 depends on MMU 497 select ARCH_OMAP 498 select CLKSRC_MMIO 499 select GENERIC_IRQ_CHIP 500 select GENERIC_IRQ_MULTI_HANDLER 501 select GPIOLIB 502 select HAVE_LEGACY_CLK 503 select IRQ_DOMAIN 504 select NEED_MACH_IO_H if PCCARD 505 select NEED_MACH_MEMORY_H 506 select SPARSE_IRQ 507 help 508 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 509 510endchoice 511 512menu "Multiple platform selection" 513 depends on ARCH_MULTIPLATFORM 514 515comment "CPU Core family selection" 516 517config ARCH_MULTI_V4 518 bool "ARMv4 based platforms (FA526)" 519 depends on !ARCH_MULTI_V6_V7 520 select ARCH_MULTI_V4_V5 521 select CPU_FA526 522 523config ARCH_MULTI_V4T 524 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 525 depends on !ARCH_MULTI_V6_V7 526 select ARCH_MULTI_V4_V5 527 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 528 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 529 CPU_ARM925T || CPU_ARM940T) 530 531config ARCH_MULTI_V5 532 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 533 depends on !ARCH_MULTI_V6_V7 534 select ARCH_MULTI_V4_V5 535 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 536 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 537 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 538 539config ARCH_MULTI_V4_V5 540 bool 541 542config ARCH_MULTI_V6 543 bool "ARMv6 based platforms (ARM11)" 544 select ARCH_MULTI_V6_V7 545 select CPU_V6K 546 547config ARCH_MULTI_V7 548 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 549 default y 550 select ARCH_MULTI_V6_V7 551 select CPU_V7 552 select HAVE_SMP 553 554config ARCH_MULTI_V6_V7 555 bool 556 select MIGHT_HAVE_CACHE_L2X0 557 558config ARCH_MULTI_CPU_AUTO 559 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 560 select ARCH_MULTI_V5 561 562endmenu 563 564config ARCH_VIRT 565 bool "Dummy Virtual Machine" 566 depends on ARCH_MULTI_V7 567 select ARM_AMBA 568 select ARM_GIC 569 select ARM_GIC_V2M if PCI 570 select ARM_GIC_V3 571 select ARM_GIC_V3_ITS if PCI 572 select ARM_PSCI 573 select HAVE_ARM_ARCH_TIMER 574 select ARCH_SUPPORTS_BIG_ENDIAN 575 576# 577# This is sorted alphabetically by mach-* pathname. However, plat-* 578# Kconfigs may be included either alphabetically (according to the 579# plat- suffix) or along side the corresponding mach-* source. 580# 581source "arch/arm/mach-actions/Kconfig" 582 583source "arch/arm/mach-alpine/Kconfig" 584 585source "arch/arm/mach-artpec/Kconfig" 586 587source "arch/arm/mach-asm9260/Kconfig" 588 589source "arch/arm/mach-aspeed/Kconfig" 590 591source "arch/arm/mach-at91/Kconfig" 592 593source "arch/arm/mach-axxia/Kconfig" 594 595source "arch/arm/mach-bcm/Kconfig" 596 597source "arch/arm/mach-berlin/Kconfig" 598 599source "arch/arm/mach-clps711x/Kconfig" 600 601source "arch/arm/mach-cns3xxx/Kconfig" 602 603source "arch/arm/mach-davinci/Kconfig" 604 605source "arch/arm/mach-digicolor/Kconfig" 606 607source "arch/arm/mach-dove/Kconfig" 608 609source "arch/arm/mach-ep93xx/Kconfig" 610 611source "arch/arm/mach-exynos/Kconfig" 612 613source "arch/arm/mach-footbridge/Kconfig" 614 615source "arch/arm/mach-gemini/Kconfig" 616 617source "arch/arm/mach-highbank/Kconfig" 618 619source "arch/arm/mach-hisi/Kconfig" 620 621source "arch/arm/mach-imx/Kconfig" 622 623source "arch/arm/mach-integrator/Kconfig" 624 625source "arch/arm/mach-iop32x/Kconfig" 626 627source "arch/arm/mach-ixp4xx/Kconfig" 628 629source "arch/arm/mach-keystone/Kconfig" 630 631source "arch/arm/mach-lpc32xx/Kconfig" 632 633source "arch/arm/mach-mediatek/Kconfig" 634 635source "arch/arm/mach-meson/Kconfig" 636 637source "arch/arm/mach-milbeaut/Kconfig" 638 639source "arch/arm/mach-mmp/Kconfig" 640 641source "arch/arm/mach-moxart/Kconfig" 642 643source "arch/arm/mach-mstar/Kconfig" 644 645source "arch/arm/mach-mv78xx0/Kconfig" 646 647source "arch/arm/mach-mvebu/Kconfig" 648 649source "arch/arm/mach-mxs/Kconfig" 650 651source "arch/arm/mach-nomadik/Kconfig" 652 653source "arch/arm/mach-npcm/Kconfig" 654 655source "arch/arm/mach-nspire/Kconfig" 656 657source "arch/arm/plat-omap/Kconfig" 658 659source "arch/arm/mach-omap1/Kconfig" 660 661source "arch/arm/mach-omap2/Kconfig" 662 663source "arch/arm/mach-orion5x/Kconfig" 664 665source "arch/arm/mach-oxnas/Kconfig" 666 667source "arch/arm/mach-pxa/Kconfig" 668source "arch/arm/plat-pxa/Kconfig" 669 670source "arch/arm/mach-qcom/Kconfig" 671 672source "arch/arm/mach-rda/Kconfig" 673 674source "arch/arm/mach-realtek/Kconfig" 675 676source "arch/arm/mach-realview/Kconfig" 677 678source "arch/arm/mach-rockchip/Kconfig" 679 680source "arch/arm/mach-s3c/Kconfig" 681 682source "arch/arm/mach-s5pv210/Kconfig" 683 684source "arch/arm/mach-sa1100/Kconfig" 685 686source "arch/arm/mach-shmobile/Kconfig" 687 688source "arch/arm/mach-socfpga/Kconfig" 689 690source "arch/arm/mach-spear/Kconfig" 691 692source "arch/arm/mach-sti/Kconfig" 693 694source "arch/arm/mach-stm32/Kconfig" 695 696source "arch/arm/mach-sunxi/Kconfig" 697 698source "arch/arm/mach-tegra/Kconfig" 699 700source "arch/arm/mach-uniphier/Kconfig" 701 702source "arch/arm/mach-ux500/Kconfig" 703 704source "arch/arm/mach-versatile/Kconfig" 705 706source "arch/arm/mach-vexpress/Kconfig" 707 708source "arch/arm/mach-vt8500/Kconfig" 709 710source "arch/arm/mach-zynq/Kconfig" 711 712# ARMv7-M architecture 713config ARCH_LPC18XX 714 bool "NXP LPC18xx/LPC43xx" 715 depends on ARM_SINGLE_ARMV7M 716 select ARCH_HAS_RESET_CONTROLLER 717 select ARM_AMBA 718 select CLKSRC_LPC32XX 719 select PINCTRL 720 help 721 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 722 high performance microcontrollers. 723 724config ARCH_MPS2 725 bool "ARM MPS2 platform" 726 depends on ARM_SINGLE_ARMV7M 727 select ARM_AMBA 728 select CLKSRC_MPS2 729 help 730 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 731 with a range of available cores like Cortex-M3/M4/M7. 732 733 Please, note that depends which Application Note is used memory map 734 for the platform may vary, so adjustment of RAM base might be needed. 735 736# Definitions to make life easier 737config ARCH_ACORN 738 bool 739 740config PLAT_IOP 741 bool 742 743config PLAT_ORION 744 bool 745 select CLKSRC_MMIO 746 select COMMON_CLK 747 select GENERIC_IRQ_CHIP 748 select IRQ_DOMAIN 749 750config PLAT_ORION_LEGACY 751 bool 752 select PLAT_ORION 753 754config PLAT_PXA 755 bool 756 757config PLAT_VERSATILE 758 bool 759 760source "arch/arm/mm/Kconfig" 761 762config IWMMXT 763 bool "Enable iWMMXt support" 764 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 765 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 766 help 767 Enable support for iWMMXt context switching at run time if 768 running on a CPU that supports it. 769 770if !MMU 771source "arch/arm/Kconfig-nommu" 772endif 773 774config PJ4B_ERRATA_4742 775 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 776 depends on CPU_PJ4B && MACH_ARMADA_370 777 default y 778 help 779 When coming out of either a Wait for Interrupt (WFI) or a Wait for 780 Event (WFE) IDLE states, a specific timing sensitivity exists between 781 the retiring WFI/WFE instructions and the newly issued subsequent 782 instructions. This sensitivity can result in a CPU hang scenario. 783 Workaround: 784 The software must insert either a Data Synchronization Barrier (DSB) 785 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 786 instruction 787 788config ARM_ERRATA_326103 789 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 790 depends on CPU_V6 791 help 792 Executing a SWP instruction to read-only memory does not set bit 11 793 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 794 treat the access as a read, preventing a COW from occurring and 795 causing the faulting task to livelock. 796 797config ARM_ERRATA_411920 798 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 799 depends on CPU_V6 || CPU_V6K 800 help 801 Invalidation of the Instruction Cache operation can 802 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 803 It does not affect the MPCore. This option enables the ARM Ltd. 804 recommended workaround. 805 806config ARM_ERRATA_430973 807 bool "ARM errata: Stale prediction on replaced interworking branch" 808 depends on CPU_V7 809 help 810 This option enables the workaround for the 430973 Cortex-A8 811 r1p* erratum. If a code sequence containing an ARM/Thumb 812 interworking branch is replaced with another code sequence at the 813 same virtual address, whether due to self-modifying code or virtual 814 to physical address re-mapping, Cortex-A8 does not recover from the 815 stale interworking branch prediction. This results in Cortex-A8 816 executing the new code sequence in the incorrect ARM or Thumb state. 817 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 818 and also flushes the branch target cache at every context switch. 819 Note that setting specific bits in the ACTLR register may not be 820 available in non-secure mode. 821 822config ARM_ERRATA_458693 823 bool "ARM errata: Processor deadlock when a false hazard is created" 824 depends on CPU_V7 825 depends on !ARCH_MULTIPLATFORM 826 help 827 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 828 erratum. For very specific sequences of memory operations, it is 829 possible for a hazard condition intended for a cache line to instead 830 be incorrectly associated with a different cache line. This false 831 hazard might then cause a processor deadlock. The workaround enables 832 the L1 caching of the NEON accesses and disables the PLD instruction 833 in the ACTLR register. Note that setting specific bits in the ACTLR 834 register may not be available in non-secure mode. 835 836config ARM_ERRATA_460075 837 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 838 depends on CPU_V7 839 depends on !ARCH_MULTIPLATFORM 840 help 841 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 842 erratum. Any asynchronous access to the L2 cache may encounter a 843 situation in which recent store transactions to the L2 cache are lost 844 and overwritten with stale memory contents from external memory. The 845 workaround disables the write-allocate mode for the L2 cache via the 846 ACTLR register. Note that setting specific bits in the ACTLR register 847 may not be available in non-secure mode. 848 849config ARM_ERRATA_742230 850 bool "ARM errata: DMB operation may be faulty" 851 depends on CPU_V7 && SMP 852 depends on !ARCH_MULTIPLATFORM 853 help 854 This option enables the workaround for the 742230 Cortex-A9 855 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 856 between two write operations may not ensure the correct visibility 857 ordering of the two writes. This workaround sets a specific bit in 858 the diagnostic register of the Cortex-A9 which causes the DMB 859 instruction to behave as a DSB, ensuring the correct behaviour of 860 the two writes. 861 862config ARM_ERRATA_742231 863 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 864 depends on CPU_V7 && SMP 865 depends on !ARCH_MULTIPLATFORM 866 help 867 This option enables the workaround for the 742231 Cortex-A9 868 (r2p0..r2p2) erratum. Under certain conditions, specific to the 869 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 870 accessing some data located in the same cache line, may get corrupted 871 data due to bad handling of the address hazard when the line gets 872 replaced from one of the CPUs at the same time as another CPU is 873 accessing it. This workaround sets specific bits in the diagnostic 874 register of the Cortex-A9 which reduces the linefill issuing 875 capabilities of the processor. 876 877config ARM_ERRATA_643719 878 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 879 depends on CPU_V7 && SMP 880 default y 881 help 882 This option enables the workaround for the 643719 Cortex-A9 (prior to 883 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 884 register returns zero when it should return one. The workaround 885 corrects this value, ensuring cache maintenance operations which use 886 it behave as intended and avoiding data corruption. 887 888config ARM_ERRATA_720789 889 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 890 depends on CPU_V7 891 help 892 This option enables the workaround for the 720789 Cortex-A9 (prior to 893 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 894 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 895 As a consequence of this erratum, some TLB entries which should be 896 invalidated are not, resulting in an incoherency in the system page 897 tables. The workaround changes the TLB flushing routines to invalidate 898 entries regardless of the ASID. 899 900config ARM_ERRATA_743622 901 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 902 depends on CPU_V7 903 depends on !ARCH_MULTIPLATFORM 904 help 905 This option enables the workaround for the 743622 Cortex-A9 906 (r2p*) erratum. Under very rare conditions, a faulty 907 optimisation in the Cortex-A9 Store Buffer may lead to data 908 corruption. This workaround sets a specific bit in the diagnostic 909 register of the Cortex-A9 which disables the Store Buffer 910 optimisation, preventing the defect from occurring. This has no 911 visible impact on the overall performance or power consumption of the 912 processor. 913 914config ARM_ERRATA_751472 915 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 916 depends on CPU_V7 917 depends on !ARCH_MULTIPLATFORM 918 help 919 This option enables the workaround for the 751472 Cortex-A9 (prior 920 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 921 completion of a following broadcasted operation if the second 922 operation is received by a CPU before the ICIALLUIS has completed, 923 potentially leading to corrupted entries in the cache or TLB. 924 925config ARM_ERRATA_754322 926 bool "ARM errata: possible faulty MMU translations following an ASID switch" 927 depends on CPU_V7 928 help 929 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 930 r3p*) erratum. A speculative memory access may cause a page table walk 931 which starts prior to an ASID switch but completes afterwards. This 932 can populate the micro-TLB with a stale entry which may be hit with 933 the new ASID. This workaround places two dsb instructions in the mm 934 switching code so that no page table walks can cross the ASID switch. 935 936config ARM_ERRATA_754327 937 bool "ARM errata: no automatic Store Buffer drain" 938 depends on CPU_V7 && SMP 939 help 940 This option enables the workaround for the 754327 Cortex-A9 (prior to 941 r2p0) erratum. The Store Buffer does not have any automatic draining 942 mechanism and therefore a livelock may occur if an external agent 943 continuously polls a memory location waiting to observe an update. 944 This workaround defines cpu_relax() as smp_mb(), preventing correctly 945 written polling loops from denying visibility of updates to memory. 946 947config ARM_ERRATA_364296 948 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 949 depends on CPU_V6 950 help 951 This options enables the workaround for the 364296 ARM1136 952 r0p2 erratum (possible cache data corruption with 953 hit-under-miss enabled). It sets the undocumented bit 31 in 954 the auxiliary control register and the FI bit in the control 955 register, thus disabling hit-under-miss without putting the 956 processor into full low interrupt latency mode. ARM11MPCore 957 is not affected. 958 959config ARM_ERRATA_764369 960 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 961 depends on CPU_V7 && SMP 962 help 963 This option enables the workaround for erratum 764369 964 affecting Cortex-A9 MPCore with two or more processors (all 965 current revisions). Under certain timing circumstances, a data 966 cache line maintenance operation by MVA targeting an Inner 967 Shareable memory region may fail to proceed up to either the 968 Point of Coherency or to the Point of Unification of the 969 system. This workaround adds a DSB instruction before the 970 relevant cache maintenance functions and sets a specific bit 971 in the diagnostic control register of the SCU. 972 973config ARM_ERRATA_775420 974 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 975 depends on CPU_V7 976 help 977 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 978 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 979 operation aborts with MMU exception, it might cause the processor 980 to deadlock. This workaround puts DSB before executing ISB if 981 an abort may occur on cache maintenance. 982 983config ARM_ERRATA_798181 984 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 985 depends on CPU_V7 && SMP 986 help 987 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 988 adequately shooting down all use of the old entries. This 989 option enables the Linux kernel workaround for this erratum 990 which sends an IPI to the CPUs that are running the same ASID 991 as the one being invalidated. 992 993config ARM_ERRATA_773022 994 bool "ARM errata: incorrect instructions may be executed from loop buffer" 995 depends on CPU_V7 996 help 997 This option enables the workaround for the 773022 Cortex-A15 998 (up to r0p4) erratum. In certain rare sequences of code, the 999 loop buffer may deliver incorrect instructions. This 1000 workaround disables the loop buffer to avoid the erratum. 1001 1002config ARM_ERRATA_818325_852422 1003 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1004 depends on CPU_V7 1005 help 1006 This option enables the workaround for: 1007 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1008 instruction might deadlock. Fixed in r0p1. 1009 - Cortex-A12 852422: Execution of a sequence of instructions might 1010 lead to either a data corruption or a CPU deadlock. Not fixed in 1011 any Cortex-A12 cores yet. 1012 This workaround for all both errata involves setting bit[12] of the 1013 Feature Register. This bit disables an optimisation applied to a 1014 sequence of 2 instructions that use opposing condition codes. 1015 1016config ARM_ERRATA_821420 1017 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1018 depends on CPU_V7 1019 help 1020 This option enables the workaround for the 821420 Cortex-A12 1021 (all revs) erratum. In very rare timing conditions, a sequence 1022 of VMOV to Core registers instructions, for which the second 1023 one is in the shadow of a branch or abort, can lead to a 1024 deadlock when the VMOV instructions are issued out-of-order. 1025 1026config ARM_ERRATA_825619 1027 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1028 depends on CPU_V7 1029 help 1030 This option enables the workaround for the 825619 Cortex-A12 1031 (all revs) erratum. Within rare timing constraints, executing a 1032 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1033 and Device/Strongly-Ordered loads and stores might cause deadlock 1034 1035config ARM_ERRATA_857271 1036 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1037 depends on CPU_V7 1038 help 1039 This option enables the workaround for the 857271 Cortex-A12 1040 (all revs) erratum. Under very rare timing conditions, the CPU might 1041 hang. The workaround is expected to have a < 1% performance impact. 1042 1043config ARM_ERRATA_852421 1044 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1045 depends on CPU_V7 1046 help 1047 This option enables the workaround for the 852421 Cortex-A17 1048 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1049 execution of a DMB ST instruction might fail to properly order 1050 stores from GroupA and stores from GroupB. 1051 1052config ARM_ERRATA_852423 1053 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1054 depends on CPU_V7 1055 help 1056 This option enables the workaround for: 1057 - Cortex-A17 852423: Execution of a sequence of instructions might 1058 lead to either a data corruption or a CPU deadlock. Not fixed in 1059 any Cortex-A17 cores yet. 1060 This is identical to Cortex-A12 erratum 852422. It is a separate 1061 config option from the A12 erratum due to the way errata are checked 1062 for and handled. 1063 1064config ARM_ERRATA_857272 1065 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1066 depends on CPU_V7 1067 help 1068 This option enables the workaround for the 857272 Cortex-A17 erratum. 1069 This erratum is not known to be fixed in any A17 revision. 1070 This is identical to Cortex-A12 erratum 857271. It is a separate 1071 config option from the A12 erratum due to the way errata are checked 1072 for and handled. 1073 1074endmenu 1075 1076source "arch/arm/common/Kconfig" 1077 1078menu "Bus support" 1079 1080config ISA 1081 bool 1082 help 1083 Find out whether you have ISA slots on your motherboard. ISA is the 1084 name of a bus system, i.e. the way the CPU talks to the other stuff 1085 inside your box. Other bus systems are PCI, EISA, MicroChannel 1086 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1087 newer boards don't support it. If you have ISA, say Y, otherwise N. 1088 1089# Select ISA DMA controller support 1090config ISA_DMA 1091 bool 1092 select ISA_DMA_API 1093 1094# Select ISA DMA interface 1095config ISA_DMA_API 1096 bool 1097 1098config PCI_NANOENGINE 1099 bool "BSE nanoEngine PCI support" 1100 depends on SA1100_NANOENGINE 1101 help 1102 Enable PCI on the BSE nanoEngine board. 1103 1104config ARM_ERRATA_814220 1105 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1106 depends on CPU_V7 1107 help 1108 The v7 ARM states that all cache and branch predictor maintenance 1109 operations that do not specify an address execute, relative to 1110 each other, in program order. 1111 However, because of this erratum, an L2 set/way cache maintenance 1112 operation can overtake an L1 set/way cache maintenance operation. 1113 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1114 r0p4, r0p5. 1115 1116endmenu 1117 1118menu "Kernel Features" 1119 1120config HAVE_SMP 1121 bool 1122 help 1123 This option should be selected by machines which have an SMP- 1124 capable CPU. 1125 1126 The only effect of this option is to make the SMP-related 1127 options available to the user for configuration. 1128 1129config SMP 1130 bool "Symmetric Multi-Processing" 1131 depends on CPU_V6K || CPU_V7 1132 depends on HAVE_SMP 1133 depends on MMU || ARM_MPU 1134 select IRQ_WORK 1135 help 1136 This enables support for systems with more than one CPU. If you have 1137 a system with only one CPU, say N. If you have a system with more 1138 than one CPU, say Y. 1139 1140 If you say N here, the kernel will run on uni- and multiprocessor 1141 machines, but will use only one CPU of a multiprocessor machine. If 1142 you say Y here, the kernel will run on many, but not all, 1143 uniprocessor machines. On a uniprocessor machine, the kernel 1144 will run faster if you say N here. 1145 1146 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1147 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1148 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1149 1150 If you don't know what to do here, say N. 1151 1152config SMP_ON_UP 1153 bool "Allow booting SMP kernel on uniprocessor systems" 1154 depends on SMP && !XIP_KERNEL && MMU 1155 default y 1156 help 1157 SMP kernels contain instructions which fail on non-SMP processors. 1158 Enabling this option allows the kernel to modify itself to make 1159 these instructions safe. Disabling it allows about 1K of space 1160 savings. 1161 1162 If you don't know what to do here, say Y. 1163 1164 1165config CURRENT_POINTER_IN_TPIDRURO 1166 def_bool y 1167 depends on SMP && CPU_32v6K && !CPU_V6 1168 1169config ARM_CPU_TOPOLOGY 1170 bool "Support cpu topology definition" 1171 depends on SMP && CPU_V7 1172 default y 1173 help 1174 Support ARM cpu topology definition. The MPIDR register defines 1175 affinity between processors which is then used to describe the cpu 1176 topology of an ARM System. 1177 1178config SCHED_MC 1179 bool "Multi-core scheduler support" 1180 depends on ARM_CPU_TOPOLOGY 1181 help 1182 Multi-core scheduler support improves the CPU scheduler's decision 1183 making when dealing with multi-core CPU chips at a cost of slightly 1184 increased overhead in some places. If unsure say N here. 1185 1186config SCHED_SMT 1187 bool "SMT scheduler support" 1188 depends on ARM_CPU_TOPOLOGY 1189 help 1190 Improves the CPU scheduler's decision making when dealing with 1191 MultiThreading at a cost of slightly increased overhead in some 1192 places. If unsure say N here. 1193 1194config HAVE_ARM_SCU 1195 bool 1196 help 1197 This option enables support for the ARM snoop control unit 1198 1199config HAVE_ARM_ARCH_TIMER 1200 bool "Architected timer support" 1201 depends on CPU_V7 1202 select ARM_ARCH_TIMER 1203 help 1204 This option enables support for the ARM architected timer 1205 1206config HAVE_ARM_TWD 1207 bool 1208 help 1209 This options enables support for the ARM timer and watchdog unit 1210 1211config MCPM 1212 bool "Multi-Cluster Power Management" 1213 depends on CPU_V7 && SMP 1214 help 1215 This option provides the common power management infrastructure 1216 for (multi-)cluster based systems, such as big.LITTLE based 1217 systems. 1218 1219config MCPM_QUAD_CLUSTER 1220 bool 1221 depends on MCPM 1222 help 1223 To avoid wasting resources unnecessarily, MCPM only supports up 1224 to 2 clusters by default. 1225 Platforms with 3 or 4 clusters that use MCPM must select this 1226 option to allow the additional clusters to be managed. 1227 1228config BIG_LITTLE 1229 bool "big.LITTLE support (Experimental)" 1230 depends on CPU_V7 && SMP 1231 select MCPM 1232 help 1233 This option enables support selections for the big.LITTLE 1234 system architecture. 1235 1236config BL_SWITCHER 1237 bool "big.LITTLE switcher support" 1238 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1239 select CPU_PM 1240 help 1241 The big.LITTLE "switcher" provides the core functionality to 1242 transparently handle transition between a cluster of A15's 1243 and a cluster of A7's in a big.LITTLE system. 1244 1245config BL_SWITCHER_DUMMY_IF 1246 tristate "Simple big.LITTLE switcher user interface" 1247 depends on BL_SWITCHER && DEBUG_KERNEL 1248 help 1249 This is a simple and dummy char dev interface to control 1250 the big.LITTLE switcher core code. It is meant for 1251 debugging purposes only. 1252 1253choice 1254 prompt "Memory split" 1255 depends on MMU 1256 default VMSPLIT_3G 1257 help 1258 Select the desired split between kernel and user memory. 1259 1260 If you are not absolutely sure what you are doing, leave this 1261 option alone! 1262 1263 config VMSPLIT_3G 1264 bool "3G/1G user/kernel split" 1265 config VMSPLIT_3G_OPT 1266 depends on !ARM_LPAE 1267 bool "3G/1G user/kernel split (for full 1G low memory)" 1268 config VMSPLIT_2G 1269 bool "2G/2G user/kernel split" 1270 config VMSPLIT_1G 1271 bool "1G/3G user/kernel split" 1272endchoice 1273 1274config PAGE_OFFSET 1275 hex 1276 default PHYS_OFFSET if !MMU 1277 default 0x40000000 if VMSPLIT_1G 1278 default 0x80000000 if VMSPLIT_2G 1279 default 0xB0000000 if VMSPLIT_3G_OPT 1280 default 0xC0000000 1281 1282config KASAN_SHADOW_OFFSET 1283 hex 1284 depends on KASAN 1285 default 0x1f000000 if PAGE_OFFSET=0x40000000 1286 default 0x5f000000 if PAGE_OFFSET=0x80000000 1287 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1288 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1289 default 0xffffffff 1290 1291config NR_CPUS 1292 int "Maximum number of CPUs (2-32)" 1293 range 2 16 if DEBUG_KMAP_LOCAL 1294 range 2 32 if !DEBUG_KMAP_LOCAL 1295 depends on SMP 1296 default "4" 1297 help 1298 The maximum number of CPUs that the kernel can support. 1299 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1300 debugging is enabled, which uses half of the per-CPU fixmap 1301 slots as guard regions. 1302 1303config HOTPLUG_CPU 1304 bool "Support for hot-pluggable CPUs" 1305 depends on SMP 1306 select GENERIC_IRQ_MIGRATION 1307 help 1308 Say Y here to experiment with turning CPUs off and on. CPUs 1309 can be controlled through /sys/devices/system/cpu. 1310 1311config ARM_PSCI 1312 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1313 depends on HAVE_ARM_SMCCC 1314 select ARM_PSCI_FW 1315 help 1316 Say Y here if you want Linux to communicate with system firmware 1317 implementing the PSCI specification for CPU-centric power 1318 management operations described in ARM document number ARM DEN 1319 0022A ("Power State Coordination Interface System Software on 1320 ARM processors"). 1321 1322# The GPIO number here must be sorted by descending number. In case of 1323# a multiplatform kernel, we just want the highest value required by the 1324# selected platforms. 1325config ARCH_NR_GPIO 1326 int 1327 default 2048 if ARCH_INTEL_SOCFPGA 1328 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1329 ARCH_ZYNQ || ARCH_ASPEED 1330 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1331 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1332 default 416 if ARCH_SUNXI 1333 default 392 if ARCH_U8500 1334 default 352 if ARCH_VT8500 1335 default 288 if ARCH_ROCKCHIP 1336 default 264 if MACH_H4700 1337 default 0 1338 help 1339 Maximum number of GPIOs in the system. 1340 1341 If unsure, leave the default value. 1342 1343config HZ_FIXED 1344 int 1345 default 128 if SOC_AT91RM9200 1346 default 0 1347 1348choice 1349 depends on HZ_FIXED = 0 1350 prompt "Timer frequency" 1351 1352config HZ_100 1353 bool "100 Hz" 1354 1355config HZ_200 1356 bool "200 Hz" 1357 1358config HZ_250 1359 bool "250 Hz" 1360 1361config HZ_300 1362 bool "300 Hz" 1363 1364config HZ_500 1365 bool "500 Hz" 1366 1367config HZ_1000 1368 bool "1000 Hz" 1369 1370endchoice 1371 1372config HZ 1373 int 1374 default HZ_FIXED if HZ_FIXED != 0 1375 default 100 if HZ_100 1376 default 200 if HZ_200 1377 default 250 if HZ_250 1378 default 300 if HZ_300 1379 default 500 if HZ_500 1380 default 1000 1381 1382config SCHED_HRTICK 1383 def_bool HIGH_RES_TIMERS 1384 1385config THUMB2_KERNEL 1386 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1387 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1388 default y if CPU_THUMBONLY 1389 select ARM_UNWIND 1390 help 1391 By enabling this option, the kernel will be compiled in 1392 Thumb-2 mode. 1393 1394 If unsure, say N. 1395 1396config ARM_PATCH_IDIV 1397 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1398 depends on CPU_32v7 && !XIP_KERNEL 1399 default y 1400 help 1401 The ARM compiler inserts calls to __aeabi_idiv() and 1402 __aeabi_uidiv() when it needs to perform division on signed 1403 and unsigned integers. Some v7 CPUs have support for the sdiv 1404 and udiv instructions that can be used to implement those 1405 functions. 1406 1407 Enabling this option allows the kernel to modify itself to 1408 replace the first two instructions of these library functions 1409 with the sdiv or udiv plus "bx lr" instructions when the CPU 1410 it is running on supports them. Typically this will be faster 1411 and less power intensive than running the original library 1412 code to do integer division. 1413 1414config AEABI 1415 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1416 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1417 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1418 help 1419 This option allows for the kernel to be compiled using the latest 1420 ARM ABI (aka EABI). This is only useful if you are using a user 1421 space environment that is also compiled with EABI. 1422 1423 Since there are major incompatibilities between the legacy ABI and 1424 EABI, especially with regard to structure member alignment, this 1425 option also changes the kernel syscall calling convention to 1426 disambiguate both ABIs and allow for backward compatibility support 1427 (selected with CONFIG_OABI_COMPAT). 1428 1429 To use this you need GCC version 4.0.0 or later. 1430 1431config OABI_COMPAT 1432 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1433 depends on AEABI && !THUMB2_KERNEL 1434 help 1435 This option preserves the old syscall interface along with the 1436 new (ARM EABI) one. It also provides a compatibility layer to 1437 intercept syscalls that have structure arguments which layout 1438 in memory differs between the legacy ABI and the new ARM EABI 1439 (only for non "thumb" binaries). This option adds a tiny 1440 overhead to all syscalls and produces a slightly larger kernel. 1441 1442 The seccomp filter system will not be available when this is 1443 selected, since there is no way yet to sensibly distinguish 1444 between calling conventions during filtering. 1445 1446 If you know you'll be using only pure EABI user space then you 1447 can say N here. If this option is not selected and you attempt 1448 to execute a legacy ABI binary then the result will be 1449 UNPREDICTABLE (in fact it can be predicted that it won't work 1450 at all). If in doubt say N. 1451 1452config ARCH_SELECT_MEMORY_MODEL 1453 bool 1454 1455config ARCH_FLATMEM_ENABLE 1456 bool 1457 1458config ARCH_SPARSEMEM_ENABLE 1459 bool 1460 select SPARSEMEM_STATIC if SPARSEMEM 1461 1462config HIGHMEM 1463 bool "High Memory Support" 1464 depends on MMU 1465 select KMAP_LOCAL 1466 help 1467 The address space of ARM processors is only 4 Gigabytes large 1468 and it has to accommodate user address space, kernel address 1469 space as well as some memory mapped IO. That means that, if you 1470 have a large amount of physical memory and/or IO, not all of the 1471 memory can be "permanently mapped" by the kernel. The physical 1472 memory that is not permanently mapped is called "high memory". 1473 1474 Depending on the selected kernel/user memory split, minimum 1475 vmalloc space and actual amount of RAM, you may not need this 1476 option which should result in a slightly faster kernel. 1477 1478 If unsure, say n. 1479 1480config HIGHPTE 1481 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1482 depends on HIGHMEM 1483 default y 1484 help 1485 The VM uses one page of physical memory for each page table. 1486 For systems with a lot of processes, this can use a lot of 1487 precious low memory, eventually leading to low memory being 1488 consumed by page tables. Setting this option will allow 1489 user-space 2nd level page tables to reside in high memory. 1490 1491config CPU_SW_DOMAIN_PAN 1492 bool "Enable use of CPU domains to implement privileged no-access" 1493 depends on MMU && !ARM_LPAE 1494 default y 1495 help 1496 Increase kernel security by ensuring that normal kernel accesses 1497 are unable to access userspace addresses. This can help prevent 1498 use-after-free bugs becoming an exploitable privilege escalation 1499 by ensuring that magic values (such as LIST_POISON) will always 1500 fault when dereferenced. 1501 1502 CPUs with low-vector mappings use a best-efforts implementation. 1503 Their lower 1MB needs to remain accessible for the vectors, but 1504 the remainder of userspace will become appropriately inaccessible. 1505 1506config HW_PERF_EVENTS 1507 def_bool y 1508 depends on ARM_PMU 1509 1510config ARCH_WANT_GENERAL_HUGETLB 1511 def_bool y 1512 1513config ARM_MODULE_PLTS 1514 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1515 depends on MODULES 1516 default y 1517 help 1518 Allocate PLTs when loading modules so that jumps and calls whose 1519 targets are too far away for their relative offsets to be encoded 1520 in the instructions themselves can be bounced via veneers in the 1521 module's PLT. This allows modules to be allocated in the generic 1522 vmalloc area after the dedicated module memory area has been 1523 exhausted. The modules will use slightly more memory, but after 1524 rounding up to page size, the actual memory footprint is usually 1525 the same. 1526 1527 Disabling this is usually safe for small single-platform 1528 configurations. If unsure, say y. 1529 1530config FORCE_MAX_ZONEORDER 1531 int "Maximum zone order" 1532 default "12" if SOC_AM33XX 1533 default "9" if SA1111 1534 default "11" 1535 help 1536 The kernel memory allocator divides physically contiguous memory 1537 blocks into "zones", where each zone is a power of two number of 1538 pages. This option selects the largest power of two that the kernel 1539 keeps in the memory allocator. If you need to allocate very large 1540 blocks of physically contiguous memory, then you may need to 1541 increase this value. 1542 1543 This config option is actually maximum order plus one. For example, 1544 a value of 11 means that the largest free memory block is 2^10 pages. 1545 1546config ALIGNMENT_TRAP 1547 def_bool CPU_CP15_MMU 1548 select HAVE_PROC_CPU if PROC_FS 1549 help 1550 ARM processors cannot fetch/store information which is not 1551 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1552 address divisible by 4. On 32-bit ARM processors, these non-aligned 1553 fetch/store instructions will be emulated in software if you say 1554 here, which has a severe performance impact. This is necessary for 1555 correct operation of some network protocols. With an IP-only 1556 configuration it is safe to say N, otherwise say Y. 1557 1558config UACCESS_WITH_MEMCPY 1559 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1560 depends on MMU 1561 default y if CPU_FEROCEON 1562 help 1563 Implement faster copy_to_user and clear_user methods for CPU 1564 cores where a 8-word STM instruction give significantly higher 1565 memory write throughput than a sequence of individual 32bit stores. 1566 1567 A possible side effect is a slight increase in scheduling latency 1568 between threads sharing the same address space if they invoke 1569 such copy operations with large buffers. 1570 1571 However, if the CPU data cache is using a write-allocate mode, 1572 this option is unlikely to provide any performance gain. 1573 1574config PARAVIRT 1575 bool "Enable paravirtualization code" 1576 help 1577 This changes the kernel so it can modify itself when it is run 1578 under a hypervisor, potentially improving performance significantly 1579 over full virtualization. 1580 1581config PARAVIRT_TIME_ACCOUNTING 1582 bool "Paravirtual steal time accounting" 1583 select PARAVIRT 1584 help 1585 Select this option to enable fine granularity task steal time 1586 accounting. Time spent executing other tasks in parallel with 1587 the current vCPU is discounted from the vCPU power. To account for 1588 that, there can be a small performance impact. 1589 1590 If in doubt, say N here. 1591 1592config XEN_DOM0 1593 def_bool y 1594 depends on XEN 1595 1596config XEN 1597 bool "Xen guest support on ARM" 1598 depends on ARM && AEABI && OF 1599 depends on CPU_V7 && !CPU_V6 1600 depends on !GENERIC_ATOMIC64 1601 depends on MMU 1602 select ARCH_DMA_ADDR_T_64BIT 1603 select ARM_PSCI 1604 select SWIOTLB 1605 select SWIOTLB_XEN 1606 select PARAVIRT 1607 help 1608 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1609 1610config STACKPROTECTOR_PER_TASK 1611 bool "Use a unique stack canary value for each task" 1612 depends on GCC_PLUGINS && STACKPROTECTOR && THREAD_INFO_IN_TASK && !XIP_DEFLATED_DATA 1613 select GCC_PLUGIN_ARM_SSP_PER_TASK 1614 default y 1615 help 1616 Due to the fact that GCC uses an ordinary symbol reference from 1617 which to load the value of the stack canary, this value can only 1618 change at reboot time on SMP systems, and all tasks running in the 1619 kernel's address space are forced to use the same canary value for 1620 the entire duration that the system is up. 1621 1622 Enable this option to switch to a different method that uses a 1623 different canary value for each task. 1624 1625endmenu 1626 1627menu "Boot options" 1628 1629config USE_OF 1630 bool "Flattened Device Tree support" 1631 select IRQ_DOMAIN 1632 select OF 1633 help 1634 Include support for flattened device tree machine descriptions. 1635 1636config ATAGS 1637 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1638 default y 1639 help 1640 This is the traditional way of passing data to the kernel at boot 1641 time. If you are solely relying on the flattened device tree (or 1642 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1643 to remove ATAGS support from your kernel binary. If unsure, 1644 leave this to y. 1645 1646config DEPRECATED_PARAM_STRUCT 1647 bool "Provide old way to pass kernel parameters" 1648 depends on ATAGS 1649 help 1650 This was deprecated in 2001 and announced to live on for 5 years. 1651 Some old boot loaders still use this way. 1652 1653# Compressed boot loader in ROM. Yes, we really want to ask about 1654# TEXT and BSS so we preserve their values in the config files. 1655config ZBOOT_ROM_TEXT 1656 hex "Compressed ROM boot loader base address" 1657 default 0x0 1658 help 1659 The physical address at which the ROM-able zImage is to be 1660 placed in the target. Platforms which normally make use of 1661 ROM-able zImage formats normally set this to a suitable 1662 value in their defconfig file. 1663 1664 If ZBOOT_ROM is not enabled, this has no effect. 1665 1666config ZBOOT_ROM_BSS 1667 hex "Compressed ROM boot loader BSS address" 1668 default 0x0 1669 help 1670 The base address of an area of read/write memory in the target 1671 for the ROM-able zImage which must be available while the 1672 decompressor is running. It must be large enough to hold the 1673 entire decompressed kernel plus an additional 128 KiB. 1674 Platforms which normally make use of ROM-able zImage formats 1675 normally set this to a suitable value in their defconfig file. 1676 1677 If ZBOOT_ROM is not enabled, this has no effect. 1678 1679config ZBOOT_ROM 1680 bool "Compressed boot loader in ROM/flash" 1681 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1682 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1683 help 1684 Say Y here if you intend to execute your compressed kernel image 1685 (zImage) directly from ROM or flash. If unsure, say N. 1686 1687config ARM_APPENDED_DTB 1688 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1689 depends on OF 1690 help 1691 With this option, the boot code will look for a device tree binary 1692 (DTB) appended to zImage 1693 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1694 1695 This is meant as a backward compatibility convenience for those 1696 systems with a bootloader that can't be upgraded to accommodate 1697 the documented boot protocol using a device tree. 1698 1699 Beware that there is very little in terms of protection against 1700 this option being confused by leftover garbage in memory that might 1701 look like a DTB header after a reboot if no actual DTB is appended 1702 to zImage. Do not leave this option active in a production kernel 1703 if you don't intend to always append a DTB. Proper passing of the 1704 location into r2 of a bootloader provided DTB is always preferable 1705 to this option. 1706 1707config ARM_ATAG_DTB_COMPAT 1708 bool "Supplement the appended DTB with traditional ATAG information" 1709 depends on ARM_APPENDED_DTB 1710 help 1711 Some old bootloaders can't be updated to a DTB capable one, yet 1712 they provide ATAGs with memory configuration, the ramdisk address, 1713 the kernel cmdline string, etc. Such information is dynamically 1714 provided by the bootloader and can't always be stored in a static 1715 DTB. To allow a device tree enabled kernel to be used with such 1716 bootloaders, this option allows zImage to extract the information 1717 from the ATAG list and store it at run time into the appended DTB. 1718 1719choice 1720 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1721 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1722 1723config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1724 bool "Use bootloader kernel arguments if available" 1725 help 1726 Uses the command-line options passed by the boot loader instead of 1727 the device tree bootargs property. If the boot loader doesn't provide 1728 any, the device tree bootargs property will be used. 1729 1730config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1731 bool "Extend with bootloader kernel arguments" 1732 help 1733 The command-line arguments provided by the boot loader will be 1734 appended to the the device tree bootargs property. 1735 1736endchoice 1737 1738config CMDLINE 1739 string "Default kernel command string" 1740 default "" 1741 help 1742 On some architectures (e.g. CATS), there is currently no way 1743 for the boot loader to pass arguments to the kernel. For these 1744 architectures, you should supply some command-line options at build 1745 time by entering them here. As a minimum, you should specify the 1746 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1747 1748choice 1749 prompt "Kernel command line type" if CMDLINE != "" 1750 default CMDLINE_FROM_BOOTLOADER 1751 depends on ATAGS 1752 1753config CMDLINE_FROM_BOOTLOADER 1754 bool "Use bootloader kernel arguments if available" 1755 help 1756 Uses the command-line options passed by the boot loader. If 1757 the boot loader doesn't provide any, the default kernel command 1758 string provided in CMDLINE will be used. 1759 1760config CMDLINE_EXTEND 1761 bool "Extend bootloader kernel arguments" 1762 help 1763 The command-line arguments provided by the boot loader will be 1764 appended to the default kernel command string. 1765 1766config CMDLINE_FORCE 1767 bool "Always use the default kernel command string" 1768 help 1769 Always use the default kernel command string, even if the boot 1770 loader passes other arguments to the kernel. 1771 This is useful if you cannot or don't want to change the 1772 command-line options your boot loader passes to the kernel. 1773endchoice 1774 1775config XIP_KERNEL 1776 bool "Kernel Execute-In-Place from ROM" 1777 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1778 help 1779 Execute-In-Place allows the kernel to run from non-volatile storage 1780 directly addressable by the CPU, such as NOR flash. This saves RAM 1781 space since the text section of the kernel is not loaded from flash 1782 to RAM. Read-write sections, such as the data section and stack, 1783 are still copied to RAM. The XIP kernel is not compressed since 1784 it has to run directly from flash, so it will take more space to 1785 store it. The flash address used to link the kernel object files, 1786 and for storing it, is configuration dependent. Therefore, if you 1787 say Y here, you must know the proper physical address where to 1788 store the kernel image depending on your own flash memory usage. 1789 1790 Also note that the make target becomes "make xipImage" rather than 1791 "make zImage" or "make Image". The final kernel binary to put in 1792 ROM memory will be arch/arm/boot/xipImage. 1793 1794 If unsure, say N. 1795 1796config XIP_PHYS_ADDR 1797 hex "XIP Kernel Physical Location" 1798 depends on XIP_KERNEL 1799 default "0x00080000" 1800 help 1801 This is the physical address in your flash memory the kernel will 1802 be linked for and stored to. This address is dependent on your 1803 own flash usage. 1804 1805config XIP_DEFLATED_DATA 1806 bool "Store kernel .data section compressed in ROM" 1807 depends on XIP_KERNEL 1808 select ZLIB_INFLATE 1809 help 1810 Before the kernel is actually executed, its .data section has to be 1811 copied to RAM from ROM. This option allows for storing that data 1812 in compressed form and decompressed to RAM rather than merely being 1813 copied, saving some precious ROM space. A possible drawback is a 1814 slightly longer boot delay. 1815 1816config KEXEC 1817 bool "Kexec system call (EXPERIMENTAL)" 1818 depends on (!SMP || PM_SLEEP_SMP) 1819 depends on MMU 1820 select KEXEC_CORE 1821 help 1822 kexec is a system call that implements the ability to shutdown your 1823 current kernel, and to start another kernel. It is like a reboot 1824 but it is independent of the system firmware. And like a reboot 1825 you can start any kernel with it, not just Linux. 1826 1827 It is an ongoing process to be certain the hardware in a machine 1828 is properly shutdown, so do not be surprised if this code does not 1829 initially work for you. 1830 1831config ATAGS_PROC 1832 bool "Export atags in procfs" 1833 depends on ATAGS && KEXEC 1834 default y 1835 help 1836 Should the atags used to boot the kernel be exported in an "atags" 1837 file in procfs. Useful with kexec. 1838 1839config CRASH_DUMP 1840 bool "Build kdump crash kernel (EXPERIMENTAL)" 1841 help 1842 Generate crash dump after being started by kexec. This should 1843 be normally only set in special crash dump kernels which are 1844 loaded in the main kernel with kexec-tools into a specially 1845 reserved region and then later executed after a crash by 1846 kdump/kexec. The crash dump kernel must be compiled to a 1847 memory address not used by the main kernel 1848 1849 For more details see Documentation/admin-guide/kdump/kdump.rst 1850 1851config AUTO_ZRELADDR 1852 bool "Auto calculation of the decompressed kernel image address" 1853 help 1854 ZRELADDR is the physical address where the decompressed kernel 1855 image will be placed. If AUTO_ZRELADDR is selected, the address 1856 will be determined at run-time, either by masking the current IP 1857 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1858 This assumes the zImage being placed in the first 128MB from 1859 start of memory. 1860 1861config EFI_STUB 1862 bool 1863 1864config EFI 1865 bool "UEFI runtime support" 1866 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1867 select UCS2_STRING 1868 select EFI_PARAMS_FROM_FDT 1869 select EFI_STUB 1870 select EFI_GENERIC_STUB 1871 select EFI_RUNTIME_WRAPPERS 1872 help 1873 This option provides support for runtime services provided 1874 by UEFI firmware (such as non-volatile variables, realtime 1875 clock, and platform reset). A UEFI stub is also provided to 1876 allow the kernel to be booted as an EFI application. This 1877 is only useful for kernels that may run on systems that have 1878 UEFI firmware. 1879 1880config DMI 1881 bool "Enable support for SMBIOS (DMI) tables" 1882 depends on EFI 1883 default y 1884 help 1885 This enables SMBIOS/DMI feature for systems. 1886 1887 This option is only useful on systems that have UEFI firmware. 1888 However, even with this option, the resultant kernel should 1889 continue to boot on existing non-UEFI platforms. 1890 1891 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1892 i.e., the the practice of identifying the platform via DMI to 1893 decide whether certain workarounds for buggy hardware and/or 1894 firmware need to be enabled. This would require the DMI subsystem 1895 to be enabled much earlier than we do on ARM, which is non-trivial. 1896 1897endmenu 1898 1899menu "CPU Power Management" 1900 1901source "drivers/cpufreq/Kconfig" 1902 1903source "drivers/cpuidle/Kconfig" 1904 1905endmenu 1906 1907menu "Floating point emulation" 1908 1909comment "At least one emulation must be selected" 1910 1911config FPE_NWFPE 1912 bool "NWFPE math emulation" 1913 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1914 help 1915 Say Y to include the NWFPE floating point emulator in the kernel. 1916 This is necessary to run most binaries. Linux does not currently 1917 support floating point hardware so you need to say Y here even if 1918 your machine has an FPA or floating point co-processor podule. 1919 1920 You may say N here if you are going to load the Acorn FPEmulator 1921 early in the bootup. 1922 1923config FPE_NWFPE_XP 1924 bool "Support extended precision" 1925 depends on FPE_NWFPE 1926 help 1927 Say Y to include 80-bit support in the kernel floating-point 1928 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1929 Note that gcc does not generate 80-bit operations by default, 1930 so in most cases this option only enlarges the size of the 1931 floating point emulator without any good reason. 1932 1933 You almost surely want to say N here. 1934 1935config FPE_FASTFPE 1936 bool "FastFPE math emulation (EXPERIMENTAL)" 1937 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1938 help 1939 Say Y here to include the FAST floating point emulator in the kernel. 1940 This is an experimental much faster emulator which now also has full 1941 precision for the mantissa. It does not support any exceptions. 1942 It is very simple, and approximately 3-6 times faster than NWFPE. 1943 1944 It should be sufficient for most programs. It may be not suitable 1945 for scientific calculations, but you have to check this for yourself. 1946 If you do not feel you need a faster FP emulation you should better 1947 choose NWFPE. 1948 1949config VFP 1950 bool "VFP-format floating point maths" 1951 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1952 help 1953 Say Y to include VFP support code in the kernel. This is needed 1954 if your hardware includes a VFP unit. 1955 1956 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1957 release notes and additional status information. 1958 1959 Say N if your target does not have VFP hardware. 1960 1961config VFPv3 1962 bool 1963 depends on VFP 1964 default y if CPU_V7 1965 1966config NEON 1967 bool "Advanced SIMD (NEON) Extension support" 1968 depends on VFPv3 && CPU_V7 1969 help 1970 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1971 Extension. 1972 1973config KERNEL_MODE_NEON 1974 bool "Support for NEON in kernel mode" 1975 depends on NEON && AEABI 1976 help 1977 Say Y to include support for NEON in kernel mode. 1978 1979endmenu 1980 1981menu "Power management options" 1982 1983source "kernel/power/Kconfig" 1984 1985config ARCH_SUSPEND_POSSIBLE 1986 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1987 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1988 def_bool y 1989 1990config ARM_CPU_SUSPEND 1991 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1992 depends on ARCH_SUSPEND_POSSIBLE 1993 1994config ARCH_HIBERNATION_POSSIBLE 1995 bool 1996 depends on MMU 1997 default y if ARCH_SUSPEND_POSSIBLE 1998 1999endmenu 2000 2001if CRYPTO 2002source "arch/arm/crypto/Kconfig" 2003endif 2004 2005source "arch/arm/Kconfig.assembler" 2006