1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select ARCH_WANT_LD_ORPHAN_WARN 39 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 40 select BUILDTIME_TABLE_SORT if MMU 41 select CLONE_BACKWARDS 42 select CPU_PM if SUSPEND || CPU_IDLE 43 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 44 select DMA_DECLARE_COHERENT 45 select DMA_OPS 46 select DMA_REMAP if MMU 47 select EDAC_SUPPORT 48 select EDAC_ATOMIC_SCRUB 49 select GENERIC_ALLOCATOR 50 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 51 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 52 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 53 select GENERIC_IRQ_IPI if SMP 54 select GENERIC_CPU_AUTOPROBE 55 select GENERIC_EARLY_IOREMAP 56 select GENERIC_IDLE_POLL_SETUP 57 select GENERIC_IRQ_PROBE 58 select GENERIC_IRQ_SHOW 59 select GENERIC_IRQ_SHOW_LEVEL 60 select GENERIC_PCI_IOMAP 61 select GENERIC_SCHED_CLOCK 62 select GENERIC_SMP_IDLE_THREAD 63 select GENERIC_STRNCPY_FROM_USER 64 select GENERIC_STRNLEN_USER 65 select HANDLE_DOMAIN_IRQ 66 select HARDIRQS_SW_RESEND 67 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 68 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 69 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 70 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 71 select HAVE_ARCH_MMAP_RND_BITS if MMU 72 select HAVE_ARCH_PFN_VALID 73 select HAVE_ARCH_SECCOMP 74 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 75 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 76 select HAVE_ARCH_TRACEHOOK 77 select HAVE_ARM_SMCCC if CPU_V7 78 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 79 select HAVE_CONTEXT_TRACKING 80 select HAVE_C_RECORDMCOUNT 81 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 82 select HAVE_DMA_CONTIGUOUS if MMU 83 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 84 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 85 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 86 select HAVE_EXIT_THREAD 87 select HAVE_FAST_GUP if ARM_LPAE 88 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 89 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 90 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 91 select HAVE_GCC_PLUGINS 92 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 93 select HAVE_IDE if PCI || ISA || PCMCIA 94 select HAVE_IRQ_TIME_ACCOUNTING 95 select HAVE_KERNEL_GZIP 96 select HAVE_KERNEL_LZ4 97 select HAVE_KERNEL_LZMA 98 select HAVE_KERNEL_LZO 99 select HAVE_KERNEL_XZ 100 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 101 select HAVE_KRETPROBES if HAVE_KPROBES 102 select HAVE_MOD_ARCH_SPECIFIC 103 select HAVE_NMI 104 select HAVE_OPROFILE if HAVE_PERF_EVENTS 105 select HAVE_OPTPROBES if !THUMB2_KERNEL 106 select HAVE_PERF_EVENTS 107 select HAVE_PERF_REGS 108 select HAVE_PERF_USER_STACK_DUMP 109 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 110 select HAVE_REGS_AND_STACK_ACCESS_API 111 select HAVE_RSEQ 112 select HAVE_STACKPROTECTOR 113 select HAVE_SYSCALL_TRACEPOINTS 114 select HAVE_UID16 115 select HAVE_VIRT_CPU_ACCOUNTING_GEN 116 select IRQ_FORCED_THREADING 117 select MODULES_USE_ELF_REL 118 select NEED_DMA_MAP_STATE 119 select OF_EARLY_FLATTREE if OF 120 select OLD_SIGACTION 121 select OLD_SIGSUSPEND3 122 select PCI_SYSCALL if PCI 123 select PERF_USE_VMALLOC 124 select RTC_LIB 125 select SET_FS 126 select SYS_SUPPORTS_APM_EMULATION 127 # Above selects are sorted alphabetically; please add new ones 128 # according to that. Thanks. 129 help 130 The ARM series is a line of low-power-consumption RISC chip designs 131 licensed by ARM Ltd and targeted at embedded applications and 132 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 133 manufactured, but legacy ARM-based PC hardware remains popular in 134 Europe. There is an ARM Linux project with a web page at 135 <http://www.arm.linux.org.uk/>. 136 137config ARM_HAS_SG_CHAIN 138 bool 139 140config ARM_DMA_USE_IOMMU 141 bool 142 select ARM_HAS_SG_CHAIN 143 select NEED_SG_DMA_LENGTH 144 145if ARM_DMA_USE_IOMMU 146 147config ARM_DMA_IOMMU_ALIGNMENT 148 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 149 range 4 9 150 default 8 151 help 152 DMA mapping framework by default aligns all buffers to the smallest 153 PAGE_SIZE order which is greater than or equal to the requested buffer 154 size. This works well for buffers up to a few hundreds kilobytes, but 155 for larger buffers it just a waste of address space. Drivers which has 156 relatively small addressing window (like 64Mib) might run out of 157 virtual space with just a few allocations. 158 159 With this parameter you can specify the maximum PAGE_SIZE order for 160 DMA IOMMU buffers. Larger buffers will be aligned only to this 161 specified order. The order is expressed as a power of two multiplied 162 by the PAGE_SIZE. 163 164endif 165 166config SYS_SUPPORTS_APM_EMULATION 167 bool 168 169config HAVE_TCM 170 bool 171 select GENERIC_ALLOCATOR 172 173config HAVE_PROC_CPU 174 bool 175 176config NO_IOPORT_MAP 177 bool 178 179config SBUS 180 bool 181 182config STACKTRACE_SUPPORT 183 bool 184 default y 185 186config LOCKDEP_SUPPORT 187 bool 188 default y 189 190config TRACE_IRQFLAGS_SUPPORT 191 bool 192 default !CPU_V7M 193 194config ARCH_HAS_ILOG2_U32 195 bool 196 197config ARCH_HAS_ILOG2_U64 198 bool 199 200config ARCH_HAS_BANDGAP 201 bool 202 203config FIX_EARLYCON_MEM 204 def_bool y if MMU 205 206config GENERIC_HWEIGHT 207 bool 208 default y 209 210config GENERIC_CALIBRATE_DELAY 211 bool 212 default y 213 214config ARCH_MAY_HAVE_PC_FDC 215 bool 216 217config ZONE_DMA 218 bool 219 220config ARCH_SUPPORTS_UPROBES 221 def_bool y 222 223config ARCH_HAS_DMA_SET_COHERENT_MASK 224 bool 225 226config GENERIC_ISA_DMA 227 bool 228 229config FIQ 230 bool 231 232config NEED_RET_TO_USER 233 bool 234 235config ARCH_MTD_XIP 236 bool 237 238config ARM_PATCH_PHYS_VIRT 239 bool "Patch physical to virtual translations at runtime" if EMBEDDED 240 default y 241 depends on !XIP_KERNEL && MMU 242 help 243 Patch phys-to-virt and virt-to-phys translation functions at 244 boot and module load time according to the position of the 245 kernel in system memory. 246 247 This can only be used with non-XIP MMU kernels where the base 248 of physical memory is at a 16MB boundary. 249 250 Only disable this option if you know that you do not require 251 this feature (eg, building a kernel for a single machine) and 252 you need to shrink the kernel to the minimal size. 253 254config NEED_MACH_IO_H 255 bool 256 help 257 Select this when mach/io.h is required to provide special 258 definitions for this platform. The need for mach/io.h should 259 be avoided when possible. 260 261config NEED_MACH_MEMORY_H 262 bool 263 help 264 Select this when mach/memory.h is required to provide special 265 definitions for this platform. The need for mach/memory.h should 266 be avoided when possible. 267 268config PHYS_OFFSET 269 hex "Physical address of main memory" if MMU 270 depends on !ARM_PATCH_PHYS_VIRT 271 default DRAM_BASE if !MMU 272 default 0x00000000 if ARCH_FOOTBRIDGE 273 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 274 default 0x20000000 if ARCH_S5PV210 275 default 0xc0000000 if ARCH_SA1100 276 help 277 Please provide the physical address corresponding to the 278 location of main memory in your system. 279 280config GENERIC_BUG 281 def_bool y 282 depends on BUG 283 284config PGTABLE_LEVELS 285 int 286 default 3 if ARM_LPAE 287 default 2 288 289menu "System Type" 290 291config MMU 292 bool "MMU-based Paged Memory Management Support" 293 default y 294 help 295 Select if you want MMU-based virtualised addressing space 296 support by paged memory management. If unsure, say 'Y'. 297 298config ARCH_MMAP_RND_BITS_MIN 299 default 8 300 301config ARCH_MMAP_RND_BITS_MAX 302 default 14 if PAGE_OFFSET=0x40000000 303 default 15 if PAGE_OFFSET=0x80000000 304 default 16 305 306# 307# The "ARM system type" choice list is ordered alphabetically by option 308# text. Please add new entries in the option alphabetic order. 309# 310choice 311 prompt "ARM system type" 312 default ARM_SINGLE_ARMV7M if !MMU 313 default ARCH_MULTIPLATFORM if MMU 314 315config ARCH_MULTIPLATFORM 316 bool "Allow multiple platforms to be selected" 317 depends on MMU 318 select ARCH_FLATMEM_ENABLE 319 select ARCH_SPARSEMEM_ENABLE 320 select ARCH_SELECT_MEMORY_MODEL 321 select ARM_HAS_SG_CHAIN 322 select ARM_PATCH_PHYS_VIRT 323 select AUTO_ZRELADDR 324 select TIMER_OF 325 select COMMON_CLK 326 select GENERIC_IRQ_MULTI_HANDLER 327 select HAVE_PCI 328 select PCI_DOMAINS_GENERIC if PCI 329 select SPARSE_IRQ 330 select USE_OF 331 332config ARM_SINGLE_ARMV7M 333 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 334 depends on !MMU 335 select ARM_NVIC 336 select AUTO_ZRELADDR 337 select TIMER_OF 338 select COMMON_CLK 339 select CPU_V7M 340 select NO_IOPORT_MAP 341 select SPARSE_IRQ 342 select USE_OF 343 344config ARCH_EP93XX 345 bool "EP93xx-based" 346 select ARCH_SPARSEMEM_ENABLE 347 select ARM_AMBA 348 imply ARM_PATCH_PHYS_VIRT 349 select ARM_VIC 350 select AUTO_ZRELADDR 351 select CLKDEV_LOOKUP 352 select CLKSRC_MMIO 353 select CPU_ARM920T 354 select GPIOLIB 355 select HAVE_LEGACY_CLK 356 help 357 This enables support for the Cirrus EP93xx series of CPUs. 358 359config ARCH_FOOTBRIDGE 360 bool "FootBridge" 361 select CPU_SA110 362 select FOOTBRIDGE 363 select HAVE_IDE 364 select NEED_MACH_IO_H if !MMU 365 select NEED_MACH_MEMORY_H 366 help 367 Support for systems based on the DC21285 companion chip 368 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 369 370config ARCH_IOP32X 371 bool "IOP32x-based" 372 depends on MMU 373 select CPU_XSCALE 374 select GPIO_IOP 375 select GPIOLIB 376 select NEED_RET_TO_USER 377 select FORCE_PCI 378 select PLAT_IOP 379 help 380 Support for Intel's 80219 and IOP32X (XScale) family of 381 processors. 382 383config ARCH_IXP4XX 384 bool "IXP4xx-based" 385 depends on MMU 386 select ARCH_HAS_DMA_SET_COHERENT_MASK 387 select ARCH_SUPPORTS_BIG_ENDIAN 388 select CPU_XSCALE 389 select DMABOUNCE if PCI 390 select GENERIC_IRQ_MULTI_HANDLER 391 select GPIO_IXP4XX 392 select GPIOLIB 393 select HAVE_PCI 394 select IXP4XX_IRQ 395 select IXP4XX_TIMER 396 select NEED_MACH_IO_H 397 select USB_EHCI_BIG_ENDIAN_DESC 398 select USB_EHCI_BIG_ENDIAN_MMIO 399 help 400 Support for Intel's IXP4XX (XScale) family of processors. 401 402config ARCH_DOVE 403 bool "Marvell Dove" 404 select CPU_PJ4 405 select GENERIC_IRQ_MULTI_HANDLER 406 select GPIOLIB 407 select HAVE_PCI 408 select MVEBU_MBUS 409 select PINCTRL 410 select PINCTRL_DOVE 411 select PLAT_ORION_LEGACY 412 select SPARSE_IRQ 413 select PM_GENERIC_DOMAINS if PM 414 help 415 Support for the Marvell Dove SoC 88AP510 416 417config ARCH_PXA 418 bool "PXA2xx/PXA3xx-based" 419 depends on MMU 420 select ARCH_MTD_XIP 421 select ARM_CPU_SUSPEND if PM 422 select AUTO_ZRELADDR 423 select COMMON_CLK 424 select CLKSRC_PXA 425 select CLKSRC_MMIO 426 select TIMER_OF 427 select CPU_XSCALE if !CPU_XSC3 428 select GENERIC_IRQ_MULTI_HANDLER 429 select GPIO_PXA 430 select GPIOLIB 431 select HAVE_IDE 432 select IRQ_DOMAIN 433 select PLAT_PXA 434 select SPARSE_IRQ 435 help 436 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 437 438config ARCH_RPC 439 bool "RiscPC" 440 depends on MMU 441 select ARCH_ACORN 442 select ARCH_MAY_HAVE_PC_FDC 443 select ARCH_SPARSEMEM_ENABLE 444 select ARM_HAS_SG_CHAIN 445 select CPU_SA110 446 select FIQ 447 select HAVE_IDE 448 select HAVE_PATA_PLATFORM 449 select ISA_DMA_API 450 select LEGACY_TIMER_TICK 451 select NEED_MACH_IO_H 452 select NEED_MACH_MEMORY_H 453 select NO_IOPORT_MAP 454 help 455 On the Acorn Risc-PC, Linux can support the internal IDE disk and 456 CD-ROM interface, serial and parallel port, and the floppy drive. 457 458config ARCH_SA1100 459 bool "SA1100-based" 460 select ARCH_MTD_XIP 461 select ARCH_SPARSEMEM_ENABLE 462 select CLKSRC_MMIO 463 select CLKSRC_PXA 464 select TIMER_OF if OF 465 select COMMON_CLK 466 select CPU_FREQ 467 select CPU_SA1100 468 select GENERIC_IRQ_MULTI_HANDLER 469 select GPIOLIB 470 select HAVE_IDE 471 select IRQ_DOMAIN 472 select ISA 473 select NEED_MACH_MEMORY_H 474 select SPARSE_IRQ 475 help 476 Support for StrongARM 11x0 based boards. 477 478config ARCH_S3C24XX 479 bool "Samsung S3C24XX SoCs" 480 select ATAGS 481 select CLKSRC_SAMSUNG_PWM 482 select GPIO_SAMSUNG 483 select GPIOLIB 484 select GENERIC_IRQ_MULTI_HANDLER 485 select HAVE_S3C2410_I2C if I2C 486 select HAVE_S3C_RTC if RTC_CLASS 487 select NEED_MACH_IO_H 488 select S3C2410_WATCHDOG 489 select SAMSUNG_ATAGS 490 select USE_OF 491 select WATCHDOG 492 help 493 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 494 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 495 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 496 Samsung SMDK2410 development board (and derivatives). 497 498config ARCH_OMAP1 499 bool "TI OMAP1" 500 depends on MMU 501 select ARCH_OMAP 502 select CLKDEV_LOOKUP 503 select CLKSRC_MMIO 504 select GENERIC_IRQ_CHIP 505 select GENERIC_IRQ_MULTI_HANDLER 506 select GPIOLIB 507 select HAVE_IDE 508 select HAVE_LEGACY_CLK 509 select IRQ_DOMAIN 510 select NEED_MACH_IO_H if PCCARD 511 select NEED_MACH_MEMORY_H 512 select SPARSE_IRQ 513 help 514 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 515 516endchoice 517 518menu "Multiple platform selection" 519 depends on ARCH_MULTIPLATFORM 520 521comment "CPU Core family selection" 522 523config ARCH_MULTI_V4 524 bool "ARMv4 based platforms (FA526)" 525 depends on !ARCH_MULTI_V6_V7 526 select ARCH_MULTI_V4_V5 527 select CPU_FA526 528 529config ARCH_MULTI_V4T 530 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 531 depends on !ARCH_MULTI_V6_V7 532 select ARCH_MULTI_V4_V5 533 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 534 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 535 CPU_ARM925T || CPU_ARM940T) 536 537config ARCH_MULTI_V5 538 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 539 depends on !ARCH_MULTI_V6_V7 540 select ARCH_MULTI_V4_V5 541 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 542 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 543 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 544 545config ARCH_MULTI_V4_V5 546 bool 547 548config ARCH_MULTI_V6 549 bool "ARMv6 based platforms (ARM11)" 550 select ARCH_MULTI_V6_V7 551 select CPU_V6K 552 553config ARCH_MULTI_V7 554 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 555 default y 556 select ARCH_MULTI_V6_V7 557 select CPU_V7 558 select HAVE_SMP 559 560config ARCH_MULTI_V6_V7 561 bool 562 select MIGHT_HAVE_CACHE_L2X0 563 564config ARCH_MULTI_CPU_AUTO 565 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 566 select ARCH_MULTI_V5 567 568endmenu 569 570config ARCH_VIRT 571 bool "Dummy Virtual Machine" 572 depends on ARCH_MULTI_V7 573 select ARM_AMBA 574 select ARM_GIC 575 select ARM_GIC_V2M if PCI 576 select ARM_GIC_V3 577 select ARM_GIC_V3_ITS if PCI 578 select ARM_PSCI 579 select HAVE_ARM_ARCH_TIMER 580 select ARCH_SUPPORTS_BIG_ENDIAN 581 582# 583# This is sorted alphabetically by mach-* pathname. However, plat-* 584# Kconfigs may be included either alphabetically (according to the 585# plat- suffix) or along side the corresponding mach-* source. 586# 587source "arch/arm/mach-actions/Kconfig" 588 589source "arch/arm/mach-alpine/Kconfig" 590 591source "arch/arm/mach-artpec/Kconfig" 592 593source "arch/arm/mach-asm9260/Kconfig" 594 595source "arch/arm/mach-aspeed/Kconfig" 596 597source "arch/arm/mach-at91/Kconfig" 598 599source "arch/arm/mach-axxia/Kconfig" 600 601source "arch/arm/mach-bcm/Kconfig" 602 603source "arch/arm/mach-berlin/Kconfig" 604 605source "arch/arm/mach-clps711x/Kconfig" 606 607source "arch/arm/mach-cns3xxx/Kconfig" 608 609source "arch/arm/mach-davinci/Kconfig" 610 611source "arch/arm/mach-digicolor/Kconfig" 612 613source "arch/arm/mach-dove/Kconfig" 614 615source "arch/arm/mach-ep93xx/Kconfig" 616 617source "arch/arm/mach-exynos/Kconfig" 618 619source "arch/arm/mach-footbridge/Kconfig" 620 621source "arch/arm/mach-gemini/Kconfig" 622 623source "arch/arm/mach-highbank/Kconfig" 624 625source "arch/arm/mach-hisi/Kconfig" 626 627source "arch/arm/mach-imx/Kconfig" 628 629source "arch/arm/mach-integrator/Kconfig" 630 631source "arch/arm/mach-iop32x/Kconfig" 632 633source "arch/arm/mach-ixp4xx/Kconfig" 634 635source "arch/arm/mach-keystone/Kconfig" 636 637source "arch/arm/mach-lpc32xx/Kconfig" 638 639source "arch/arm/mach-mediatek/Kconfig" 640 641source "arch/arm/mach-meson/Kconfig" 642 643source "arch/arm/mach-milbeaut/Kconfig" 644 645source "arch/arm/mach-mmp/Kconfig" 646 647source "arch/arm/mach-moxart/Kconfig" 648 649source "arch/arm/mach-mstar/Kconfig" 650 651source "arch/arm/mach-mv78xx0/Kconfig" 652 653source "arch/arm/mach-mvebu/Kconfig" 654 655source "arch/arm/mach-mxs/Kconfig" 656 657source "arch/arm/mach-nomadik/Kconfig" 658 659source "arch/arm/mach-npcm/Kconfig" 660 661source "arch/arm/mach-nspire/Kconfig" 662 663source "arch/arm/plat-omap/Kconfig" 664 665source "arch/arm/mach-omap1/Kconfig" 666 667source "arch/arm/mach-omap2/Kconfig" 668 669source "arch/arm/mach-orion5x/Kconfig" 670 671source "arch/arm/mach-oxnas/Kconfig" 672 673source "arch/arm/mach-picoxcell/Kconfig" 674 675source "arch/arm/mach-prima2/Kconfig" 676 677source "arch/arm/mach-pxa/Kconfig" 678source "arch/arm/plat-pxa/Kconfig" 679 680source "arch/arm/mach-qcom/Kconfig" 681 682source "arch/arm/mach-rda/Kconfig" 683 684source "arch/arm/mach-realtek/Kconfig" 685 686source "arch/arm/mach-realview/Kconfig" 687 688source "arch/arm/mach-rockchip/Kconfig" 689 690source "arch/arm/mach-s3c/Kconfig" 691 692source "arch/arm/mach-s5pv210/Kconfig" 693 694source "arch/arm/mach-sa1100/Kconfig" 695 696source "arch/arm/mach-shmobile/Kconfig" 697 698source "arch/arm/mach-socfpga/Kconfig" 699 700source "arch/arm/mach-spear/Kconfig" 701 702source "arch/arm/mach-sti/Kconfig" 703 704source "arch/arm/mach-stm32/Kconfig" 705 706source "arch/arm/mach-sunxi/Kconfig" 707 708source "arch/arm/mach-tango/Kconfig" 709 710source "arch/arm/mach-tegra/Kconfig" 711 712source "arch/arm/mach-u300/Kconfig" 713 714source "arch/arm/mach-uniphier/Kconfig" 715 716source "arch/arm/mach-ux500/Kconfig" 717 718source "arch/arm/mach-versatile/Kconfig" 719 720source "arch/arm/mach-vexpress/Kconfig" 721 722source "arch/arm/mach-vt8500/Kconfig" 723 724source "arch/arm/mach-zx/Kconfig" 725 726source "arch/arm/mach-zynq/Kconfig" 727 728# ARMv7-M architecture 729config ARCH_EFM32 730 bool "Energy Micro efm32" 731 depends on ARM_SINGLE_ARMV7M 732 select GPIOLIB 733 help 734 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 735 processors. 736 737config ARCH_LPC18XX 738 bool "NXP LPC18xx/LPC43xx" 739 depends on ARM_SINGLE_ARMV7M 740 select ARCH_HAS_RESET_CONTROLLER 741 select ARM_AMBA 742 select CLKSRC_LPC32XX 743 select PINCTRL 744 help 745 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 746 high performance microcontrollers. 747 748config ARCH_MPS2 749 bool "ARM MPS2 platform" 750 depends on ARM_SINGLE_ARMV7M 751 select ARM_AMBA 752 select CLKSRC_MPS2 753 help 754 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 755 with a range of available cores like Cortex-M3/M4/M7. 756 757 Please, note that depends which Application Note is used memory map 758 for the platform may vary, so adjustment of RAM base might be needed. 759 760# Definitions to make life easier 761config ARCH_ACORN 762 bool 763 764config PLAT_IOP 765 bool 766 767config PLAT_ORION 768 bool 769 select CLKSRC_MMIO 770 select COMMON_CLK 771 select GENERIC_IRQ_CHIP 772 select IRQ_DOMAIN 773 774config PLAT_ORION_LEGACY 775 bool 776 select PLAT_ORION 777 778config PLAT_PXA 779 bool 780 781config PLAT_VERSATILE 782 bool 783 784source "arch/arm/mm/Kconfig" 785 786config IWMMXT 787 bool "Enable iWMMXt support" 788 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 789 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 790 help 791 Enable support for iWMMXt context switching at run time if 792 running on a CPU that supports it. 793 794if !MMU 795source "arch/arm/Kconfig-nommu" 796endif 797 798config PJ4B_ERRATA_4742 799 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 800 depends on CPU_PJ4B && MACH_ARMADA_370 801 default y 802 help 803 When coming out of either a Wait for Interrupt (WFI) or a Wait for 804 Event (WFE) IDLE states, a specific timing sensitivity exists between 805 the retiring WFI/WFE instructions and the newly issued subsequent 806 instructions. This sensitivity can result in a CPU hang scenario. 807 Workaround: 808 The software must insert either a Data Synchronization Barrier (DSB) 809 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 810 instruction 811 812config ARM_ERRATA_326103 813 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 814 depends on CPU_V6 815 help 816 Executing a SWP instruction to read-only memory does not set bit 11 817 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 818 treat the access as a read, preventing a COW from occurring and 819 causing the faulting task to livelock. 820 821config ARM_ERRATA_411920 822 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 823 depends on CPU_V6 || CPU_V6K 824 help 825 Invalidation of the Instruction Cache operation can 826 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 827 It does not affect the MPCore. This option enables the ARM Ltd. 828 recommended workaround. 829 830config ARM_ERRATA_430973 831 bool "ARM errata: Stale prediction on replaced interworking branch" 832 depends on CPU_V7 833 help 834 This option enables the workaround for the 430973 Cortex-A8 835 r1p* erratum. If a code sequence containing an ARM/Thumb 836 interworking branch is replaced with another code sequence at the 837 same virtual address, whether due to self-modifying code or virtual 838 to physical address re-mapping, Cortex-A8 does not recover from the 839 stale interworking branch prediction. This results in Cortex-A8 840 executing the new code sequence in the incorrect ARM or Thumb state. 841 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 842 and also flushes the branch target cache at every context switch. 843 Note that setting specific bits in the ACTLR register may not be 844 available in non-secure mode. 845 846config ARM_ERRATA_458693 847 bool "ARM errata: Processor deadlock when a false hazard is created" 848 depends on CPU_V7 849 depends on !ARCH_MULTIPLATFORM 850 help 851 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 852 erratum. For very specific sequences of memory operations, it is 853 possible for a hazard condition intended for a cache line to instead 854 be incorrectly associated with a different cache line. This false 855 hazard might then cause a processor deadlock. The workaround enables 856 the L1 caching of the NEON accesses and disables the PLD instruction 857 in the ACTLR register. Note that setting specific bits in the ACTLR 858 register may not be available in non-secure mode. 859 860config ARM_ERRATA_460075 861 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 862 depends on CPU_V7 863 depends on !ARCH_MULTIPLATFORM 864 help 865 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 866 erratum. Any asynchronous access to the L2 cache may encounter a 867 situation in which recent store transactions to the L2 cache are lost 868 and overwritten with stale memory contents from external memory. The 869 workaround disables the write-allocate mode for the L2 cache via the 870 ACTLR register. Note that setting specific bits in the ACTLR register 871 may not be available in non-secure mode. 872 873config ARM_ERRATA_742230 874 bool "ARM errata: DMB operation may be faulty" 875 depends on CPU_V7 && SMP 876 depends on !ARCH_MULTIPLATFORM 877 help 878 This option enables the workaround for the 742230 Cortex-A9 879 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 880 between two write operations may not ensure the correct visibility 881 ordering of the two writes. This workaround sets a specific bit in 882 the diagnostic register of the Cortex-A9 which causes the DMB 883 instruction to behave as a DSB, ensuring the correct behaviour of 884 the two writes. 885 886config ARM_ERRATA_742231 887 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 888 depends on CPU_V7 && SMP 889 depends on !ARCH_MULTIPLATFORM 890 help 891 This option enables the workaround for the 742231 Cortex-A9 892 (r2p0..r2p2) erratum. Under certain conditions, specific to the 893 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 894 accessing some data located in the same cache line, may get corrupted 895 data due to bad handling of the address hazard when the line gets 896 replaced from one of the CPUs at the same time as another CPU is 897 accessing it. This workaround sets specific bits in the diagnostic 898 register of the Cortex-A9 which reduces the linefill issuing 899 capabilities of the processor. 900 901config ARM_ERRATA_643719 902 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 903 depends on CPU_V7 && SMP 904 default y 905 help 906 This option enables the workaround for the 643719 Cortex-A9 (prior to 907 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 908 register returns zero when it should return one. The workaround 909 corrects this value, ensuring cache maintenance operations which use 910 it behave as intended and avoiding data corruption. 911 912config ARM_ERRATA_720789 913 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 914 depends on CPU_V7 915 help 916 This option enables the workaround for the 720789 Cortex-A9 (prior to 917 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 918 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 919 As a consequence of this erratum, some TLB entries which should be 920 invalidated are not, resulting in an incoherency in the system page 921 tables. The workaround changes the TLB flushing routines to invalidate 922 entries regardless of the ASID. 923 924config ARM_ERRATA_743622 925 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 926 depends on CPU_V7 927 depends on !ARCH_MULTIPLATFORM 928 help 929 This option enables the workaround for the 743622 Cortex-A9 930 (r2p*) erratum. Under very rare conditions, a faulty 931 optimisation in the Cortex-A9 Store Buffer may lead to data 932 corruption. This workaround sets a specific bit in the diagnostic 933 register of the Cortex-A9 which disables the Store Buffer 934 optimisation, preventing the defect from occurring. This has no 935 visible impact on the overall performance or power consumption of the 936 processor. 937 938config ARM_ERRATA_751472 939 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 940 depends on CPU_V7 941 depends on !ARCH_MULTIPLATFORM 942 help 943 This option enables the workaround for the 751472 Cortex-A9 (prior 944 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 945 completion of a following broadcasted operation if the second 946 operation is received by a CPU before the ICIALLUIS has completed, 947 potentially leading to corrupted entries in the cache or TLB. 948 949config ARM_ERRATA_754322 950 bool "ARM errata: possible faulty MMU translations following an ASID switch" 951 depends on CPU_V7 952 help 953 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 954 r3p*) erratum. A speculative memory access may cause a page table walk 955 which starts prior to an ASID switch but completes afterwards. This 956 can populate the micro-TLB with a stale entry which may be hit with 957 the new ASID. This workaround places two dsb instructions in the mm 958 switching code so that no page table walks can cross the ASID switch. 959 960config ARM_ERRATA_754327 961 bool "ARM errata: no automatic Store Buffer drain" 962 depends on CPU_V7 && SMP 963 help 964 This option enables the workaround for the 754327 Cortex-A9 (prior to 965 r2p0) erratum. The Store Buffer does not have any automatic draining 966 mechanism and therefore a livelock may occur if an external agent 967 continuously polls a memory location waiting to observe an update. 968 This workaround defines cpu_relax() as smp_mb(), preventing correctly 969 written polling loops from denying visibility of updates to memory. 970 971config ARM_ERRATA_364296 972 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 973 depends on CPU_V6 974 help 975 This options enables the workaround for the 364296 ARM1136 976 r0p2 erratum (possible cache data corruption with 977 hit-under-miss enabled). It sets the undocumented bit 31 in 978 the auxiliary control register and the FI bit in the control 979 register, thus disabling hit-under-miss without putting the 980 processor into full low interrupt latency mode. ARM11MPCore 981 is not affected. 982 983config ARM_ERRATA_764369 984 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 985 depends on CPU_V7 && SMP 986 help 987 This option enables the workaround for erratum 764369 988 affecting Cortex-A9 MPCore with two or more processors (all 989 current revisions). Under certain timing circumstances, a data 990 cache line maintenance operation by MVA targeting an Inner 991 Shareable memory region may fail to proceed up to either the 992 Point of Coherency or to the Point of Unification of the 993 system. This workaround adds a DSB instruction before the 994 relevant cache maintenance functions and sets a specific bit 995 in the diagnostic control register of the SCU. 996 997config ARM_ERRATA_775420 998 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 999 depends on CPU_V7 1000 help 1001 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1002 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1003 operation aborts with MMU exception, it might cause the processor 1004 to deadlock. This workaround puts DSB before executing ISB if 1005 an abort may occur on cache maintenance. 1006 1007config ARM_ERRATA_798181 1008 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1009 depends on CPU_V7 && SMP 1010 help 1011 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1012 adequately shooting down all use of the old entries. This 1013 option enables the Linux kernel workaround for this erratum 1014 which sends an IPI to the CPUs that are running the same ASID 1015 as the one being invalidated. 1016 1017config ARM_ERRATA_773022 1018 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1019 depends on CPU_V7 1020 help 1021 This option enables the workaround for the 773022 Cortex-A15 1022 (up to r0p4) erratum. In certain rare sequences of code, the 1023 loop buffer may deliver incorrect instructions. This 1024 workaround disables the loop buffer to avoid the erratum. 1025 1026config ARM_ERRATA_818325_852422 1027 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1028 depends on CPU_V7 1029 help 1030 This option enables the workaround for: 1031 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1032 instruction might deadlock. Fixed in r0p1. 1033 - Cortex-A12 852422: Execution of a sequence of instructions might 1034 lead to either a data corruption or a CPU deadlock. Not fixed in 1035 any Cortex-A12 cores yet. 1036 This workaround for all both errata involves setting bit[12] of the 1037 Feature Register. This bit disables an optimisation applied to a 1038 sequence of 2 instructions that use opposing condition codes. 1039 1040config ARM_ERRATA_821420 1041 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1042 depends on CPU_V7 1043 help 1044 This option enables the workaround for the 821420 Cortex-A12 1045 (all revs) erratum. In very rare timing conditions, a sequence 1046 of VMOV to Core registers instructions, for which the second 1047 one is in the shadow of a branch or abort, can lead to a 1048 deadlock when the VMOV instructions are issued out-of-order. 1049 1050config ARM_ERRATA_825619 1051 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1052 depends on CPU_V7 1053 help 1054 This option enables the workaround for the 825619 Cortex-A12 1055 (all revs) erratum. Within rare timing constraints, executing a 1056 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1057 and Device/Strongly-Ordered loads and stores might cause deadlock 1058 1059config ARM_ERRATA_857271 1060 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1061 depends on CPU_V7 1062 help 1063 This option enables the workaround for the 857271 Cortex-A12 1064 (all revs) erratum. Under very rare timing conditions, the CPU might 1065 hang. The workaround is expected to have a < 1% performance impact. 1066 1067config ARM_ERRATA_852421 1068 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1069 depends on CPU_V7 1070 help 1071 This option enables the workaround for the 852421 Cortex-A17 1072 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1073 execution of a DMB ST instruction might fail to properly order 1074 stores from GroupA and stores from GroupB. 1075 1076config ARM_ERRATA_852423 1077 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1078 depends on CPU_V7 1079 help 1080 This option enables the workaround for: 1081 - Cortex-A17 852423: Execution of a sequence of instructions might 1082 lead to either a data corruption or a CPU deadlock. Not fixed in 1083 any Cortex-A17 cores yet. 1084 This is identical to Cortex-A12 erratum 852422. It is a separate 1085 config option from the A12 erratum due to the way errata are checked 1086 for and handled. 1087 1088config ARM_ERRATA_857272 1089 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1090 depends on CPU_V7 1091 help 1092 This option enables the workaround for the 857272 Cortex-A17 erratum. 1093 This erratum is not known to be fixed in any A17 revision. 1094 This is identical to Cortex-A12 erratum 857271. It is a separate 1095 config option from the A12 erratum due to the way errata are checked 1096 for and handled. 1097 1098endmenu 1099 1100source "arch/arm/common/Kconfig" 1101 1102menu "Bus support" 1103 1104config ISA 1105 bool 1106 help 1107 Find out whether you have ISA slots on your motherboard. ISA is the 1108 name of a bus system, i.e. the way the CPU talks to the other stuff 1109 inside your box. Other bus systems are PCI, EISA, MicroChannel 1110 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1111 newer boards don't support it. If you have ISA, say Y, otherwise N. 1112 1113# Select ISA DMA controller support 1114config ISA_DMA 1115 bool 1116 select ISA_DMA_API 1117 1118# Select ISA DMA interface 1119config ISA_DMA_API 1120 bool 1121 1122config PCI_NANOENGINE 1123 bool "BSE nanoEngine PCI support" 1124 depends on SA1100_NANOENGINE 1125 help 1126 Enable PCI on the BSE nanoEngine board. 1127 1128config ARM_ERRATA_814220 1129 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1130 depends on CPU_V7 1131 help 1132 The v7 ARM states that all cache and branch predictor maintenance 1133 operations that do not specify an address execute, relative to 1134 each other, in program order. 1135 However, because of this erratum, an L2 set/way cache maintenance 1136 operation can overtake an L1 set/way cache maintenance operation. 1137 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1138 r0p4, r0p5. 1139 1140endmenu 1141 1142menu "Kernel Features" 1143 1144config HAVE_SMP 1145 bool 1146 help 1147 This option should be selected by machines which have an SMP- 1148 capable CPU. 1149 1150 The only effect of this option is to make the SMP-related 1151 options available to the user for configuration. 1152 1153config SMP 1154 bool "Symmetric Multi-Processing" 1155 depends on CPU_V6K || CPU_V7 1156 depends on HAVE_SMP 1157 depends on MMU || ARM_MPU 1158 select IRQ_WORK 1159 help 1160 This enables support for systems with more than one CPU. If you have 1161 a system with only one CPU, say N. If you have a system with more 1162 than one CPU, say Y. 1163 1164 If you say N here, the kernel will run on uni- and multiprocessor 1165 machines, but will use only one CPU of a multiprocessor machine. If 1166 you say Y here, the kernel will run on many, but not all, 1167 uniprocessor machines. On a uniprocessor machine, the kernel 1168 will run faster if you say N here. 1169 1170 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1171 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1172 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1173 1174 If you don't know what to do here, say N. 1175 1176config SMP_ON_UP 1177 bool "Allow booting SMP kernel on uniprocessor systems" 1178 depends on SMP && !XIP_KERNEL && MMU 1179 default y 1180 help 1181 SMP kernels contain instructions which fail on non-SMP processors. 1182 Enabling this option allows the kernel to modify itself to make 1183 these instructions safe. Disabling it allows about 1K of space 1184 savings. 1185 1186 If you don't know what to do here, say Y. 1187 1188config ARM_CPU_TOPOLOGY 1189 bool "Support cpu topology definition" 1190 depends on SMP && CPU_V7 1191 default y 1192 help 1193 Support ARM cpu topology definition. The MPIDR register defines 1194 affinity between processors which is then used to describe the cpu 1195 topology of an ARM System. 1196 1197config SCHED_MC 1198 bool "Multi-core scheduler support" 1199 depends on ARM_CPU_TOPOLOGY 1200 help 1201 Multi-core scheduler support improves the CPU scheduler's decision 1202 making when dealing with multi-core CPU chips at a cost of slightly 1203 increased overhead in some places. If unsure say N here. 1204 1205config SCHED_SMT 1206 bool "SMT scheduler support" 1207 depends on ARM_CPU_TOPOLOGY 1208 help 1209 Improves the CPU scheduler's decision making when dealing with 1210 MultiThreading at a cost of slightly increased overhead in some 1211 places. If unsure say N here. 1212 1213config HAVE_ARM_SCU 1214 bool 1215 help 1216 This option enables support for the ARM snoop control unit 1217 1218config HAVE_ARM_ARCH_TIMER 1219 bool "Architected timer support" 1220 depends on CPU_V7 1221 select ARM_ARCH_TIMER 1222 help 1223 This option enables support for the ARM architected timer 1224 1225config HAVE_ARM_TWD 1226 bool 1227 help 1228 This options enables support for the ARM timer and watchdog unit 1229 1230config MCPM 1231 bool "Multi-Cluster Power Management" 1232 depends on CPU_V7 && SMP 1233 help 1234 This option provides the common power management infrastructure 1235 for (multi-)cluster based systems, such as big.LITTLE based 1236 systems. 1237 1238config MCPM_QUAD_CLUSTER 1239 bool 1240 depends on MCPM 1241 help 1242 To avoid wasting resources unnecessarily, MCPM only supports up 1243 to 2 clusters by default. 1244 Platforms with 3 or 4 clusters that use MCPM must select this 1245 option to allow the additional clusters to be managed. 1246 1247config BIG_LITTLE 1248 bool "big.LITTLE support (Experimental)" 1249 depends on CPU_V7 && SMP 1250 select MCPM 1251 help 1252 This option enables support selections for the big.LITTLE 1253 system architecture. 1254 1255config BL_SWITCHER 1256 bool "big.LITTLE switcher support" 1257 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1258 select CPU_PM 1259 help 1260 The big.LITTLE "switcher" provides the core functionality to 1261 transparently handle transition between a cluster of A15's 1262 and a cluster of A7's in a big.LITTLE system. 1263 1264config BL_SWITCHER_DUMMY_IF 1265 tristate "Simple big.LITTLE switcher user interface" 1266 depends on BL_SWITCHER && DEBUG_KERNEL 1267 help 1268 This is a simple and dummy char dev interface to control 1269 the big.LITTLE switcher core code. It is meant for 1270 debugging purposes only. 1271 1272choice 1273 prompt "Memory split" 1274 depends on MMU 1275 default VMSPLIT_3G 1276 help 1277 Select the desired split between kernel and user memory. 1278 1279 If you are not absolutely sure what you are doing, leave this 1280 option alone! 1281 1282 config VMSPLIT_3G 1283 bool "3G/1G user/kernel split" 1284 config VMSPLIT_3G_OPT 1285 depends on !ARM_LPAE 1286 bool "3G/1G user/kernel split (for full 1G low memory)" 1287 config VMSPLIT_2G 1288 bool "2G/2G user/kernel split" 1289 config VMSPLIT_1G 1290 bool "1G/3G user/kernel split" 1291endchoice 1292 1293config PAGE_OFFSET 1294 hex 1295 default PHYS_OFFSET if !MMU 1296 default 0x40000000 if VMSPLIT_1G 1297 default 0x80000000 if VMSPLIT_2G 1298 default 0xB0000000 if VMSPLIT_3G_OPT 1299 default 0xC0000000 1300 1301config NR_CPUS 1302 int "Maximum number of CPUs (2-32)" 1303 range 2 32 1304 depends on SMP 1305 default "4" 1306 1307config HOTPLUG_CPU 1308 bool "Support for hot-pluggable CPUs" 1309 depends on SMP 1310 select GENERIC_IRQ_MIGRATION 1311 help 1312 Say Y here to experiment with turning CPUs off and on. CPUs 1313 can be controlled through /sys/devices/system/cpu. 1314 1315config ARM_PSCI 1316 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1317 depends on HAVE_ARM_SMCCC 1318 select ARM_PSCI_FW 1319 help 1320 Say Y here if you want Linux to communicate with system firmware 1321 implementing the PSCI specification for CPU-centric power 1322 management operations described in ARM document number ARM DEN 1323 0022A ("Power State Coordination Interface System Software on 1324 ARM processors"). 1325 1326# The GPIO number here must be sorted by descending number. In case of 1327# a multiplatform kernel, we just want the highest value required by the 1328# selected platforms. 1329config ARCH_NR_GPIO 1330 int 1331 default 2048 if ARCH_SOCFPGA 1332 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1333 ARCH_ZYNQ || ARCH_ASPEED 1334 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1335 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1336 default 416 if ARCH_SUNXI 1337 default 392 if ARCH_U8500 1338 default 352 if ARCH_VT8500 1339 default 288 if ARCH_ROCKCHIP 1340 default 264 if MACH_H4700 1341 default 0 1342 help 1343 Maximum number of GPIOs in the system. 1344 1345 If unsure, leave the default value. 1346 1347config HZ_FIXED 1348 int 1349 default 128 if SOC_AT91RM9200 1350 default 0 1351 1352choice 1353 depends on HZ_FIXED = 0 1354 prompt "Timer frequency" 1355 1356config HZ_100 1357 bool "100 Hz" 1358 1359config HZ_200 1360 bool "200 Hz" 1361 1362config HZ_250 1363 bool "250 Hz" 1364 1365config HZ_300 1366 bool "300 Hz" 1367 1368config HZ_500 1369 bool "500 Hz" 1370 1371config HZ_1000 1372 bool "1000 Hz" 1373 1374endchoice 1375 1376config HZ 1377 int 1378 default HZ_FIXED if HZ_FIXED != 0 1379 default 100 if HZ_100 1380 default 200 if HZ_200 1381 default 250 if HZ_250 1382 default 300 if HZ_300 1383 default 500 if HZ_500 1384 default 1000 1385 1386config SCHED_HRTICK 1387 def_bool HIGH_RES_TIMERS 1388 1389config THUMB2_KERNEL 1390 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1391 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1392 default y if CPU_THUMBONLY 1393 select ARM_UNWIND 1394 help 1395 By enabling this option, the kernel will be compiled in 1396 Thumb-2 mode. 1397 1398 If unsure, say N. 1399 1400config ARM_PATCH_IDIV 1401 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1402 depends on CPU_32v7 && !XIP_KERNEL 1403 default y 1404 help 1405 The ARM compiler inserts calls to __aeabi_idiv() and 1406 __aeabi_uidiv() when it needs to perform division on signed 1407 and unsigned integers. Some v7 CPUs have support for the sdiv 1408 and udiv instructions that can be used to implement those 1409 functions. 1410 1411 Enabling this option allows the kernel to modify itself to 1412 replace the first two instructions of these library functions 1413 with the sdiv or udiv plus "bx lr" instructions when the CPU 1414 it is running on supports them. Typically this will be faster 1415 and less power intensive than running the original library 1416 code to do integer division. 1417 1418config AEABI 1419 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1420 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1421 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1422 help 1423 This option allows for the kernel to be compiled using the latest 1424 ARM ABI (aka EABI). This is only useful if you are using a user 1425 space environment that is also compiled with EABI. 1426 1427 Since there are major incompatibilities between the legacy ABI and 1428 EABI, especially with regard to structure member alignment, this 1429 option also changes the kernel syscall calling convention to 1430 disambiguate both ABIs and allow for backward compatibility support 1431 (selected with CONFIG_OABI_COMPAT). 1432 1433 To use this you need GCC version 4.0.0 or later. 1434 1435config OABI_COMPAT 1436 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1437 depends on AEABI && !THUMB2_KERNEL 1438 help 1439 This option preserves the old syscall interface along with the 1440 new (ARM EABI) one. It also provides a compatibility layer to 1441 intercept syscalls that have structure arguments which layout 1442 in memory differs between the legacy ABI and the new ARM EABI 1443 (only for non "thumb" binaries). This option adds a tiny 1444 overhead to all syscalls and produces a slightly larger kernel. 1445 1446 The seccomp filter system will not be available when this is 1447 selected, since there is no way yet to sensibly distinguish 1448 between calling conventions during filtering. 1449 1450 If you know you'll be using only pure EABI user space then you 1451 can say N here. If this option is not selected and you attempt 1452 to execute a legacy ABI binary then the result will be 1453 UNPREDICTABLE (in fact it can be predicted that it won't work 1454 at all). If in doubt say N. 1455 1456config ARCH_SELECT_MEMORY_MODEL 1457 bool 1458 1459config ARCH_FLATMEM_ENABLE 1460 bool 1461 1462config ARCH_SPARSEMEM_ENABLE 1463 bool 1464 select SPARSEMEM_STATIC if SPARSEMEM 1465 1466config HIGHMEM 1467 bool "High Memory Support" 1468 depends on MMU 1469 select KMAP_LOCAL 1470 help 1471 The address space of ARM processors is only 4 Gigabytes large 1472 and it has to accommodate user address space, kernel address 1473 space as well as some memory mapped IO. That means that, if you 1474 have a large amount of physical memory and/or IO, not all of the 1475 memory can be "permanently mapped" by the kernel. The physical 1476 memory that is not permanently mapped is called "high memory". 1477 1478 Depending on the selected kernel/user memory split, minimum 1479 vmalloc space and actual amount of RAM, you may not need this 1480 option which should result in a slightly faster kernel. 1481 1482 If unsure, say n. 1483 1484config HIGHPTE 1485 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1486 depends on HIGHMEM 1487 default y 1488 help 1489 The VM uses one page of physical memory for each page table. 1490 For systems with a lot of processes, this can use a lot of 1491 precious low memory, eventually leading to low memory being 1492 consumed by page tables. Setting this option will allow 1493 user-space 2nd level page tables to reside in high memory. 1494 1495config CPU_SW_DOMAIN_PAN 1496 bool "Enable use of CPU domains to implement privileged no-access" 1497 depends on MMU && !ARM_LPAE 1498 default y 1499 help 1500 Increase kernel security by ensuring that normal kernel accesses 1501 are unable to access userspace addresses. This can help prevent 1502 use-after-free bugs becoming an exploitable privilege escalation 1503 by ensuring that magic values (such as LIST_POISON) will always 1504 fault when dereferenced. 1505 1506 CPUs with low-vector mappings use a best-efforts implementation. 1507 Their lower 1MB needs to remain accessible for the vectors, but 1508 the remainder of userspace will become appropriately inaccessible. 1509 1510config HW_PERF_EVENTS 1511 def_bool y 1512 depends on ARM_PMU 1513 1514config SYS_SUPPORTS_HUGETLBFS 1515 def_bool y 1516 depends on ARM_LPAE 1517 1518config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1519 def_bool y 1520 depends on ARM_LPAE 1521 1522config ARCH_WANT_GENERAL_HUGETLB 1523 def_bool y 1524 1525config ARM_MODULE_PLTS 1526 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1527 depends on MODULES 1528 default y 1529 help 1530 Allocate PLTs when loading modules so that jumps and calls whose 1531 targets are too far away for their relative offsets to be encoded 1532 in the instructions themselves can be bounced via veneers in the 1533 module's PLT. This allows modules to be allocated in the generic 1534 vmalloc area after the dedicated module memory area has been 1535 exhausted. The modules will use slightly more memory, but after 1536 rounding up to page size, the actual memory footprint is usually 1537 the same. 1538 1539 Disabling this is usually safe for small single-platform 1540 configurations. If unsure, say y. 1541 1542config FORCE_MAX_ZONEORDER 1543 int "Maximum zone order" 1544 default "12" if SOC_AM33XX 1545 default "9" if SA1111 || ARCH_EFM32 1546 default "11" 1547 help 1548 The kernel memory allocator divides physically contiguous memory 1549 blocks into "zones", where each zone is a power of two number of 1550 pages. This option selects the largest power of two that the kernel 1551 keeps in the memory allocator. If you need to allocate very large 1552 blocks of physically contiguous memory, then you may need to 1553 increase this value. 1554 1555 This config option is actually maximum order plus one. For example, 1556 a value of 11 means that the largest free memory block is 2^10 pages. 1557 1558config ALIGNMENT_TRAP 1559 def_bool CPU_CP15_MMU 1560 select HAVE_PROC_CPU if PROC_FS 1561 help 1562 ARM processors cannot fetch/store information which is not 1563 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1564 address divisible by 4. On 32-bit ARM processors, these non-aligned 1565 fetch/store instructions will be emulated in software if you say 1566 here, which has a severe performance impact. This is necessary for 1567 correct operation of some network protocols. With an IP-only 1568 configuration it is safe to say N, otherwise say Y. 1569 1570config UACCESS_WITH_MEMCPY 1571 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1572 depends on MMU 1573 default y if CPU_FEROCEON 1574 help 1575 Implement faster copy_to_user and clear_user methods for CPU 1576 cores where a 8-word STM instruction give significantly higher 1577 memory write throughput than a sequence of individual 32bit stores. 1578 1579 A possible side effect is a slight increase in scheduling latency 1580 between threads sharing the same address space if they invoke 1581 such copy operations with large buffers. 1582 1583 However, if the CPU data cache is using a write-allocate mode, 1584 this option is unlikely to provide any performance gain. 1585 1586config PARAVIRT 1587 bool "Enable paravirtualization code" 1588 help 1589 This changes the kernel so it can modify itself when it is run 1590 under a hypervisor, potentially improving performance significantly 1591 over full virtualization. 1592 1593config PARAVIRT_TIME_ACCOUNTING 1594 bool "Paravirtual steal time accounting" 1595 select PARAVIRT 1596 help 1597 Select this option to enable fine granularity task steal time 1598 accounting. Time spent executing other tasks in parallel with 1599 the current vCPU is discounted from the vCPU power. To account for 1600 that, there can be a small performance impact. 1601 1602 If in doubt, say N here. 1603 1604config XEN_DOM0 1605 def_bool y 1606 depends on XEN 1607 1608config XEN 1609 bool "Xen guest support on ARM" 1610 depends on ARM && AEABI && OF 1611 depends on CPU_V7 && !CPU_V6 1612 depends on !GENERIC_ATOMIC64 1613 depends on MMU 1614 select ARCH_DMA_ADDR_T_64BIT 1615 select ARM_PSCI 1616 select SWIOTLB 1617 select SWIOTLB_XEN 1618 select PARAVIRT 1619 help 1620 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1621 1622config STACKPROTECTOR_PER_TASK 1623 bool "Use a unique stack canary value for each task" 1624 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1625 select GCC_PLUGIN_ARM_SSP_PER_TASK 1626 default y 1627 help 1628 Due to the fact that GCC uses an ordinary symbol reference from 1629 which to load the value of the stack canary, this value can only 1630 change at reboot time on SMP systems, and all tasks running in the 1631 kernel's address space are forced to use the same canary value for 1632 the entire duration that the system is up. 1633 1634 Enable this option to switch to a different method that uses a 1635 different canary value for each task. 1636 1637endmenu 1638 1639menu "Boot options" 1640 1641config USE_OF 1642 bool "Flattened Device Tree support" 1643 select IRQ_DOMAIN 1644 select OF 1645 help 1646 Include support for flattened device tree machine descriptions. 1647 1648config ATAGS 1649 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1650 default y 1651 help 1652 This is the traditional way of passing data to the kernel at boot 1653 time. If you are solely relying on the flattened device tree (or 1654 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1655 to remove ATAGS support from your kernel binary. If unsure, 1656 leave this to y. 1657 1658config DEPRECATED_PARAM_STRUCT 1659 bool "Provide old way to pass kernel parameters" 1660 depends on ATAGS 1661 help 1662 This was deprecated in 2001 and announced to live on for 5 years. 1663 Some old boot loaders still use this way. 1664 1665# Compressed boot loader in ROM. Yes, we really want to ask about 1666# TEXT and BSS so we preserve their values in the config files. 1667config ZBOOT_ROM_TEXT 1668 hex "Compressed ROM boot loader base address" 1669 default 0x0 1670 help 1671 The physical address at which the ROM-able zImage is to be 1672 placed in the target. Platforms which normally make use of 1673 ROM-able zImage formats normally set this to a suitable 1674 value in their defconfig file. 1675 1676 If ZBOOT_ROM is not enabled, this has no effect. 1677 1678config ZBOOT_ROM_BSS 1679 hex "Compressed ROM boot loader BSS address" 1680 default 0x0 1681 help 1682 The base address of an area of read/write memory in the target 1683 for the ROM-able zImage which must be available while the 1684 decompressor is running. It must be large enough to hold the 1685 entire decompressed kernel plus an additional 128 KiB. 1686 Platforms which normally make use of ROM-able zImage formats 1687 normally set this to a suitable value in their defconfig file. 1688 1689 If ZBOOT_ROM is not enabled, this has no effect. 1690 1691config ZBOOT_ROM 1692 bool "Compressed boot loader in ROM/flash" 1693 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1694 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1695 help 1696 Say Y here if you intend to execute your compressed kernel image 1697 (zImage) directly from ROM or flash. If unsure, say N. 1698 1699config ARM_APPENDED_DTB 1700 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1701 depends on OF 1702 help 1703 With this option, the boot code will look for a device tree binary 1704 (DTB) appended to zImage 1705 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1706 1707 This is meant as a backward compatibility convenience for those 1708 systems with a bootloader that can't be upgraded to accommodate 1709 the documented boot protocol using a device tree. 1710 1711 Beware that there is very little in terms of protection against 1712 this option being confused by leftover garbage in memory that might 1713 look like a DTB header after a reboot if no actual DTB is appended 1714 to zImage. Do not leave this option active in a production kernel 1715 if you don't intend to always append a DTB. Proper passing of the 1716 location into r2 of a bootloader provided DTB is always preferable 1717 to this option. 1718 1719config ARM_ATAG_DTB_COMPAT 1720 bool "Supplement the appended DTB with traditional ATAG information" 1721 depends on ARM_APPENDED_DTB 1722 help 1723 Some old bootloaders can't be updated to a DTB capable one, yet 1724 they provide ATAGs with memory configuration, the ramdisk address, 1725 the kernel cmdline string, etc. Such information is dynamically 1726 provided by the bootloader and can't always be stored in a static 1727 DTB. To allow a device tree enabled kernel to be used with such 1728 bootloaders, this option allows zImage to extract the information 1729 from the ATAG list and store it at run time into the appended DTB. 1730 1731choice 1732 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1733 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1734 1735config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1736 bool "Use bootloader kernel arguments if available" 1737 help 1738 Uses the command-line options passed by the boot loader instead of 1739 the device tree bootargs property. If the boot loader doesn't provide 1740 any, the device tree bootargs property will be used. 1741 1742config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1743 bool "Extend with bootloader kernel arguments" 1744 help 1745 The command-line arguments provided by the boot loader will be 1746 appended to the the device tree bootargs property. 1747 1748endchoice 1749 1750config CMDLINE 1751 string "Default kernel command string" 1752 default "" 1753 help 1754 On some architectures (e.g. CATS), there is currently no way 1755 for the boot loader to pass arguments to the kernel. For these 1756 architectures, you should supply some command-line options at build 1757 time by entering them here. As a minimum, you should specify the 1758 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1759 1760choice 1761 prompt "Kernel command line type" if CMDLINE != "" 1762 default CMDLINE_FROM_BOOTLOADER 1763 depends on ATAGS 1764 1765config CMDLINE_FROM_BOOTLOADER 1766 bool "Use bootloader kernel arguments if available" 1767 help 1768 Uses the command-line options passed by the boot loader. If 1769 the boot loader doesn't provide any, the default kernel command 1770 string provided in CMDLINE will be used. 1771 1772config CMDLINE_EXTEND 1773 bool "Extend bootloader kernel arguments" 1774 help 1775 The command-line arguments provided by the boot loader will be 1776 appended to the default kernel command string. 1777 1778config CMDLINE_FORCE 1779 bool "Always use the default kernel command string" 1780 help 1781 Always use the default kernel command string, even if the boot 1782 loader passes other arguments to the kernel. 1783 This is useful if you cannot or don't want to change the 1784 command-line options your boot loader passes to the kernel. 1785endchoice 1786 1787config XIP_KERNEL 1788 bool "Kernel Execute-In-Place from ROM" 1789 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1790 help 1791 Execute-In-Place allows the kernel to run from non-volatile storage 1792 directly addressable by the CPU, such as NOR flash. This saves RAM 1793 space since the text section of the kernel is not loaded from flash 1794 to RAM. Read-write sections, such as the data section and stack, 1795 are still copied to RAM. The XIP kernel is not compressed since 1796 it has to run directly from flash, so it will take more space to 1797 store it. The flash address used to link the kernel object files, 1798 and for storing it, is configuration dependent. Therefore, if you 1799 say Y here, you must know the proper physical address where to 1800 store the kernel image depending on your own flash memory usage. 1801 1802 Also note that the make target becomes "make xipImage" rather than 1803 "make zImage" or "make Image". The final kernel binary to put in 1804 ROM memory will be arch/arm/boot/xipImage. 1805 1806 If unsure, say N. 1807 1808config XIP_PHYS_ADDR 1809 hex "XIP Kernel Physical Location" 1810 depends on XIP_KERNEL 1811 default "0x00080000" 1812 help 1813 This is the physical address in your flash memory the kernel will 1814 be linked for and stored to. This address is dependent on your 1815 own flash usage. 1816 1817config XIP_DEFLATED_DATA 1818 bool "Store kernel .data section compressed in ROM" 1819 depends on XIP_KERNEL 1820 select ZLIB_INFLATE 1821 help 1822 Before the kernel is actually executed, its .data section has to be 1823 copied to RAM from ROM. This option allows for storing that data 1824 in compressed form and decompressed to RAM rather than merely being 1825 copied, saving some precious ROM space. A possible drawback is a 1826 slightly longer boot delay. 1827 1828config KEXEC 1829 bool "Kexec system call (EXPERIMENTAL)" 1830 depends on (!SMP || PM_SLEEP_SMP) 1831 depends on MMU 1832 select KEXEC_CORE 1833 help 1834 kexec is a system call that implements the ability to shutdown your 1835 current kernel, and to start another kernel. It is like a reboot 1836 but it is independent of the system firmware. And like a reboot 1837 you can start any kernel with it, not just Linux. 1838 1839 It is an ongoing process to be certain the hardware in a machine 1840 is properly shutdown, so do not be surprised if this code does not 1841 initially work for you. 1842 1843config ATAGS_PROC 1844 bool "Export atags in procfs" 1845 depends on ATAGS && KEXEC 1846 default y 1847 help 1848 Should the atags used to boot the kernel be exported in an "atags" 1849 file in procfs. Useful with kexec. 1850 1851config CRASH_DUMP 1852 bool "Build kdump crash kernel (EXPERIMENTAL)" 1853 help 1854 Generate crash dump after being started by kexec. This should 1855 be normally only set in special crash dump kernels which are 1856 loaded in the main kernel with kexec-tools into a specially 1857 reserved region and then later executed after a crash by 1858 kdump/kexec. The crash dump kernel must be compiled to a 1859 memory address not used by the main kernel 1860 1861 For more details see Documentation/admin-guide/kdump/kdump.rst 1862 1863config AUTO_ZRELADDR 1864 bool "Auto calculation of the decompressed kernel image address" 1865 help 1866 ZRELADDR is the physical address where the decompressed kernel 1867 image will be placed. If AUTO_ZRELADDR is selected, the address 1868 will be determined at run-time by masking the current IP with 1869 0xf8000000. This assumes the zImage being placed in the first 128MB 1870 from start of memory. 1871 1872config EFI_STUB 1873 bool 1874 1875config EFI 1876 bool "UEFI runtime support" 1877 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1878 select UCS2_STRING 1879 select EFI_PARAMS_FROM_FDT 1880 select EFI_STUB 1881 select EFI_GENERIC_STUB 1882 select EFI_RUNTIME_WRAPPERS 1883 help 1884 This option provides support for runtime services provided 1885 by UEFI firmware (such as non-volatile variables, realtime 1886 clock, and platform reset). A UEFI stub is also provided to 1887 allow the kernel to be booted as an EFI application. This 1888 is only useful for kernels that may run on systems that have 1889 UEFI firmware. 1890 1891config DMI 1892 bool "Enable support for SMBIOS (DMI) tables" 1893 depends on EFI 1894 default y 1895 help 1896 This enables SMBIOS/DMI feature for systems. 1897 1898 This option is only useful on systems that have UEFI firmware. 1899 However, even with this option, the resultant kernel should 1900 continue to boot on existing non-UEFI platforms. 1901 1902 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1903 i.e., the the practice of identifying the platform via DMI to 1904 decide whether certain workarounds for buggy hardware and/or 1905 firmware need to be enabled. This would require the DMI subsystem 1906 to be enabled much earlier than we do on ARM, which is non-trivial. 1907 1908endmenu 1909 1910menu "CPU Power Management" 1911 1912source "drivers/cpufreq/Kconfig" 1913 1914source "drivers/cpuidle/Kconfig" 1915 1916endmenu 1917 1918menu "Floating point emulation" 1919 1920comment "At least one emulation must be selected" 1921 1922config FPE_NWFPE 1923 bool "NWFPE math emulation" 1924 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1925 help 1926 Say Y to include the NWFPE floating point emulator in the kernel. 1927 This is necessary to run most binaries. Linux does not currently 1928 support floating point hardware so you need to say Y here even if 1929 your machine has an FPA or floating point co-processor podule. 1930 1931 You may say N here if you are going to load the Acorn FPEmulator 1932 early in the bootup. 1933 1934config FPE_NWFPE_XP 1935 bool "Support extended precision" 1936 depends on FPE_NWFPE 1937 help 1938 Say Y to include 80-bit support in the kernel floating-point 1939 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1940 Note that gcc does not generate 80-bit operations by default, 1941 so in most cases this option only enlarges the size of the 1942 floating point emulator without any good reason. 1943 1944 You almost surely want to say N here. 1945 1946config FPE_FASTFPE 1947 bool "FastFPE math emulation (EXPERIMENTAL)" 1948 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1949 help 1950 Say Y here to include the FAST floating point emulator in the kernel. 1951 This is an experimental much faster emulator which now also has full 1952 precision for the mantissa. It does not support any exceptions. 1953 It is very simple, and approximately 3-6 times faster than NWFPE. 1954 1955 It should be sufficient for most programs. It may be not suitable 1956 for scientific calculations, but you have to check this for yourself. 1957 If you do not feel you need a faster FP emulation you should better 1958 choose NWFPE. 1959 1960config VFP 1961 bool "VFP-format floating point maths" 1962 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1963 help 1964 Say Y to include VFP support code in the kernel. This is needed 1965 if your hardware includes a VFP unit. 1966 1967 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1968 release notes and additional status information. 1969 1970 Say N if your target does not have VFP hardware. 1971 1972config VFPv3 1973 bool 1974 depends on VFP 1975 default y if CPU_V7 1976 1977config NEON 1978 bool "Advanced SIMD (NEON) Extension support" 1979 depends on VFPv3 && CPU_V7 1980 help 1981 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1982 Extension. 1983 1984config KERNEL_MODE_NEON 1985 bool "Support for NEON in kernel mode" 1986 depends on NEON && AEABI 1987 help 1988 Say Y to include support for NEON in kernel mode. 1989 1990endmenu 1991 1992menu "Power management options" 1993 1994source "kernel/power/Kconfig" 1995 1996config ARCH_SUSPEND_POSSIBLE 1997 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1998 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1999 def_bool y 2000 2001config ARM_CPU_SUSPEND 2002 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2003 depends on ARCH_SUSPEND_POSSIBLE 2004 2005config ARCH_HIBERNATION_POSSIBLE 2006 bool 2007 depends on MMU 2008 default y if ARCH_SUSPEND_POSSIBLE 2009 2010endmenu 2011 2012source "drivers/firmware/Kconfig" 2013 2014if CRYPTO 2015source "arch/arm/crypto/Kconfig" 2016endif 2017 2018source "arch/arm/Kconfig.assembler" 2019