1config ARM 2 bool 3 default y 4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 7 select ARCH_HAVE_CUSTOM_GPIO_H 8 select ARCH_MIGHT_HAVE_PC_PARPORT 9 select ARCH_USE_BUILTIN_BSWAP 10 select ARCH_USE_CMPXCHG_LOCKREF 11 select ARCH_WANT_IPC_PARSE_VERSION 12 select BUILDTIME_EXTABLE_SORT if MMU 13 select CLONE_BACKWARDS 14 select CPU_PM if (SUSPEND || CPU_IDLE) 15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 18 select GENERIC_IDLE_POLL_SETUP 19 select GENERIC_IRQ_PROBE 20 select GENERIC_IRQ_SHOW 21 select GENERIC_PCI_IOMAP 22 select GENERIC_SCHED_CLOCK 23 select GENERIC_SMP_IDLE_THREAD 24 select GENERIC_STRNCPY_FROM_USER 25 select GENERIC_STRNLEN_USER 26 select HARDIRQS_SW_RESEND 27 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 28 select HAVE_ARCH_KGDB 29 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 30 select HAVE_ARCH_TRACEHOOK 31 select HAVE_BPF_JIT 32 select HAVE_CONTEXT_TRACKING 33 select HAVE_C_RECORDMCOUNT 34 select HAVE_CC_STACKPROTECTOR 35 select HAVE_DEBUG_KMEMLEAK 36 select HAVE_DMA_API_DEBUG 37 select HAVE_DMA_ATTRS 38 select HAVE_DMA_CONTIGUOUS if MMU 39 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 40 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 41 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 42 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 43 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 44 select HAVE_GENERIC_DMA_COHERENT 45 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 46 select HAVE_IDE if PCI || ISA || PCMCIA 47 select HAVE_IRQ_TIME_ACCOUNTING 48 select HAVE_KERNEL_GZIP 49 select HAVE_KERNEL_LZ4 50 select HAVE_KERNEL_LZMA 51 select HAVE_KERNEL_LZO 52 select HAVE_KERNEL_XZ 53 select HAVE_KPROBES if !XIP_KERNEL 54 select HAVE_KRETPROBES if (HAVE_KPROBES) 55 select HAVE_MEMBLOCK 56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND 57 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 58 select HAVE_PERF_EVENTS 59 select HAVE_PERF_REGS 60 select HAVE_PERF_USER_STACK_DUMP 61 select HAVE_REGS_AND_STACK_ACCESS_API 62 select HAVE_SYSCALL_TRACEPOINTS 63 select HAVE_UID16 64 select HAVE_VIRT_CPU_ACCOUNTING_GEN 65 select IRQ_FORCED_THREADING 66 select KTIME_SCALAR 67 select MODULES_USE_ELF_REL 68 select NO_BOOTMEM 69 select OLD_SIGACTION 70 select OLD_SIGSUSPEND3 71 select PERF_USE_VMALLOC 72 select RTC_LIB 73 select SYS_SUPPORTS_APM_EMULATION 74 # Above selects are sorted alphabetically; please add new ones 75 # according to that. Thanks. 76 help 77 The ARM series is a line of low-power-consumption RISC chip designs 78 licensed by ARM Ltd and targeted at embedded applications and 79 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 80 manufactured, but legacy ARM-based PC hardware remains popular in 81 Europe. There is an ARM Linux project with a web page at 82 <http://www.arm.linux.org.uk/>. 83 84config ARM_HAS_SG_CHAIN 85 bool 86 87config NEED_SG_DMA_LENGTH 88 bool 89 90config ARM_DMA_USE_IOMMU 91 bool 92 select ARM_HAS_SG_CHAIN 93 select NEED_SG_DMA_LENGTH 94 95if ARM_DMA_USE_IOMMU 96 97config ARM_DMA_IOMMU_ALIGNMENT 98 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 99 range 4 9 100 default 8 101 help 102 DMA mapping framework by default aligns all buffers to the smallest 103 PAGE_SIZE order which is greater than or equal to the requested buffer 104 size. This works well for buffers up to a few hundreds kilobytes, but 105 for larger buffers it just a waste of address space. Drivers which has 106 relatively small addressing window (like 64Mib) might run out of 107 virtual space with just a few allocations. 108 109 With this parameter you can specify the maximum PAGE_SIZE order for 110 DMA IOMMU buffers. Larger buffers will be aligned only to this 111 specified order. The order is expressed as a power of two multiplied 112 by the PAGE_SIZE. 113 114endif 115 116config HAVE_PWM 117 bool 118 119config MIGHT_HAVE_PCI 120 bool 121 122config SYS_SUPPORTS_APM_EMULATION 123 bool 124 125config HAVE_TCM 126 bool 127 select GENERIC_ALLOCATOR 128 129config HAVE_PROC_CPU 130 bool 131 132config NO_IOPORT 133 bool 134 135config EISA 136 bool 137 ---help--- 138 The Extended Industry Standard Architecture (EISA) bus was 139 developed as an open alternative to the IBM MicroChannel bus. 140 141 The EISA bus provided some of the features of the IBM MicroChannel 142 bus while maintaining backward compatibility with cards made for 143 the older ISA bus. The EISA bus saw limited use between 1988 and 144 1995 when it was made obsolete by the PCI bus. 145 146 Say Y here if you are building a kernel for an EISA-based machine. 147 148 Otherwise, say N. 149 150config SBUS 151 bool 152 153config STACKTRACE_SUPPORT 154 bool 155 default y 156 157config HAVE_LATENCYTOP_SUPPORT 158 bool 159 depends on !SMP 160 default y 161 162config LOCKDEP_SUPPORT 163 bool 164 default y 165 166config TRACE_IRQFLAGS_SUPPORT 167 bool 168 default y 169 170config RWSEM_GENERIC_SPINLOCK 171 bool 172 default y 173 174config RWSEM_XCHGADD_ALGORITHM 175 bool 176 177config ARCH_HAS_ILOG2_U32 178 bool 179 180config ARCH_HAS_ILOG2_U64 181 bool 182 183config ARCH_HAS_CPUFREQ 184 bool 185 help 186 Internal node to signify that the ARCH has CPUFREQ support 187 and that the relevant menu configurations are displayed for 188 it. 189 190config ARCH_HAS_BANDGAP 191 bool 192 193config GENERIC_HWEIGHT 194 bool 195 default y 196 197config GENERIC_CALIBRATE_DELAY 198 bool 199 default y 200 201config ARCH_MAY_HAVE_PC_FDC 202 bool 203 204config ZONE_DMA 205 bool 206 207config NEED_DMA_MAP_STATE 208 def_bool y 209 210config ARCH_HAS_DMA_SET_COHERENT_MASK 211 bool 212 213config GENERIC_ISA_DMA 214 bool 215 216config FIQ 217 bool 218 219config NEED_RET_TO_USER 220 bool 221 222config ARCH_MTD_XIP 223 bool 224 225config VECTORS_BASE 226 hex 227 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 228 default DRAM_BASE if REMAP_VECTORS_TO_RAM 229 default 0x00000000 230 help 231 The base address of exception vectors. This must be two pages 232 in size. 233 234config ARM_PATCH_PHYS_VIRT 235 bool "Patch physical to virtual translations at runtime" if EMBEDDED 236 default y 237 depends on !XIP_KERNEL && MMU 238 depends on !ARCH_REALVIEW || !SPARSEMEM 239 help 240 Patch phys-to-virt and virt-to-phys translation functions at 241 boot and module load time according to the position of the 242 kernel in system memory. 243 244 This can only be used with non-XIP MMU kernels where the base 245 of physical memory is at a 16MB boundary. 246 247 Only disable this option if you know that you do not require 248 this feature (eg, building a kernel for a single machine) and 249 you need to shrink the kernel to the minimal size. 250 251config NEED_MACH_GPIO_H 252 bool 253 help 254 Select this when mach/gpio.h is required to provide special 255 definitions for this platform. The need for mach/gpio.h should 256 be avoided when possible. 257 258config NEED_MACH_IO_H 259 bool 260 help 261 Select this when mach/io.h is required to provide special 262 definitions for this platform. The need for mach/io.h should 263 be avoided when possible. 264 265config NEED_MACH_MEMORY_H 266 bool 267 help 268 Select this when mach/memory.h is required to provide special 269 definitions for this platform. The need for mach/memory.h should 270 be avoided when possible. 271 272config PHYS_OFFSET 273 hex "Physical address of main memory" if MMU 274 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H 275 default DRAM_BASE if !MMU 276 help 277 Please provide the physical address corresponding to the 278 location of main memory in your system. 279 280config GENERIC_BUG 281 def_bool y 282 depends on BUG 283 284source "init/Kconfig" 285 286source "kernel/Kconfig.freezer" 287 288menu "System Type" 289 290config MMU 291 bool "MMU-based Paged Memory Management Support" 292 default y 293 help 294 Select if you want MMU-based virtualised addressing space 295 support by paged memory management. If unsure, say 'Y'. 296 297# 298# The "ARM system type" choice list is ordered alphabetically by option 299# text. Please add new entries in the option alphabetic order. 300# 301choice 302 prompt "ARM system type" 303 default ARCH_VERSATILE if !MMU 304 default ARCH_MULTIPLATFORM if MMU 305 306config ARCH_MULTIPLATFORM 307 bool "Allow multiple platforms to be selected" 308 depends on MMU 309 select ARM_PATCH_PHYS_VIRT 310 select AUTO_ZRELADDR 311 select COMMON_CLK 312 select MULTI_IRQ_HANDLER 313 select SPARSE_IRQ 314 select USE_OF 315 316config ARCH_INTEGRATOR 317 bool "ARM Ltd. Integrator family" 318 select ARCH_HAS_CPUFREQ 319 select ARM_AMBA 320 select ARM_PATCH_PHYS_VIRT 321 select AUTO_ZRELADDR 322 select COMMON_CLK 323 select COMMON_CLK_VERSATILE 324 select GENERIC_CLOCKEVENTS 325 select HAVE_TCM 326 select ICST 327 select MULTI_IRQ_HANDLER 328 select NEED_MACH_MEMORY_H 329 select PLAT_VERSATILE 330 select SPARSE_IRQ 331 select USE_OF 332 select VERSATILE_FPGA_IRQ 333 help 334 Support for ARM's Integrator platform. 335 336config ARCH_REALVIEW 337 bool "ARM Ltd. RealView family" 338 select ARCH_WANT_OPTIONAL_GPIOLIB 339 select ARM_AMBA 340 select ARM_TIMER_SP804 341 select COMMON_CLK 342 select COMMON_CLK_VERSATILE 343 select GENERIC_CLOCKEVENTS 344 select GPIO_PL061 if GPIOLIB 345 select ICST 346 select NEED_MACH_MEMORY_H 347 select PLAT_VERSATILE 348 select PLAT_VERSATILE_CLCD 349 help 350 This enables support for ARM Ltd RealView boards. 351 352config ARCH_VERSATILE 353 bool "ARM Ltd. Versatile family" 354 select ARCH_WANT_OPTIONAL_GPIOLIB 355 select ARM_AMBA 356 select ARM_TIMER_SP804 357 select ARM_VIC 358 select CLKDEV_LOOKUP 359 select GENERIC_CLOCKEVENTS 360 select HAVE_MACH_CLKDEV 361 select ICST 362 select PLAT_VERSATILE 363 select PLAT_VERSATILE_CLCD 364 select PLAT_VERSATILE_CLOCK 365 select VERSATILE_FPGA_IRQ 366 help 367 This enables support for ARM Ltd Versatile board. 368 369config ARCH_AT91 370 bool "Atmel AT91" 371 select ARCH_REQUIRE_GPIOLIB 372 select CLKDEV_LOOKUP 373 select IRQ_DOMAIN 374 select NEED_MACH_GPIO_H 375 select NEED_MACH_IO_H if PCCARD 376 select PINCTRL 377 select PINCTRL_AT91 if USE_OF 378 help 379 This enables support for systems based on Atmel 380 AT91RM9200 and AT91SAM9* processors. 381 382config ARCH_CLPS711X 383 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 384 select ARCH_REQUIRE_GPIOLIB 385 select AUTO_ZRELADDR 386 select CLKSRC_MMIO 387 select COMMON_CLK 388 select CPU_ARM720T 389 select GENERIC_CLOCKEVENTS 390 select MFD_SYSCON 391 select MULTI_IRQ_HANDLER 392 select SPARSE_IRQ 393 help 394 Support for Cirrus Logic 711x/721x/731x based boards. 395 396config ARCH_GEMINI 397 bool "Cortina Systems Gemini" 398 select ARCH_REQUIRE_GPIOLIB 399 select CLKSRC_MMIO 400 select CPU_FA526 401 select GENERIC_CLOCKEVENTS 402 help 403 Support for the Cortina Systems Gemini family SoCs 404 405config ARCH_EBSA110 406 bool "EBSA-110" 407 select ARCH_USES_GETTIMEOFFSET 408 select CPU_SA110 409 select ISA 410 select NEED_MACH_IO_H 411 select NEED_MACH_MEMORY_H 412 select NO_IOPORT 413 help 414 This is an evaluation board for the StrongARM processor available 415 from Digital. It has limited hardware on-board, including an 416 Ethernet interface, two PCMCIA sockets, two serial ports and a 417 parallel port. 418 419config ARCH_EFM32 420 bool "Energy Micro efm32" 421 depends on !MMU 422 select ARCH_REQUIRE_GPIOLIB 423 select ARM_NVIC 424 # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged, 425 # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO 426 select CLKSRC_MMIO 427 select CLKSRC_OF 428 select COMMON_CLK 429 select CPU_V7M 430 select GENERIC_CLOCKEVENTS 431 select NO_DMA 432 select NO_IOPORT 433 select SPARSE_IRQ 434 select USE_OF 435 help 436 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 437 processors. 438 439config ARCH_EP93XX 440 bool "EP93xx-based" 441 select ARCH_HAS_HOLES_MEMORYMODEL 442 select ARCH_REQUIRE_GPIOLIB 443 select ARCH_USES_GETTIMEOFFSET 444 select ARM_AMBA 445 select ARM_VIC 446 select CLKDEV_LOOKUP 447 select CPU_ARM920T 448 select NEED_MACH_MEMORY_H 449 help 450 This enables support for the Cirrus EP93xx series of CPUs. 451 452config ARCH_FOOTBRIDGE 453 bool "FootBridge" 454 select CPU_SA110 455 select FOOTBRIDGE 456 select GENERIC_CLOCKEVENTS 457 select HAVE_IDE 458 select NEED_MACH_IO_H if !MMU 459 select NEED_MACH_MEMORY_H 460 help 461 Support for systems based on the DC21285 companion chip 462 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 463 464config ARCH_NETX 465 bool "Hilscher NetX based" 466 select ARM_VIC 467 select CLKSRC_MMIO 468 select CPU_ARM926T 469 select GENERIC_CLOCKEVENTS 470 help 471 This enables support for systems based on the Hilscher NetX Soc 472 473config ARCH_IOP13XX 474 bool "IOP13xx-based" 475 depends on MMU 476 select CPU_XSC3 477 select NEED_MACH_MEMORY_H 478 select NEED_RET_TO_USER 479 select PCI 480 select PLAT_IOP 481 select VMSPLIT_1G 482 help 483 Support for Intel's IOP13XX (XScale) family of processors. 484 485config ARCH_IOP32X 486 bool "IOP32x-based" 487 depends on MMU 488 select ARCH_REQUIRE_GPIOLIB 489 select CPU_XSCALE 490 select GPIO_IOP 491 select NEED_RET_TO_USER 492 select PCI 493 select PLAT_IOP 494 help 495 Support for Intel's 80219 and IOP32X (XScale) family of 496 processors. 497 498config ARCH_IOP33X 499 bool "IOP33x-based" 500 depends on MMU 501 select ARCH_REQUIRE_GPIOLIB 502 select CPU_XSCALE 503 select GPIO_IOP 504 select NEED_RET_TO_USER 505 select PCI 506 select PLAT_IOP 507 help 508 Support for Intel's IOP33X (XScale) family of processors. 509 510config ARCH_IXP4XX 511 bool "IXP4xx-based" 512 depends on MMU 513 select ARCH_HAS_DMA_SET_COHERENT_MASK 514 select ARCH_SUPPORTS_BIG_ENDIAN 515 select ARCH_REQUIRE_GPIOLIB 516 select CLKSRC_MMIO 517 select CPU_XSCALE 518 select DMABOUNCE if PCI 519 select GENERIC_CLOCKEVENTS 520 select MIGHT_HAVE_PCI 521 select NEED_MACH_IO_H 522 select USB_EHCI_BIG_ENDIAN_DESC 523 select USB_EHCI_BIG_ENDIAN_MMIO 524 help 525 Support for Intel's IXP4XX (XScale) family of processors. 526 527config ARCH_DOVE 528 bool "Marvell Dove" 529 select ARCH_REQUIRE_GPIOLIB 530 select CPU_PJ4 531 select GENERIC_CLOCKEVENTS 532 select MIGHT_HAVE_PCI 533 select MVEBU_MBUS 534 select PINCTRL 535 select PINCTRL_DOVE 536 select PLAT_ORION_LEGACY 537 select USB_ARCH_HAS_EHCI 538 help 539 Support for the Marvell Dove SoC 88AP510 540 541config ARCH_KIRKWOOD 542 bool "Marvell Kirkwood" 543 select ARCH_HAS_CPUFREQ 544 select ARCH_REQUIRE_GPIOLIB 545 select CPU_FEROCEON 546 select GENERIC_CLOCKEVENTS 547 select MVEBU_MBUS 548 select PCI 549 select PCI_QUIRKS 550 select PINCTRL 551 select PINCTRL_KIRKWOOD 552 select PLAT_ORION_LEGACY 553 help 554 Support for the following Marvell Kirkwood series SoCs: 555 88F6180, 88F6192 and 88F6281. 556 557config ARCH_MV78XX0 558 bool "Marvell MV78xx0" 559 select ARCH_REQUIRE_GPIOLIB 560 select CPU_FEROCEON 561 select GENERIC_CLOCKEVENTS 562 select MVEBU_MBUS 563 select PCI 564 select PLAT_ORION_LEGACY 565 help 566 Support for the following Marvell MV78xx0 series SoCs: 567 MV781x0, MV782x0. 568 569config ARCH_ORION5X 570 bool "Marvell Orion" 571 depends on MMU 572 select ARCH_REQUIRE_GPIOLIB 573 select CPU_FEROCEON 574 select GENERIC_CLOCKEVENTS 575 select MVEBU_MBUS 576 select PCI 577 select PLAT_ORION_LEGACY 578 help 579 Support for the following Marvell Orion 5x series SoCs: 580 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 581 Orion-2 (5281), Orion-1-90 (6183). 582 583config ARCH_MMP 584 bool "Marvell PXA168/910/MMP2" 585 depends on MMU 586 select ARCH_REQUIRE_GPIOLIB 587 select CLKDEV_LOOKUP 588 select GENERIC_ALLOCATOR 589 select GENERIC_CLOCKEVENTS 590 select GPIO_PXA 591 select IRQ_DOMAIN 592 select MULTI_IRQ_HANDLER 593 select PINCTRL 594 select PLAT_PXA 595 select SPARSE_IRQ 596 help 597 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 598 599config ARCH_KS8695 600 bool "Micrel/Kendin KS8695" 601 select ARCH_REQUIRE_GPIOLIB 602 select CLKSRC_MMIO 603 select CPU_ARM922T 604 select GENERIC_CLOCKEVENTS 605 select NEED_MACH_MEMORY_H 606 help 607 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 608 System-on-Chip devices. 609 610config ARCH_W90X900 611 bool "Nuvoton W90X900 CPU" 612 select ARCH_REQUIRE_GPIOLIB 613 select CLKDEV_LOOKUP 614 select CLKSRC_MMIO 615 select CPU_ARM926T 616 select GENERIC_CLOCKEVENTS 617 help 618 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 619 At present, the w90x900 has been renamed nuc900, regarding 620 the ARM series product line, you can login the following 621 link address to know more. 622 623 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 624 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 625 626config ARCH_LPC32XX 627 bool "NXP LPC32XX" 628 select ARCH_REQUIRE_GPIOLIB 629 select ARM_AMBA 630 select CLKDEV_LOOKUP 631 select CLKSRC_MMIO 632 select CPU_ARM926T 633 select GENERIC_CLOCKEVENTS 634 select HAVE_IDE 635 select HAVE_PWM 636 select USB_ARCH_HAS_OHCI 637 select USE_OF 638 help 639 Support for the NXP LPC32XX family of processors 640 641config ARCH_PXA 642 bool "PXA2xx/PXA3xx-based" 643 depends on MMU 644 select ARCH_HAS_CPUFREQ 645 select ARCH_MTD_XIP 646 select ARCH_REQUIRE_GPIOLIB 647 select ARM_CPU_SUSPEND if PM 648 select AUTO_ZRELADDR 649 select CLKDEV_LOOKUP 650 select CLKSRC_MMIO 651 select GENERIC_CLOCKEVENTS 652 select GPIO_PXA 653 select HAVE_IDE 654 select MULTI_IRQ_HANDLER 655 select PLAT_PXA 656 select SPARSE_IRQ 657 help 658 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 659 660config ARCH_MSM_NODT 661 bool "Qualcomm MSM" 662 select ARCH_MSM 663 select ARCH_REQUIRE_GPIOLIB 664 select COMMON_CLK 665 select GENERIC_CLOCKEVENTS 666 help 667 Support for Qualcomm MSM/QSD based systems. This runs on the 668 apps processor of the MSM/QSD and depends on a shared memory 669 interface to the modem processor which runs the baseband 670 stack and controls some vital subsystems 671 (clock and power control, etc). 672 673config ARCH_SHMOBILE_LEGACY 674 bool "Renesas ARM SoCs (non-multiplatform)" 675 select ARCH_SHMOBILE 676 select ARM_PATCH_PHYS_VIRT 677 select CLKDEV_LOOKUP 678 select GENERIC_CLOCKEVENTS 679 select HAVE_ARM_SCU if SMP 680 select HAVE_ARM_TWD if SMP 681 select HAVE_MACH_CLKDEV 682 select HAVE_SMP 683 select MIGHT_HAVE_CACHE_L2X0 684 select MULTI_IRQ_HANDLER 685 select NO_IOPORT 686 select PINCTRL 687 select PM_GENERIC_DOMAINS if PM 688 select SPARSE_IRQ 689 help 690 Support for Renesas ARM SoC platforms using a non-multiplatform 691 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car 692 and RZ families. 693 694config ARCH_RPC 695 bool "RiscPC" 696 select ARCH_ACORN 697 select ARCH_MAY_HAVE_PC_FDC 698 select ARCH_SPARSEMEM_ENABLE 699 select ARCH_USES_GETTIMEOFFSET 700 select FIQ 701 select HAVE_IDE 702 select HAVE_PATA_PLATFORM 703 select ISA_DMA_API 704 select NEED_MACH_IO_H 705 select NEED_MACH_MEMORY_H 706 select NO_IOPORT 707 select VIRT_TO_BUS 708 help 709 On the Acorn Risc-PC, Linux can support the internal IDE disk and 710 CD-ROM interface, serial and parallel port, and the floppy drive. 711 712config ARCH_SA1100 713 bool "SA1100-based" 714 select ARCH_HAS_CPUFREQ 715 select ARCH_MTD_XIP 716 select ARCH_REQUIRE_GPIOLIB 717 select ARCH_SPARSEMEM_ENABLE 718 select CLKDEV_LOOKUP 719 select CLKSRC_MMIO 720 select CPU_FREQ 721 select CPU_SA1100 722 select GENERIC_CLOCKEVENTS 723 select HAVE_IDE 724 select ISA 725 select NEED_MACH_MEMORY_H 726 select SPARSE_IRQ 727 help 728 Support for StrongARM 11x0 based boards. 729 730config ARCH_S3C24XX 731 bool "Samsung S3C24XX SoCs" 732 select ARCH_HAS_CPUFREQ 733 select ARCH_REQUIRE_GPIOLIB 734 select CLKDEV_LOOKUP 735 select CLKSRC_SAMSUNG_PWM 736 select GENERIC_CLOCKEVENTS 737 select GPIO_SAMSUNG 738 select HAVE_S3C2410_I2C if I2C 739 select HAVE_S3C2410_WATCHDOG if WATCHDOG 740 select HAVE_S3C_RTC if RTC_CLASS 741 select MULTI_IRQ_HANDLER 742 select NEED_MACH_IO_H 743 select SAMSUNG_ATAGS 744 help 745 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 746 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 747 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 748 Samsung SMDK2410 development board (and derivatives). 749 750config ARCH_S3C64XX 751 bool "Samsung S3C64XX" 752 select ARCH_HAS_CPUFREQ 753 select ARCH_REQUIRE_GPIOLIB 754 select ARM_AMBA 755 select ARM_VIC 756 select CLKDEV_LOOKUP 757 select CLKSRC_SAMSUNG_PWM 758 select COMMON_CLK 759 select CPU_V6K 760 select GENERIC_CLOCKEVENTS 761 select GPIO_SAMSUNG 762 select HAVE_S3C2410_I2C if I2C 763 select HAVE_S3C2410_WATCHDOG if WATCHDOG 764 select HAVE_TCM 765 select NO_IOPORT 766 select PLAT_SAMSUNG 767 select PM_GENERIC_DOMAINS 768 select S3C_DEV_NAND 769 select S3C_GPIO_TRACK 770 select SAMSUNG_ATAGS 771 select SAMSUNG_WAKEMASK 772 select SAMSUNG_WDT_RESET 773 select USB_ARCH_HAS_OHCI 774 help 775 Samsung S3C64XX series based systems 776 777config ARCH_S5P64X0 778 bool "Samsung S5P6440 S5P6450" 779 select CLKDEV_LOOKUP 780 select CLKSRC_SAMSUNG_PWM 781 select CPU_V6 782 select GENERIC_CLOCKEVENTS 783 select GPIO_SAMSUNG 784 select HAVE_S3C2410_I2C if I2C 785 select HAVE_S3C2410_WATCHDOG if WATCHDOG 786 select HAVE_S3C_RTC if RTC_CLASS 787 select NEED_MACH_GPIO_H 788 select SAMSUNG_ATAGS 789 select SAMSUNG_WDT_RESET 790 help 791 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 792 SMDK6450. 793 794config ARCH_S5PC100 795 bool "Samsung S5PC100" 796 select ARCH_REQUIRE_GPIOLIB 797 select CLKDEV_LOOKUP 798 select CLKSRC_SAMSUNG_PWM 799 select CPU_V7 800 select GENERIC_CLOCKEVENTS 801 select GPIO_SAMSUNG 802 select HAVE_S3C2410_I2C if I2C 803 select HAVE_S3C2410_WATCHDOG if WATCHDOG 804 select HAVE_S3C_RTC if RTC_CLASS 805 select NEED_MACH_GPIO_H 806 select SAMSUNG_ATAGS 807 select SAMSUNG_WDT_RESET 808 help 809 Samsung S5PC100 series based systems 810 811config ARCH_S5PV210 812 bool "Samsung S5PV210/S5PC110" 813 select ARCH_HAS_CPUFREQ 814 select ARCH_HAS_HOLES_MEMORYMODEL 815 select ARCH_SPARSEMEM_ENABLE 816 select CLKDEV_LOOKUP 817 select CLKSRC_SAMSUNG_PWM 818 select CPU_V7 819 select GENERIC_CLOCKEVENTS 820 select GPIO_SAMSUNG 821 select HAVE_S3C2410_I2C if I2C 822 select HAVE_S3C2410_WATCHDOG if WATCHDOG 823 select HAVE_S3C_RTC if RTC_CLASS 824 select NEED_MACH_GPIO_H 825 select NEED_MACH_MEMORY_H 826 select SAMSUNG_ATAGS 827 help 828 Samsung S5PV210/S5PC110 series based systems 829 830config ARCH_EXYNOS 831 bool "Samsung EXYNOS" 832 select ARCH_HAS_CPUFREQ 833 select ARCH_HAS_HOLES_MEMORYMODEL 834 select ARCH_REQUIRE_GPIOLIB 835 select ARCH_SPARSEMEM_ENABLE 836 select ARM_GIC 837 select COMMON_CLK 838 select CPU_V7 839 select GENERIC_CLOCKEVENTS 840 select HAVE_S3C2410_I2C if I2C 841 select HAVE_S3C2410_WATCHDOG if WATCHDOG 842 select HAVE_S3C_RTC if RTC_CLASS 843 select NEED_MACH_MEMORY_H 844 select SPARSE_IRQ 845 select USE_OF 846 help 847 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 848 849config ARCH_DAVINCI 850 bool "TI DaVinci" 851 select ARCH_HAS_HOLES_MEMORYMODEL 852 select ARCH_REQUIRE_GPIOLIB 853 select CLKDEV_LOOKUP 854 select GENERIC_ALLOCATOR 855 select GENERIC_CLOCKEVENTS 856 select GENERIC_IRQ_CHIP 857 select HAVE_IDE 858 select TI_PRIV_EDMA 859 select USE_OF 860 select ZONE_DMA 861 help 862 Support for TI's DaVinci platform. 863 864config ARCH_OMAP1 865 bool "TI OMAP1" 866 depends on MMU 867 select ARCH_HAS_CPUFREQ 868 select ARCH_HAS_HOLES_MEMORYMODEL 869 select ARCH_OMAP 870 select ARCH_REQUIRE_GPIOLIB 871 select CLKDEV_LOOKUP 872 select CLKSRC_MMIO 873 select GENERIC_CLOCKEVENTS 874 select GENERIC_IRQ_CHIP 875 select HAVE_IDE 876 select IRQ_DOMAIN 877 select NEED_MACH_IO_H if PCCARD 878 select NEED_MACH_MEMORY_H 879 help 880 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 881 882endchoice 883 884menu "Multiple platform selection" 885 depends on ARCH_MULTIPLATFORM 886 887comment "CPU Core family selection" 888 889config ARCH_MULTI_V4T 890 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 891 depends on !ARCH_MULTI_V6_V7 892 select ARCH_MULTI_V4_V5 893 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 894 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 895 CPU_ARM925T || CPU_ARM940T) 896 897config ARCH_MULTI_V5 898 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 899 depends on !ARCH_MULTI_V6_V7 900 select ARCH_MULTI_V4_V5 901 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \ 902 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 903 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 904 905config ARCH_MULTI_V4_V5 906 bool 907 908config ARCH_MULTI_V6 909 bool "ARMv6 based platforms (ARM11)" 910 select ARCH_MULTI_V6_V7 911 select CPU_V6 912 913config ARCH_MULTI_V7 914 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 915 default y 916 select ARCH_MULTI_V6_V7 917 select CPU_V7 918 919config ARCH_MULTI_V6_V7 920 bool 921 922config ARCH_MULTI_CPU_AUTO 923 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 924 select ARCH_MULTI_V5 925 926endmenu 927 928# 929# This is sorted alphabetically by mach-* pathname. However, plat-* 930# Kconfigs may be included either alphabetically (according to the 931# plat- suffix) or along side the corresponding mach-* source. 932# 933source "arch/arm/mach-mvebu/Kconfig" 934 935source "arch/arm/mach-at91/Kconfig" 936 937source "arch/arm/mach-bcm/Kconfig" 938 939source "arch/arm/mach-bcm2835/Kconfig" 940 941source "arch/arm/mach-berlin/Kconfig" 942 943source "arch/arm/mach-clps711x/Kconfig" 944 945source "arch/arm/mach-cns3xxx/Kconfig" 946 947source "arch/arm/mach-davinci/Kconfig" 948 949source "arch/arm/mach-dove/Kconfig" 950 951source "arch/arm/mach-ep93xx/Kconfig" 952 953source "arch/arm/mach-footbridge/Kconfig" 954 955source "arch/arm/mach-gemini/Kconfig" 956 957source "arch/arm/mach-highbank/Kconfig" 958 959source "arch/arm/mach-hisi/Kconfig" 960 961source "arch/arm/mach-integrator/Kconfig" 962 963source "arch/arm/mach-iop32x/Kconfig" 964 965source "arch/arm/mach-iop33x/Kconfig" 966 967source "arch/arm/mach-iop13xx/Kconfig" 968 969source "arch/arm/mach-ixp4xx/Kconfig" 970 971source "arch/arm/mach-keystone/Kconfig" 972 973source "arch/arm/mach-kirkwood/Kconfig" 974 975source "arch/arm/mach-ks8695/Kconfig" 976 977source "arch/arm/mach-msm/Kconfig" 978 979source "arch/arm/mach-moxart/Kconfig" 980 981source "arch/arm/mach-mv78xx0/Kconfig" 982 983source "arch/arm/mach-imx/Kconfig" 984 985source "arch/arm/mach-mxs/Kconfig" 986 987source "arch/arm/mach-netx/Kconfig" 988 989source "arch/arm/mach-nomadik/Kconfig" 990 991source "arch/arm/mach-nspire/Kconfig" 992 993source "arch/arm/plat-omap/Kconfig" 994 995source "arch/arm/mach-omap1/Kconfig" 996 997source "arch/arm/mach-omap2/Kconfig" 998 999source "arch/arm/mach-orion5x/Kconfig" 1000 1001source "arch/arm/mach-picoxcell/Kconfig" 1002 1003source "arch/arm/mach-pxa/Kconfig" 1004source "arch/arm/plat-pxa/Kconfig" 1005 1006source "arch/arm/mach-mmp/Kconfig" 1007 1008source "arch/arm/mach-realview/Kconfig" 1009 1010source "arch/arm/mach-rockchip/Kconfig" 1011 1012source "arch/arm/mach-sa1100/Kconfig" 1013 1014source "arch/arm/plat-samsung/Kconfig" 1015 1016source "arch/arm/mach-socfpga/Kconfig" 1017 1018source "arch/arm/mach-spear/Kconfig" 1019 1020source "arch/arm/mach-sti/Kconfig" 1021 1022source "arch/arm/mach-s3c24xx/Kconfig" 1023 1024source "arch/arm/mach-s3c64xx/Kconfig" 1025 1026source "arch/arm/mach-s5p64x0/Kconfig" 1027 1028source "arch/arm/mach-s5pc100/Kconfig" 1029 1030source "arch/arm/mach-s5pv210/Kconfig" 1031 1032source "arch/arm/mach-exynos/Kconfig" 1033 1034source "arch/arm/mach-shmobile/Kconfig" 1035 1036source "arch/arm/mach-sunxi/Kconfig" 1037 1038source "arch/arm/mach-prima2/Kconfig" 1039 1040source "arch/arm/mach-tegra/Kconfig" 1041 1042source "arch/arm/mach-u300/Kconfig" 1043 1044source "arch/arm/mach-ux500/Kconfig" 1045 1046source "arch/arm/mach-versatile/Kconfig" 1047 1048source "arch/arm/mach-vexpress/Kconfig" 1049source "arch/arm/plat-versatile/Kconfig" 1050 1051source "arch/arm/mach-virt/Kconfig" 1052 1053source "arch/arm/mach-vt8500/Kconfig" 1054 1055source "arch/arm/mach-w90x900/Kconfig" 1056 1057source "arch/arm/mach-zynq/Kconfig" 1058 1059# Definitions to make life easier 1060config ARCH_ACORN 1061 bool 1062 1063config PLAT_IOP 1064 bool 1065 select GENERIC_CLOCKEVENTS 1066 1067config PLAT_ORION 1068 bool 1069 select CLKSRC_MMIO 1070 select COMMON_CLK 1071 select GENERIC_IRQ_CHIP 1072 select IRQ_DOMAIN 1073 1074config PLAT_ORION_LEGACY 1075 bool 1076 select PLAT_ORION 1077 1078config PLAT_PXA 1079 bool 1080 1081config PLAT_VERSATILE 1082 bool 1083 1084config ARM_TIMER_SP804 1085 bool 1086 select CLKSRC_MMIO 1087 select CLKSRC_OF if OF 1088 1089source "arch/arm/firmware/Kconfig" 1090 1091source arch/arm/mm/Kconfig 1092 1093config ARM_NR_BANKS 1094 int 1095 default 16 if ARCH_EP93XX 1096 default 8 1097 1098config IWMMXT 1099 bool "Enable iWMMXt support" if !CPU_PJ4 1100 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1101 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 1102 help 1103 Enable support for iWMMXt context switching at run time if 1104 running on a CPU that supports it. 1105 1106config MULTI_IRQ_HANDLER 1107 bool 1108 help 1109 Allow each machine to specify it's own IRQ handler at run time. 1110 1111if !MMU 1112source "arch/arm/Kconfig-nommu" 1113endif 1114 1115config PJ4B_ERRATA_4742 1116 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 1117 depends on CPU_PJ4B && MACH_ARMADA_370 1118 default y 1119 help 1120 When coming out of either a Wait for Interrupt (WFI) or a Wait for 1121 Event (WFE) IDLE states, a specific timing sensitivity exists between 1122 the retiring WFI/WFE instructions and the newly issued subsequent 1123 instructions. This sensitivity can result in a CPU hang scenario. 1124 Workaround: 1125 The software must insert either a Data Synchronization Barrier (DSB) 1126 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 1127 instruction 1128 1129config ARM_ERRATA_326103 1130 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 1131 depends on CPU_V6 1132 help 1133 Executing a SWP instruction to read-only memory does not set bit 11 1134 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 1135 treat the access as a read, preventing a COW from occurring and 1136 causing the faulting task to livelock. 1137 1138config ARM_ERRATA_411920 1139 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1140 depends on CPU_V6 || CPU_V6K 1141 help 1142 Invalidation of the Instruction Cache operation can 1143 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1144 It does not affect the MPCore. This option enables the ARM Ltd. 1145 recommended workaround. 1146 1147config ARM_ERRATA_430973 1148 bool "ARM errata: Stale prediction on replaced interworking branch" 1149 depends on CPU_V7 1150 help 1151 This option enables the workaround for the 430973 Cortex-A8 1152 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1153 interworking branch is replaced with another code sequence at the 1154 same virtual address, whether due to self-modifying code or virtual 1155 to physical address re-mapping, Cortex-A8 does not recover from the 1156 stale interworking branch prediction. This results in Cortex-A8 1157 executing the new code sequence in the incorrect ARM or Thumb state. 1158 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1159 and also flushes the branch target cache at every context switch. 1160 Note that setting specific bits in the ACTLR register may not be 1161 available in non-secure mode. 1162 1163config ARM_ERRATA_458693 1164 bool "ARM errata: Processor deadlock when a false hazard is created" 1165 depends on CPU_V7 1166 depends on !ARCH_MULTIPLATFORM 1167 help 1168 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1169 erratum. For very specific sequences of memory operations, it is 1170 possible for a hazard condition intended for a cache line to instead 1171 be incorrectly associated with a different cache line. This false 1172 hazard might then cause a processor deadlock. The workaround enables 1173 the L1 caching of the NEON accesses and disables the PLD instruction 1174 in the ACTLR register. Note that setting specific bits in the ACTLR 1175 register may not be available in non-secure mode. 1176 1177config ARM_ERRATA_460075 1178 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1179 depends on CPU_V7 1180 depends on !ARCH_MULTIPLATFORM 1181 help 1182 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1183 erratum. Any asynchronous access to the L2 cache may encounter a 1184 situation in which recent store transactions to the L2 cache are lost 1185 and overwritten with stale memory contents from external memory. The 1186 workaround disables the write-allocate mode for the L2 cache via the 1187 ACTLR register. Note that setting specific bits in the ACTLR register 1188 may not be available in non-secure mode. 1189 1190config ARM_ERRATA_742230 1191 bool "ARM errata: DMB operation may be faulty" 1192 depends on CPU_V7 && SMP 1193 depends on !ARCH_MULTIPLATFORM 1194 help 1195 This option enables the workaround for the 742230 Cortex-A9 1196 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1197 between two write operations may not ensure the correct visibility 1198 ordering of the two writes. This workaround sets a specific bit in 1199 the diagnostic register of the Cortex-A9 which causes the DMB 1200 instruction to behave as a DSB, ensuring the correct behaviour of 1201 the two writes. 1202 1203config ARM_ERRATA_742231 1204 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1205 depends on CPU_V7 && SMP 1206 depends on !ARCH_MULTIPLATFORM 1207 help 1208 This option enables the workaround for the 742231 Cortex-A9 1209 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1210 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1211 accessing some data located in the same cache line, may get corrupted 1212 data due to bad handling of the address hazard when the line gets 1213 replaced from one of the CPUs at the same time as another CPU is 1214 accessing it. This workaround sets specific bits in the diagnostic 1215 register of the Cortex-A9 which reduces the linefill issuing 1216 capabilities of the processor. 1217 1218config PL310_ERRATA_588369 1219 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" 1220 depends on CACHE_L2X0 1221 help 1222 The PL310 L2 cache controller implements three types of Clean & 1223 Invalidate maintenance operations: by Physical Address 1224 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1225 They are architecturally defined to behave as the execution of a 1226 clean operation followed immediately by an invalidate operation, 1227 both performing to the same memory location. This functionality 1228 is not correctly implemented in PL310 as clean lines are not 1229 invalidated as a result of these operations. 1230 1231config ARM_ERRATA_643719 1232 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1233 depends on CPU_V7 && SMP 1234 help 1235 This option enables the workaround for the 643719 Cortex-A9 (prior to 1236 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1237 register returns zero when it should return one. The workaround 1238 corrects this value, ensuring cache maintenance operations which use 1239 it behave as intended and avoiding data corruption. 1240 1241config ARM_ERRATA_720789 1242 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1243 depends on CPU_V7 1244 help 1245 This option enables the workaround for the 720789 Cortex-A9 (prior to 1246 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1247 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1248 As a consequence of this erratum, some TLB entries which should be 1249 invalidated are not, resulting in an incoherency in the system page 1250 tables. The workaround changes the TLB flushing routines to invalidate 1251 entries regardless of the ASID. 1252 1253config PL310_ERRATA_727915 1254 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" 1255 depends on CACHE_L2X0 1256 help 1257 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1258 operation (offset 0x7FC). This operation runs in background so that 1259 PL310 can handle normal accesses while it is in progress. Under very 1260 rare circumstances, due to this erratum, write data can be lost when 1261 PL310 treats a cacheable write transaction during a Clean & 1262 Invalidate by Way operation. 1263 1264config ARM_ERRATA_743622 1265 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1266 depends on CPU_V7 1267 depends on !ARCH_MULTIPLATFORM 1268 help 1269 This option enables the workaround for the 743622 Cortex-A9 1270 (r2p*) erratum. Under very rare conditions, a faulty 1271 optimisation in the Cortex-A9 Store Buffer may lead to data 1272 corruption. This workaround sets a specific bit in the diagnostic 1273 register of the Cortex-A9 which disables the Store Buffer 1274 optimisation, preventing the defect from occurring. This has no 1275 visible impact on the overall performance or power consumption of the 1276 processor. 1277 1278config ARM_ERRATA_751472 1279 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1280 depends on CPU_V7 1281 depends on !ARCH_MULTIPLATFORM 1282 help 1283 This option enables the workaround for the 751472 Cortex-A9 (prior 1284 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1285 completion of a following broadcasted operation if the second 1286 operation is received by a CPU before the ICIALLUIS has completed, 1287 potentially leading to corrupted entries in the cache or TLB. 1288 1289config PL310_ERRATA_753970 1290 bool "PL310 errata: cache sync operation may be faulty" 1291 depends on CACHE_PL310 1292 help 1293 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1294 1295 Under some condition the effect of cache sync operation on 1296 the store buffer still remains when the operation completes. 1297 This means that the store buffer is always asked to drain and 1298 this prevents it from merging any further writes. The workaround 1299 is to replace the normal offset of cache sync operation (0x730) 1300 by another offset targeting an unmapped PL310 register 0x740. 1301 This has the same effect as the cache sync operation: store buffer 1302 drain and waiting for all buffers empty. 1303 1304config ARM_ERRATA_754322 1305 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1306 depends on CPU_V7 1307 help 1308 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1309 r3p*) erratum. A speculative memory access may cause a page table walk 1310 which starts prior to an ASID switch but completes afterwards. This 1311 can populate the micro-TLB with a stale entry which may be hit with 1312 the new ASID. This workaround places two dsb instructions in the mm 1313 switching code so that no page table walks can cross the ASID switch. 1314 1315config ARM_ERRATA_754327 1316 bool "ARM errata: no automatic Store Buffer drain" 1317 depends on CPU_V7 && SMP 1318 help 1319 This option enables the workaround for the 754327 Cortex-A9 (prior to 1320 r2p0) erratum. The Store Buffer does not have any automatic draining 1321 mechanism and therefore a livelock may occur if an external agent 1322 continuously polls a memory location waiting to observe an update. 1323 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1324 written polling loops from denying visibility of updates to memory. 1325 1326config ARM_ERRATA_364296 1327 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1328 depends on CPU_V6 1329 help 1330 This options enables the workaround for the 364296 ARM1136 1331 r0p2 erratum (possible cache data corruption with 1332 hit-under-miss enabled). It sets the undocumented bit 31 in 1333 the auxiliary control register and the FI bit in the control 1334 register, thus disabling hit-under-miss without putting the 1335 processor into full low interrupt latency mode. ARM11MPCore 1336 is not affected. 1337 1338config ARM_ERRATA_764369 1339 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1340 depends on CPU_V7 && SMP 1341 help 1342 This option enables the workaround for erratum 764369 1343 affecting Cortex-A9 MPCore with two or more processors (all 1344 current revisions). Under certain timing circumstances, a data 1345 cache line maintenance operation by MVA targeting an Inner 1346 Shareable memory region may fail to proceed up to either the 1347 Point of Coherency or to the Point of Unification of the 1348 system. This workaround adds a DSB instruction before the 1349 relevant cache maintenance functions and sets a specific bit 1350 in the diagnostic control register of the SCU. 1351 1352config PL310_ERRATA_769419 1353 bool "PL310 errata: no automatic Store Buffer drain" 1354 depends on CACHE_L2X0 1355 help 1356 On revisions of the PL310 prior to r3p2, the Store Buffer does 1357 not automatically drain. This can cause normal, non-cacheable 1358 writes to be retained when the memory system is idle, leading 1359 to suboptimal I/O performance for drivers using coherent DMA. 1360 This option adds a write barrier to the cpu_idle loop so that, 1361 on systems with an outer cache, the store buffer is drained 1362 explicitly. 1363 1364config ARM_ERRATA_775420 1365 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1366 depends on CPU_V7 1367 help 1368 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1369 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1370 operation aborts with MMU exception, it might cause the processor 1371 to deadlock. This workaround puts DSB before executing ISB if 1372 an abort may occur on cache maintenance. 1373 1374config ARM_ERRATA_798181 1375 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1376 depends on CPU_V7 && SMP 1377 help 1378 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1379 adequately shooting down all use of the old entries. This 1380 option enables the Linux kernel workaround for this erratum 1381 which sends an IPI to the CPUs that are running the same ASID 1382 as the one being invalidated. 1383 1384config ARM_ERRATA_773022 1385 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1386 depends on CPU_V7 1387 help 1388 This option enables the workaround for the 773022 Cortex-A15 1389 (up to r0p4) erratum. In certain rare sequences of code, the 1390 loop buffer may deliver incorrect instructions. This 1391 workaround disables the loop buffer to avoid the erratum. 1392 1393endmenu 1394 1395source "arch/arm/common/Kconfig" 1396 1397menu "Bus support" 1398 1399config ARM_AMBA 1400 bool 1401 1402config ISA 1403 bool 1404 help 1405 Find out whether you have ISA slots on your motherboard. ISA is the 1406 name of a bus system, i.e. the way the CPU talks to the other stuff 1407 inside your box. Other bus systems are PCI, EISA, MicroChannel 1408 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1409 newer boards don't support it. If you have ISA, say Y, otherwise N. 1410 1411# Select ISA DMA controller support 1412config ISA_DMA 1413 bool 1414 select ISA_DMA_API 1415 1416# Select ISA DMA interface 1417config ISA_DMA_API 1418 bool 1419 1420config PCI 1421 bool "PCI support" if MIGHT_HAVE_PCI 1422 help 1423 Find out whether you have a PCI motherboard. PCI is the name of a 1424 bus system, i.e. the way the CPU talks to the other stuff inside 1425 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1426 VESA. If you have PCI, say Y, otherwise N. 1427 1428config PCI_DOMAINS 1429 bool 1430 depends on PCI 1431 1432config PCI_NANOENGINE 1433 bool "BSE nanoEngine PCI support" 1434 depends on SA1100_NANOENGINE 1435 help 1436 Enable PCI on the BSE nanoEngine board. 1437 1438config PCI_SYSCALL 1439 def_bool PCI 1440 1441config PCI_HOST_ITE8152 1442 bool 1443 depends on PCI && MACH_ARMCORE 1444 default y 1445 select DMABOUNCE 1446 1447source "drivers/pci/Kconfig" 1448source "drivers/pci/pcie/Kconfig" 1449 1450source "drivers/pcmcia/Kconfig" 1451 1452endmenu 1453 1454menu "Kernel Features" 1455 1456config HAVE_SMP 1457 bool 1458 help 1459 This option should be selected by machines which have an SMP- 1460 capable CPU. 1461 1462 The only effect of this option is to make the SMP-related 1463 options available to the user for configuration. 1464 1465config SMP 1466 bool "Symmetric Multi-Processing" 1467 depends on CPU_V6K || CPU_V7 1468 depends on GENERIC_CLOCKEVENTS 1469 depends on HAVE_SMP 1470 depends on MMU || ARM_MPU 1471 help 1472 This enables support for systems with more than one CPU. If you have 1473 a system with only one CPU, say N. If you have a system with more 1474 than one CPU, say Y. 1475 1476 If you say N here, the kernel will run on uni- and multiprocessor 1477 machines, but will use only one CPU of a multiprocessor machine. If 1478 you say Y here, the kernel will run on many, but not all, 1479 uniprocessor machines. On a uniprocessor machine, the kernel 1480 will run faster if you say N here. 1481 1482 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1483 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1484 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1485 1486 If you don't know what to do here, say N. 1487 1488config SMP_ON_UP 1489 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1490 depends on SMP && !XIP_KERNEL && MMU 1491 default y 1492 help 1493 SMP kernels contain instructions which fail on non-SMP processors. 1494 Enabling this option allows the kernel to modify itself to make 1495 these instructions safe. Disabling it allows about 1K of space 1496 savings. 1497 1498 If you don't know what to do here, say Y. 1499 1500config ARM_CPU_TOPOLOGY 1501 bool "Support cpu topology definition" 1502 depends on SMP && CPU_V7 1503 default y 1504 help 1505 Support ARM cpu topology definition. The MPIDR register defines 1506 affinity between processors which is then used to describe the cpu 1507 topology of an ARM System. 1508 1509config SCHED_MC 1510 bool "Multi-core scheduler support" 1511 depends on ARM_CPU_TOPOLOGY 1512 help 1513 Multi-core scheduler support improves the CPU scheduler's decision 1514 making when dealing with multi-core CPU chips at a cost of slightly 1515 increased overhead in some places. If unsure say N here. 1516 1517config SCHED_SMT 1518 bool "SMT scheduler support" 1519 depends on ARM_CPU_TOPOLOGY 1520 help 1521 Improves the CPU scheduler's decision making when dealing with 1522 MultiThreading at a cost of slightly increased overhead in some 1523 places. If unsure say N here. 1524 1525config HAVE_ARM_SCU 1526 bool 1527 help 1528 This option enables support for the ARM system coherency unit 1529 1530config HAVE_ARM_ARCH_TIMER 1531 bool "Architected timer support" 1532 depends on CPU_V7 1533 select ARM_ARCH_TIMER 1534 select GENERIC_CLOCKEVENTS 1535 help 1536 This option enables support for the ARM architected timer 1537 1538config HAVE_ARM_TWD 1539 bool 1540 depends on SMP 1541 select CLKSRC_OF if OF 1542 help 1543 This options enables support for the ARM timer and watchdog unit 1544 1545config MCPM 1546 bool "Multi-Cluster Power Management" 1547 depends on CPU_V7 && SMP 1548 help 1549 This option provides the common power management infrastructure 1550 for (multi-)cluster based systems, such as big.LITTLE based 1551 systems. 1552 1553config BIG_LITTLE 1554 bool "big.LITTLE support (Experimental)" 1555 depends on CPU_V7 && SMP 1556 select MCPM 1557 help 1558 This option enables support selections for the big.LITTLE 1559 system architecture. 1560 1561config BL_SWITCHER 1562 bool "big.LITTLE switcher support" 1563 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU 1564 select CPU_PM 1565 select ARM_CPU_SUSPEND 1566 help 1567 The big.LITTLE "switcher" provides the core functionality to 1568 transparently handle transition between a cluster of A15's 1569 and a cluster of A7's in a big.LITTLE system. 1570 1571config BL_SWITCHER_DUMMY_IF 1572 tristate "Simple big.LITTLE switcher user interface" 1573 depends on BL_SWITCHER && DEBUG_KERNEL 1574 help 1575 This is a simple and dummy char dev interface to control 1576 the big.LITTLE switcher core code. It is meant for 1577 debugging purposes only. 1578 1579choice 1580 prompt "Memory split" 1581 depends on MMU 1582 default VMSPLIT_3G 1583 help 1584 Select the desired split between kernel and user memory. 1585 1586 If you are not absolutely sure what you are doing, leave this 1587 option alone! 1588 1589 config VMSPLIT_3G 1590 bool "3G/1G user/kernel split" 1591 config VMSPLIT_2G 1592 bool "2G/2G user/kernel split" 1593 config VMSPLIT_1G 1594 bool "1G/3G user/kernel split" 1595endchoice 1596 1597config PAGE_OFFSET 1598 hex 1599 default PHYS_OFFSET if !MMU 1600 default 0x40000000 if VMSPLIT_1G 1601 default 0x80000000 if VMSPLIT_2G 1602 default 0xC0000000 1603 1604config NR_CPUS 1605 int "Maximum number of CPUs (2-32)" 1606 range 2 32 1607 depends on SMP 1608 default "4" 1609 1610config HOTPLUG_CPU 1611 bool "Support for hot-pluggable CPUs" 1612 depends on SMP 1613 help 1614 Say Y here to experiment with turning CPUs off and on. CPUs 1615 can be controlled through /sys/devices/system/cpu. 1616 1617config ARM_PSCI 1618 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1619 depends on CPU_V7 1620 help 1621 Say Y here if you want Linux to communicate with system firmware 1622 implementing the PSCI specification for CPU-centric power 1623 management operations described in ARM document number ARM DEN 1624 0022A ("Power State Coordination Interface System Software on 1625 ARM processors"). 1626 1627# The GPIO number here must be sorted by descending number. In case of 1628# a multiplatform kernel, we just want the highest value required by the 1629# selected platforms. 1630config ARCH_NR_GPIO 1631 int 1632 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1633 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX 1634 default 392 if ARCH_U8500 1635 default 352 if ARCH_VT8500 1636 default 288 if ARCH_SUNXI 1637 default 264 if MACH_H4700 1638 default 0 1639 help 1640 Maximum number of GPIOs in the system. 1641 1642 If unsure, leave the default value. 1643 1644source kernel/Kconfig.preempt 1645 1646config HZ_FIXED 1647 int 1648 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ 1649 ARCH_S5PV210 || ARCH_EXYNOS4 1650 default AT91_TIMER_HZ if ARCH_AT91 1651 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY 1652 default 0 1653 1654choice 1655 depends on HZ_FIXED = 0 1656 prompt "Timer frequency" 1657 1658config HZ_100 1659 bool "100 Hz" 1660 1661config HZ_200 1662 bool "200 Hz" 1663 1664config HZ_250 1665 bool "250 Hz" 1666 1667config HZ_300 1668 bool "300 Hz" 1669 1670config HZ_500 1671 bool "500 Hz" 1672 1673config HZ_1000 1674 bool "1000 Hz" 1675 1676endchoice 1677 1678config HZ 1679 int 1680 default HZ_FIXED if HZ_FIXED != 0 1681 default 100 if HZ_100 1682 default 200 if HZ_200 1683 default 250 if HZ_250 1684 default 300 if HZ_300 1685 default 500 if HZ_500 1686 default 1000 1687 1688config SCHED_HRTICK 1689 def_bool HIGH_RES_TIMERS 1690 1691config THUMB2_KERNEL 1692 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1693 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1694 default y if CPU_THUMBONLY 1695 select AEABI 1696 select ARM_ASM_UNIFIED 1697 select ARM_UNWIND 1698 help 1699 By enabling this option, the kernel will be compiled in 1700 Thumb-2 mode. A compiler/assembler that understand the unified 1701 ARM-Thumb syntax is needed. 1702 1703 If unsure, say N. 1704 1705config THUMB2_AVOID_R_ARM_THM_JUMP11 1706 bool "Work around buggy Thumb-2 short branch relocations in gas" 1707 depends on THUMB2_KERNEL && MODULES 1708 default y 1709 help 1710 Various binutils versions can resolve Thumb-2 branches to 1711 locally-defined, preemptible global symbols as short-range "b.n" 1712 branch instructions. 1713 1714 This is a problem, because there's no guarantee the final 1715 destination of the symbol, or any candidate locations for a 1716 trampoline, are within range of the branch. For this reason, the 1717 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1718 relocation in modules at all, and it makes little sense to add 1719 support. 1720 1721 The symptom is that the kernel fails with an "unsupported 1722 relocation" error when loading some modules. 1723 1724 Until fixed tools are available, passing 1725 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1726 code which hits this problem, at the cost of a bit of extra runtime 1727 stack usage in some cases. 1728 1729 The problem is described in more detail at: 1730 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1731 1732 Only Thumb-2 kernels are affected. 1733 1734 Unless you are sure your tools don't have this problem, say Y. 1735 1736config ARM_ASM_UNIFIED 1737 bool 1738 1739config AEABI 1740 bool "Use the ARM EABI to compile the kernel" 1741 help 1742 This option allows for the kernel to be compiled using the latest 1743 ARM ABI (aka EABI). This is only useful if you are using a user 1744 space environment that is also compiled with EABI. 1745 1746 Since there are major incompatibilities between the legacy ABI and 1747 EABI, especially with regard to structure member alignment, this 1748 option also changes the kernel syscall calling convention to 1749 disambiguate both ABIs and allow for backward compatibility support 1750 (selected with CONFIG_OABI_COMPAT). 1751 1752 To use this you need GCC version 4.0.0 or later. 1753 1754config OABI_COMPAT 1755 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1756 depends on AEABI && !THUMB2_KERNEL 1757 help 1758 This option preserves the old syscall interface along with the 1759 new (ARM EABI) one. It also provides a compatibility layer to 1760 intercept syscalls that have structure arguments which layout 1761 in memory differs between the legacy ABI and the new ARM EABI 1762 (only for non "thumb" binaries). This option adds a tiny 1763 overhead to all syscalls and produces a slightly larger kernel. 1764 1765 The seccomp filter system will not be available when this is 1766 selected, since there is no way yet to sensibly distinguish 1767 between calling conventions during filtering. 1768 1769 If you know you'll be using only pure EABI user space then you 1770 can say N here. If this option is not selected and you attempt 1771 to execute a legacy ABI binary then the result will be 1772 UNPREDICTABLE (in fact it can be predicted that it won't work 1773 at all). If in doubt say N. 1774 1775config ARCH_HAS_HOLES_MEMORYMODEL 1776 bool 1777 1778config ARCH_SPARSEMEM_ENABLE 1779 bool 1780 1781config ARCH_SPARSEMEM_DEFAULT 1782 def_bool ARCH_SPARSEMEM_ENABLE 1783 1784config ARCH_SELECT_MEMORY_MODEL 1785 def_bool ARCH_SPARSEMEM_ENABLE 1786 1787config HAVE_ARCH_PFN_VALID 1788 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1789 1790config HIGHMEM 1791 bool "High Memory Support" 1792 depends on MMU 1793 help 1794 The address space of ARM processors is only 4 Gigabytes large 1795 and it has to accommodate user address space, kernel address 1796 space as well as some memory mapped IO. That means that, if you 1797 have a large amount of physical memory and/or IO, not all of the 1798 memory can be "permanently mapped" by the kernel. The physical 1799 memory that is not permanently mapped is called "high memory". 1800 1801 Depending on the selected kernel/user memory split, minimum 1802 vmalloc space and actual amount of RAM, you may not need this 1803 option which should result in a slightly faster kernel. 1804 1805 If unsure, say n. 1806 1807config HIGHPTE 1808 bool "Allocate 2nd-level pagetables from highmem" 1809 depends on HIGHMEM 1810 1811config HW_PERF_EVENTS 1812 bool "Enable hardware performance counter support for perf events" 1813 depends on PERF_EVENTS 1814 default y 1815 help 1816 Enable hardware performance counter support for perf events. If 1817 disabled, perf events will use software events only. 1818 1819config SYS_SUPPORTS_HUGETLBFS 1820 def_bool y 1821 depends on ARM_LPAE 1822 1823config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1824 def_bool y 1825 depends on ARM_LPAE 1826 1827config ARCH_WANT_GENERAL_HUGETLB 1828 def_bool y 1829 1830source "mm/Kconfig" 1831 1832config FORCE_MAX_ZONEORDER 1833 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY 1834 range 11 64 if ARCH_SHMOBILE_LEGACY 1835 default "12" if SOC_AM33XX 1836 default "9" if SA1111 || ARCH_EFM32 1837 default "11" 1838 help 1839 The kernel memory allocator divides physically contiguous memory 1840 blocks into "zones", where each zone is a power of two number of 1841 pages. This option selects the largest power of two that the kernel 1842 keeps in the memory allocator. If you need to allocate very large 1843 blocks of physically contiguous memory, then you may need to 1844 increase this value. 1845 1846 This config option is actually maximum order plus one. For example, 1847 a value of 11 means that the largest free memory block is 2^10 pages. 1848 1849config ALIGNMENT_TRAP 1850 bool 1851 depends on CPU_CP15_MMU 1852 default y if !ARCH_EBSA110 1853 select HAVE_PROC_CPU if PROC_FS 1854 help 1855 ARM processors cannot fetch/store information which is not 1856 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1857 address divisible by 4. On 32-bit ARM processors, these non-aligned 1858 fetch/store instructions will be emulated in software if you say 1859 here, which has a severe performance impact. This is necessary for 1860 correct operation of some network protocols. With an IP-only 1861 configuration it is safe to say N, otherwise say Y. 1862 1863config UACCESS_WITH_MEMCPY 1864 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1865 depends on MMU 1866 default y if CPU_FEROCEON 1867 help 1868 Implement faster copy_to_user and clear_user methods for CPU 1869 cores where a 8-word STM instruction give significantly higher 1870 memory write throughput than a sequence of individual 32bit stores. 1871 1872 A possible side effect is a slight increase in scheduling latency 1873 between threads sharing the same address space if they invoke 1874 such copy operations with large buffers. 1875 1876 However, if the CPU data cache is using a write-allocate mode, 1877 this option is unlikely to provide any performance gain. 1878 1879config SECCOMP 1880 bool 1881 prompt "Enable seccomp to safely compute untrusted bytecode" 1882 ---help--- 1883 This kernel feature is useful for number crunching applications 1884 that may need to compute untrusted bytecode during their 1885 execution. By using pipes or other transports made available to 1886 the process as file descriptors supporting the read/write 1887 syscalls, it's possible to isolate those applications in 1888 their own address space using seccomp. Once seccomp is 1889 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1890 and the task is only allowed to execute a few safe syscalls 1891 defined by each seccomp mode. 1892 1893config SWIOTLB 1894 def_bool y 1895 1896config IOMMU_HELPER 1897 def_bool SWIOTLB 1898 1899config XEN_DOM0 1900 def_bool y 1901 depends on XEN 1902 1903config XEN 1904 bool "Xen guest support on ARM (EXPERIMENTAL)" 1905 depends on ARM && AEABI && OF 1906 depends on CPU_V7 && !CPU_V6 1907 depends on !GENERIC_ATOMIC64 1908 depends on MMU 1909 select ARM_PSCI 1910 select SWIOTLB_XEN 1911 select ARCH_DMA_ADDR_T_64BIT 1912 help 1913 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1914 1915endmenu 1916 1917menu "Boot options" 1918 1919config USE_OF 1920 bool "Flattened Device Tree support" 1921 select IRQ_DOMAIN 1922 select OF 1923 select OF_EARLY_FLATTREE 1924 help 1925 Include support for flattened device tree machine descriptions. 1926 1927config ATAGS 1928 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1929 default y 1930 help 1931 This is the traditional way of passing data to the kernel at boot 1932 time. If you are solely relying on the flattened device tree (or 1933 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1934 to remove ATAGS support from your kernel binary. If unsure, 1935 leave this to y. 1936 1937config DEPRECATED_PARAM_STRUCT 1938 bool "Provide old way to pass kernel parameters" 1939 depends on ATAGS 1940 help 1941 This was deprecated in 2001 and announced to live on for 5 years. 1942 Some old boot loaders still use this way. 1943 1944# Compressed boot loader in ROM. Yes, we really want to ask about 1945# TEXT and BSS so we preserve their values in the config files. 1946config ZBOOT_ROM_TEXT 1947 hex "Compressed ROM boot loader base address" 1948 default "0" 1949 help 1950 The physical address at which the ROM-able zImage is to be 1951 placed in the target. Platforms which normally make use of 1952 ROM-able zImage formats normally set this to a suitable 1953 value in their defconfig file. 1954 1955 If ZBOOT_ROM is not enabled, this has no effect. 1956 1957config ZBOOT_ROM_BSS 1958 hex "Compressed ROM boot loader BSS address" 1959 default "0" 1960 help 1961 The base address of an area of read/write memory in the target 1962 for the ROM-able zImage which must be available while the 1963 decompressor is running. It must be large enough to hold the 1964 entire decompressed kernel plus an additional 128 KiB. 1965 Platforms which normally make use of ROM-able zImage formats 1966 normally set this to a suitable value in their defconfig file. 1967 1968 If ZBOOT_ROM is not enabled, this has no effect. 1969 1970config ZBOOT_ROM 1971 bool "Compressed boot loader in ROM/flash" 1972 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1973 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1974 help 1975 Say Y here if you intend to execute your compressed kernel image 1976 (zImage) directly from ROM or flash. If unsure, say N. 1977 1978choice 1979 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" 1980 depends on ZBOOT_ROM && ARCH_SH7372 1981 default ZBOOT_ROM_NONE 1982 help 1983 Include experimental SD/MMC loading code in the ROM-able zImage. 1984 With this enabled it is possible to write the ROM-able zImage 1985 kernel image to an MMC or SD card and boot the kernel straight 1986 from the reset vector. At reset the processor Mask ROM will load 1987 the first part of the ROM-able zImage which in turn loads the 1988 rest the kernel image to RAM. 1989 1990config ZBOOT_ROM_NONE 1991 bool "No SD/MMC loader in zImage (EXPERIMENTAL)" 1992 help 1993 Do not load image from SD or MMC 1994 1995config ZBOOT_ROM_MMCIF 1996 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1997 help 1998 Load image from MMCIF hardware block. 1999 2000config ZBOOT_ROM_SH_MOBILE_SDHI 2001 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" 2002 help 2003 Load image from SDHI hardware block 2004 2005endchoice 2006 2007config ARM_APPENDED_DTB 2008 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 2009 depends on OF 2010 help 2011 With this option, the boot code will look for a device tree binary 2012 (DTB) appended to zImage 2013 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 2014 2015 This is meant as a backward compatibility convenience for those 2016 systems with a bootloader that can't be upgraded to accommodate 2017 the documented boot protocol using a device tree. 2018 2019 Beware that there is very little in terms of protection against 2020 this option being confused by leftover garbage in memory that might 2021 look like a DTB header after a reboot if no actual DTB is appended 2022 to zImage. Do not leave this option active in a production kernel 2023 if you don't intend to always append a DTB. Proper passing of the 2024 location into r2 of a bootloader provided DTB is always preferable 2025 to this option. 2026 2027config ARM_ATAG_DTB_COMPAT 2028 bool "Supplement the appended DTB with traditional ATAG information" 2029 depends on ARM_APPENDED_DTB 2030 help 2031 Some old bootloaders can't be updated to a DTB capable one, yet 2032 they provide ATAGs with memory configuration, the ramdisk address, 2033 the kernel cmdline string, etc. Such information is dynamically 2034 provided by the bootloader and can't always be stored in a static 2035 DTB. To allow a device tree enabled kernel to be used with such 2036 bootloaders, this option allows zImage to extract the information 2037 from the ATAG list and store it at run time into the appended DTB. 2038 2039choice 2040 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 2041 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 2042 2043config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 2044 bool "Use bootloader kernel arguments if available" 2045 help 2046 Uses the command-line options passed by the boot loader instead of 2047 the device tree bootargs property. If the boot loader doesn't provide 2048 any, the device tree bootargs property will be used. 2049 2050config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 2051 bool "Extend with bootloader kernel arguments" 2052 help 2053 The command-line arguments provided by the boot loader will be 2054 appended to the the device tree bootargs property. 2055 2056endchoice 2057 2058config CMDLINE 2059 string "Default kernel command string" 2060 default "" 2061 help 2062 On some architectures (EBSA110 and CATS), there is currently no way 2063 for the boot loader to pass arguments to the kernel. For these 2064 architectures, you should supply some command-line options at build 2065 time by entering them here. As a minimum, you should specify the 2066 memory size and the root device (e.g., mem=64M root=/dev/nfs). 2067 2068choice 2069 prompt "Kernel command line type" if CMDLINE != "" 2070 default CMDLINE_FROM_BOOTLOADER 2071 depends on ATAGS 2072 2073config CMDLINE_FROM_BOOTLOADER 2074 bool "Use bootloader kernel arguments if available" 2075 help 2076 Uses the command-line options passed by the boot loader. If 2077 the boot loader doesn't provide any, the default kernel command 2078 string provided in CMDLINE will be used. 2079 2080config CMDLINE_EXTEND 2081 bool "Extend bootloader kernel arguments" 2082 help 2083 The command-line arguments provided by the boot loader will be 2084 appended to the default kernel command string. 2085 2086config CMDLINE_FORCE 2087 bool "Always use the default kernel command string" 2088 help 2089 Always use the default kernel command string, even if the boot 2090 loader passes other arguments to the kernel. 2091 This is useful if you cannot or don't want to change the 2092 command-line options your boot loader passes to the kernel. 2093endchoice 2094 2095config XIP_KERNEL 2096 bool "Kernel Execute-In-Place from ROM" 2097 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 2098 help 2099 Execute-In-Place allows the kernel to run from non-volatile storage 2100 directly addressable by the CPU, such as NOR flash. This saves RAM 2101 space since the text section of the kernel is not loaded from flash 2102 to RAM. Read-write sections, such as the data section and stack, 2103 are still copied to RAM. The XIP kernel is not compressed since 2104 it has to run directly from flash, so it will take more space to 2105 store it. The flash address used to link the kernel object files, 2106 and for storing it, is configuration dependent. Therefore, if you 2107 say Y here, you must know the proper physical address where to 2108 store the kernel image depending on your own flash memory usage. 2109 2110 Also note that the make target becomes "make xipImage" rather than 2111 "make zImage" or "make Image". The final kernel binary to put in 2112 ROM memory will be arch/arm/boot/xipImage. 2113 2114 If unsure, say N. 2115 2116config XIP_PHYS_ADDR 2117 hex "XIP Kernel Physical Location" 2118 depends on XIP_KERNEL 2119 default "0x00080000" 2120 help 2121 This is the physical address in your flash memory the kernel will 2122 be linked for and stored to. This address is dependent on your 2123 own flash usage. 2124 2125config KEXEC 2126 bool "Kexec system call (EXPERIMENTAL)" 2127 depends on (!SMP || PM_SLEEP_SMP) 2128 help 2129 kexec is a system call that implements the ability to shutdown your 2130 current kernel, and to start another kernel. It is like a reboot 2131 but it is independent of the system firmware. And like a reboot 2132 you can start any kernel with it, not just Linux. 2133 2134 It is an ongoing process to be certain the hardware in a machine 2135 is properly shutdown, so do not be surprised if this code does not 2136 initially work for you. 2137 2138config ATAGS_PROC 2139 bool "Export atags in procfs" 2140 depends on ATAGS && KEXEC 2141 default y 2142 help 2143 Should the atags used to boot the kernel be exported in an "atags" 2144 file in procfs. Useful with kexec. 2145 2146config CRASH_DUMP 2147 bool "Build kdump crash kernel (EXPERIMENTAL)" 2148 help 2149 Generate crash dump after being started by kexec. This should 2150 be normally only set in special crash dump kernels which are 2151 loaded in the main kernel with kexec-tools into a specially 2152 reserved region and then later executed after a crash by 2153 kdump/kexec. The crash dump kernel must be compiled to a 2154 memory address not used by the main kernel 2155 2156 For more details see Documentation/kdump/kdump.txt 2157 2158config AUTO_ZRELADDR 2159 bool "Auto calculation of the decompressed kernel image address" 2160 help 2161 ZRELADDR is the physical address where the decompressed kernel 2162 image will be placed. If AUTO_ZRELADDR is selected, the address 2163 will be determined at run-time by masking the current IP with 2164 0xf8000000. This assumes the zImage being placed in the first 128MB 2165 from start of memory. 2166 2167endmenu 2168 2169menu "CPU Power Management" 2170 2171if ARCH_HAS_CPUFREQ 2172source "drivers/cpufreq/Kconfig" 2173endif 2174 2175source "drivers/cpuidle/Kconfig" 2176 2177endmenu 2178 2179menu "Floating point emulation" 2180 2181comment "At least one emulation must be selected" 2182 2183config FPE_NWFPE 2184 bool "NWFPE math emulation" 2185 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2186 ---help--- 2187 Say Y to include the NWFPE floating point emulator in the kernel. 2188 This is necessary to run most binaries. Linux does not currently 2189 support floating point hardware so you need to say Y here even if 2190 your machine has an FPA or floating point co-processor podule. 2191 2192 You may say N here if you are going to load the Acorn FPEmulator 2193 early in the bootup. 2194 2195config FPE_NWFPE_XP 2196 bool "Support extended precision" 2197 depends on FPE_NWFPE 2198 help 2199 Say Y to include 80-bit support in the kernel floating-point 2200 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2201 Note that gcc does not generate 80-bit operations by default, 2202 so in most cases this option only enlarges the size of the 2203 floating point emulator without any good reason. 2204 2205 You almost surely want to say N here. 2206 2207config FPE_FASTFPE 2208 bool "FastFPE math emulation (EXPERIMENTAL)" 2209 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2210 ---help--- 2211 Say Y here to include the FAST floating point emulator in the kernel. 2212 This is an experimental much faster emulator which now also has full 2213 precision for the mantissa. It does not support any exceptions. 2214 It is very simple, and approximately 3-6 times faster than NWFPE. 2215 2216 It should be sufficient for most programs. It may be not suitable 2217 for scientific calculations, but you have to check this for yourself. 2218 If you do not feel you need a faster FP emulation you should better 2219 choose NWFPE. 2220 2221config VFP 2222 bool "VFP-format floating point maths" 2223 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2224 help 2225 Say Y to include VFP support code in the kernel. This is needed 2226 if your hardware includes a VFP unit. 2227 2228 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2229 release notes and additional status information. 2230 2231 Say N if your target does not have VFP hardware. 2232 2233config VFPv3 2234 bool 2235 depends on VFP 2236 default y if CPU_V7 2237 2238config NEON 2239 bool "Advanced SIMD (NEON) Extension support" 2240 depends on VFPv3 && CPU_V7 2241 help 2242 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2243 Extension. 2244 2245config KERNEL_MODE_NEON 2246 bool "Support for NEON in kernel mode" 2247 depends on NEON && AEABI 2248 help 2249 Say Y to include support for NEON in kernel mode. 2250 2251endmenu 2252 2253menu "Userspace binary formats" 2254 2255source "fs/Kconfig.binfmt" 2256 2257config ARTHUR 2258 tristate "RISC OS personality" 2259 depends on !AEABI 2260 help 2261 Say Y here to include the kernel code necessary if you want to run 2262 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2263 experimental; if this sounds frightening, say N and sleep in peace. 2264 You can also say M here to compile this support as a module (which 2265 will be called arthur). 2266 2267endmenu 2268 2269menu "Power management options" 2270 2271source "kernel/power/Kconfig" 2272 2273config ARCH_SUSPEND_POSSIBLE 2274 depends on !ARCH_S5PC100 2275 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2276 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2277 def_bool y 2278 2279config ARM_CPU_SUSPEND 2280 def_bool PM_SLEEP 2281 2282endmenu 2283 2284source "net/Kconfig" 2285 2286source "drivers/Kconfig" 2287 2288source "fs/Kconfig" 2289 2290source "arch/arm/Kconfig.debug" 2291 2292source "security/Kconfig" 2293 2294source "crypto/Kconfig" 2295 2296source "lib/Kconfig" 2297 2298source "arch/arm/kvm/Kconfig" 2299